first commit
This commit is contained in:
HosuKim
1
Source/.staticdata/.hint
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1
Source/.staticdata/.hint
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||||
{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}}
|
||||
1
Source/.staticdata/.previous/20260407_213608/.hint
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1
Source/.staticdata/.previous/20260407_213608/.hint
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@@ -0,0 +1 @@
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||||
{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}}
|
||||
1
Source/.staticdata/.previous/20260407_213608/.spec
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1
Source/.staticdata/.previous/20260407_213608/.spec
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C:\ti\Project\K2APU_DCU_v019\Source\.spec
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@@ -0,0 +1 @@
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||||
{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]}
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||||
;
|
||||
;
|
||||
; PA 의 설정입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[PA]
|
||||
; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.
|
||||
; default 값은 N 입니다.
|
||||
CLEAN_MODE=N
|
||||
;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.
|
||||
; default 값은 N 입니다.
|
||||
AUTO_ENCODING_UTF8=N
|
||||
|
||||
; 프로젝트 DB 에 대한 초기화 쿼리
|
||||
INIT_QUERY=PRAGMA mmap_size=2147418112;
|
||||
|
||||
; 람다 코드를 CFG에 포함할지 여부입니다.
|
||||
; 초기 값은 'N' 입니다.
|
||||
DISABLE_LAMBDA_CFG=N
|
||||
|
||||
|
||||
; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성
|
||||
; 초기 값은 'Y' 입니다.
|
||||
MAKE_UNIQUE_REFINED_DIR=Y
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.
|
||||
;default 값은 Y 입니다.
|
||||
[CI]
|
||||
REINDEX_MODE=Y
|
||||
|
||||
;
|
||||
;
|
||||
; DFA 의 설정입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[DFA]
|
||||
DFA_ENABLE=Y
|
||||
SCFG_OUT=N
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||||
LIMIT_ITER=N
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||||
RESULT_OUT=N
|
||||
ITER_OUT=N
|
||||
TRANSFER_OUT=N
|
||||
FYCYC_ITER=40
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||||
;
|
||||
;
|
||||
; Abstract Interpreter 설정
|
||||
;-------------------------------------------------------------------------
|
||||
[ABSINT]
|
||||
; ENABLE WHEN CI
|
||||
ABSINT_ENABLE=Y
|
||||
; MUST | MAY
|
||||
ABSINT_STRATEGY=MUST
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; ExtendedDeclarations를 db에 저장할지 결정합니다.
|
||||
; db에 저장된 정보는 linking time에 사용됩니다.
|
||||
; default 값은 Y 입니다(Y or N).
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[ExtendedDeclaration]
|
||||
SAVE_TO_PROJECT_REPOSITORY=Y
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||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.
|
||||
; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.
|
||||
; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h
|
||||
; default 값은 SKIP_SYSTEM_MACRO 입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[REPORT]
|
||||
MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO
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||||
|
||||
;-------------------------------------------------------------------------
|
||||
; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,
|
||||
; 전처리 파일을 생성할지 여부.
|
||||
; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.
|
||||
; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.
|
||||
; 이 key가 없는 경우에도 Y로 동작함.
|
||||
GEN_PP_OUTPUT=Y
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; 아래는 FunctionUnit 들에 대해 옵션들입니다.
|
||||
; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.
|
||||
;
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[FunctionMapBuilder]
|
||||
SYMBOL_MAPPER=default
|
||||
;SYMBOL_MAPPER=physical
|
||||
; default
|
||||
; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[CFGWriter]
|
||||
; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.
|
||||
GML_OUT=N
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[MetricGenerator]
|
||||
; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N
|
||||
PHYSICAL_FUNCR=N
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[TestValidator]
|
||||
; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.
|
||||
CHECK_ALL=N
|
||||
CHECK_FUNCTION_MAP=N
|
||||
CHECK_CFG=N
|
||||
CHECK_FUNCTION_INFO=N
|
||||
CHECK_TYPE_INFO=N
|
||||
CHECK_USE_DEF=N
|
||||
TYPE_INFO_GML_OUT=N
|
||||
;-------------------------------------------------------------------------
|
||||
[ANALYSIS]
|
||||
; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.
|
||||
ANNOTATION=Y
|
||||
; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.
|
||||
RUN_PSIONIC=Y
|
||||
; 분석기에서 type 이름을 짧게 납기는 옵션입니다.
|
||||
OPTIMIZE=Y
|
||||
; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.
|
||||
USER_CODE_ONLY=N
|
||||
; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.
|
||||
RUN_PREPROC=Y
|
||||
; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.
|
||||
; ';' 를 구분자로 여러항목을 입력할 수 있습니다.
|
||||
OVER_APPROXIMATION=std::vector
|
||||
;-------------------------------------------------------------------------
|
||||
[ASTFactory]
|
||||
; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부
|
||||
; 초기 값은 'N' 입니다.
|
||||
ENABLE_LAMBDA_AS_UNKNOWN=N
|
||||
|
||||
;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.
|
||||
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|
||||
; CODESCROLL STATIC(2023/04/14)
|
||||
|
||||
; ===================================
|
||||
; ENGINE VERSION
|
||||
; ===================================
|
||||
; Specify one of semantic analysis engine versions(default: latest)
|
||||
; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...
|
||||
PSIONIC_ENGINE_VERSION=latest
|
||||
|
||||
; ===================================
|
||||
; REPORTING POLICY
|
||||
; ===================================
|
||||
; Report only defects with a confidence level of 50% or higher.
|
||||
;PSIONIC_MIN_SCORE=50
|
||||
|
||||
; Rank strategy (default: 0)
|
||||
; - 1: new ranking strategy
|
||||
;PSIONIC_RANK_SYSTEM_VERSION=0
|
||||
|
||||
; Whether to report unused function arguments (default: true)
|
||||
PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N
|
||||
|
||||
; Report only ranking n error (rank starts 1 to 5, default: 1)
|
||||
; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0
|
||||
;PSIONIC_REPORT_ILL_MALLOC_RANK=1
|
||||
|
||||
; Report when malloc size over n (default: 65535)
|
||||
;PSIONIC_INVALID_MALLOC_SIZE=65535
|
||||
|
||||
; __________________________________
|
||||
; LIMITATION HANDLING
|
||||
; Some source code features not considered in this analyzer,
|
||||
; how can I handle when reaching the limit.
|
||||
;
|
||||
; in Second
|
||||
; 60s * 60 = 1 hour(3600)
|
||||
; 1day(24hour) = 86400 sec
|
||||
; 6hour = 21600 sec
|
||||
; 12hour = 43200 sec
|
||||
;
|
||||
; (default: unlimited)
|
||||
; __________________________________
|
||||
;PSIONIC_TIMEOUT=86400
|
||||
;PSIONIC_TIMEOUT_MEMORY=21600
|
||||
;PSIONIC_TIMEOUT_VALUE=21600
|
||||
;PSIONIC_MAX_MEMORY=20480
|
||||
|
||||
; ===================================
|
||||
; TUNING ANALYSIS POWER
|
||||
; DO NOT MODIFY BELOW WITHOUT EXPERTS
|
||||
; IT WAS WELL TUNED FOR VARIOUS CODES
|
||||
; ===================================
|
||||
;PSIONIC_ENABLE_ROBUST=true
|
||||
;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200
|
||||
|
||||
; __________________________________
|
||||
; Common Scalability
|
||||
; __________________________________
|
||||
;PSIONIC_CLUSTER_MAX_SIZE=999999999
|
||||
;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true
|
||||
;PSIONIC_CLUSTER_COUNT=20
|
||||
;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true
|
||||
|
||||
; __________________________________
|
||||
; Value Analysis Precision
|
||||
; >> Default(Always Widening)
|
||||
; __________________________________
|
||||
;PSIONIC_WIDENING_LIMIT=0
|
||||
;PSIONIC_NARROWING_LIMIT=5
|
||||
;PSIONIC_VALUE_MAX_VISIT=1000
|
||||
;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1
|
||||
|
||||
; Collect relations only directed relation in expression (less precise)
|
||||
;PSIONIC_ENABLE_VAR_CLUSTER=false
|
||||
|
||||
; The main trade-off for precision and speed
|
||||
; 1, interval analysis (default)
|
||||
; 2, pentagon analysis
|
||||
; 3, octagon analysis
|
||||
;PSIONIC_ANALYSIS_POWER=1
|
||||
|
||||
|
||||
;ENABLE_RESIZE_CHAR_ARRAY=true
|
||||
|
||||
; __________________________________
|
||||
; FixPoint Strategy for a Memory
|
||||
; Analysis (WTO, Worklist)
|
||||
; >> Default(Worklist)
|
||||
; __________________________________
|
||||
;PSIONIC_WITH_MEM_WTO=false
|
||||
|
||||
; __________________________________
|
||||
; Memory Analysis Precision
|
||||
; __________________________________
|
||||
;PSIONIC_MEM_MAX_VISIT=10
|
||||
;PSIONIC_MEM_MAX_STATE=2048
|
||||
|
||||
|
||||
; __________________________________
|
||||
; Dataflow Analysis Precision
|
||||
; __________________________________
|
||||
;PSIONIC_DATAFLOW_MAX_VISIT=100000
|
||||
|
||||
|
||||
; __________________________________
|
||||
; Memory Analysis Scalability
|
||||
; __________________________________
|
||||
;PSIONIC_MEM_CALLEE_BOUND=50
|
||||
|
||||
|
||||
;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false
|
||||
;
|
||||
;ENABLE_MEM_GLOBAL_POINTER_NULL=true
|
||||
;ENABLE_MEM_GLOBAL_ROBUSTNESS=true
|
||||
;
|
||||
;
|
||||
; __________________________________
|
||||
; Control Engine Runtime
|
||||
; __________________________________
|
||||
; Analysis specific target cluster only
|
||||
;PSIONIC_TARGET_CLUSTER=10
|
||||
;PSIONIC_EXCEPT_CLUSTER
|
||||
|
||||
; Value Only = 3, Memory Only = 2, Enable All = 4
|
||||
;PSIONIC_RUN_LEVEL=4
|
||||
@@ -0,0 +1 @@
|
||||
{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]}
|
||||
140
Source/.staticdata/.previous/20260407_213608/K2DCU/config/ci.ini
Normal file
140
Source/.staticdata/.previous/20260407_213608/K2DCU/config/ci.ini
Normal file
@@ -0,0 +1,140 @@
|
||||
;
|
||||
;
|
||||
; PA 의 설정입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[PA]
|
||||
; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.
|
||||
; default 값은 N 입니다.
|
||||
CLEAN_MODE=N
|
||||
;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.
|
||||
; default 값은 N 입니다.
|
||||
AUTO_ENCODING_UTF8=N
|
||||
|
||||
; 프로젝트 DB 에 대한 초기화 쿼리
|
||||
INIT_QUERY=PRAGMA mmap_size=2147418112;
|
||||
|
||||
; 람다 코드를 CFG에 포함할지 여부입니다.
|
||||
; 초기 값은 'N' 입니다.
|
||||
DISABLE_LAMBDA_CFG=N
|
||||
|
||||
|
||||
; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성
|
||||
; 초기 값은 'Y' 입니다.
|
||||
MAKE_UNIQUE_REFINED_DIR=Y
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.
|
||||
;default 값은 Y 입니다.
|
||||
[CI]
|
||||
REINDEX_MODE=Y
|
||||
|
||||
;
|
||||
;
|
||||
; DFA 의 설정입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[DFA]
|
||||
DFA_ENABLE=Y
|
||||
SCFG_OUT=N
|
||||
LIMIT_ITER=N
|
||||
RESULT_OUT=N
|
||||
ITER_OUT=N
|
||||
TRANSFER_OUT=N
|
||||
FYCYC_ITER=40
|
||||
;
|
||||
;
|
||||
; Abstract Interpreter 설정
|
||||
;-------------------------------------------------------------------------
|
||||
[ABSINT]
|
||||
; ENABLE WHEN CI
|
||||
ABSINT_ENABLE=Y
|
||||
; MUST | MAY
|
||||
ABSINT_STRATEGY=MUST
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; ExtendedDeclarations를 db에 저장할지 결정합니다.
|
||||
; db에 저장된 정보는 linking time에 사용됩니다.
|
||||
; default 값은 Y 입니다(Y or N).
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[ExtendedDeclaration]
|
||||
SAVE_TO_PROJECT_REPOSITORY=Y
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.
|
||||
; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.
|
||||
; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h
|
||||
; default 값은 SKIP_SYSTEM_MACRO 입니다.
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[REPORT]
|
||||
MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,
|
||||
; 전처리 파일을 생성할지 여부.
|
||||
; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.
|
||||
; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.
|
||||
; 이 key가 없는 경우에도 Y로 동작함.
|
||||
GEN_PP_OUTPUT=Y
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
;
|
||||
; 아래는 FunctionUnit 들에 대해 옵션들입니다.
|
||||
; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.
|
||||
;
|
||||
;
|
||||
;-------------------------------------------------------------------------
|
||||
[FunctionMapBuilder]
|
||||
SYMBOL_MAPPER=default
|
||||
;SYMBOL_MAPPER=physical
|
||||
; default
|
||||
; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)
|
||||
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[CFGWriter]
|
||||
; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.
|
||||
GML_OUT=N
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[MetricGenerator]
|
||||
; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N
|
||||
PHYSICAL_FUNCR=N
|
||||
|
||||
;-------------------------------------------------------------------------
|
||||
[TestValidator]
|
||||
; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.
|
||||
CHECK_ALL=N
|
||||
CHECK_FUNCTION_MAP=N
|
||||
CHECK_CFG=N
|
||||
CHECK_FUNCTION_INFO=N
|
||||
CHECK_TYPE_INFO=N
|
||||
CHECK_USE_DEF=N
|
||||
TYPE_INFO_GML_OUT=N
|
||||
;-------------------------------------------------------------------------
|
||||
[ANALYSIS]
|
||||
; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.
|
||||
ANNOTATION=Y
|
||||
; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.
|
||||
RUN_PSIONIC=Y
|
||||
; 분석기에서 type 이름을 짧게 납기는 옵션입니다.
|
||||
OPTIMIZE=Y
|
||||
; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.
|
||||
USER_CODE_ONLY=N
|
||||
; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.
|
||||
RUN_PREPROC=Y
|
||||
; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.
|
||||
; ';' 를 구분자로 여러항목을 입력할 수 있습니다.
|
||||
OVER_APPROXIMATION=std::vector
|
||||
;-------------------------------------------------------------------------
|
||||
[ASTFactory]
|
||||
; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부
|
||||
; 초기 값은 'N' 입니다.
|
||||
ENABLE_LAMBDA_AS_UNKNOWN=N
|
||||
|
||||
;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.
|
||||
Binary file not shown.
@@ -0,0 +1,125 @@
|
||||
; CODESCROLL STATIC(2023/04/14)
|
||||
|
||||
; ===================================
|
||||
; ENGINE VERSION
|
||||
; ===================================
|
||||
; Specify one of semantic analysis engine versions(default: latest)
|
||||
; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...
|
||||
PSIONIC_ENGINE_VERSION=latest
|
||||
|
||||
; ===================================
|
||||
; REPORTING POLICY
|
||||
; ===================================
|
||||
; Report only defects with a confidence level of 50% or higher.
|
||||
;PSIONIC_MIN_SCORE=50
|
||||
|
||||
; Rank strategy (default: 0)
|
||||
; - 1: new ranking strategy
|
||||
;PSIONIC_RANK_SYSTEM_VERSION=0
|
||||
|
||||
; Whether to report unused function arguments (default: true)
|
||||
PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N
|
||||
|
||||
; Report only ranking n error (rank starts 1 to 5, default: 1)
|
||||
; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0
|
||||
;PSIONIC_REPORT_ILL_MALLOC_RANK=1
|
||||
|
||||
; Report when malloc size over n (default: 65535)
|
||||
;PSIONIC_INVALID_MALLOC_SIZE=65535
|
||||
|
||||
; __________________________________
|
||||
; LIMITATION HANDLING
|
||||
; Some source code features not considered in this analyzer,
|
||||
; how can I handle when reaching the limit.
|
||||
;
|
||||
; in Second
|
||||
; 60s * 60 = 1 hour(3600)
|
||||
; 1day(24hour) = 86400 sec
|
||||
; 6hour = 21600 sec
|
||||
; 12hour = 43200 sec
|
||||
;
|
||||
; (default: unlimited)
|
||||
; __________________________________
|
||||
;PSIONIC_TIMEOUT=86400
|
||||
;PSIONIC_TIMEOUT_MEMORY=21600
|
||||
;PSIONIC_TIMEOUT_VALUE=21600
|
||||
;PSIONIC_MAX_MEMORY=20480
|
||||
|
||||
; ===================================
|
||||
; TUNING ANALYSIS POWER
|
||||
; DO NOT MODIFY BELOW WITHOUT EXPERTS
|
||||
; IT WAS WELL TUNED FOR VARIOUS CODES
|
||||
; ===================================
|
||||
;PSIONIC_ENABLE_ROBUST=true
|
||||
;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200
|
||||
|
||||
; __________________________________
|
||||
; Common Scalability
|
||||
; __________________________________
|
||||
;PSIONIC_CLUSTER_MAX_SIZE=999999999
|
||||
;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true
|
||||
;PSIONIC_CLUSTER_COUNT=20
|
||||
;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true
|
||||
|
||||
; __________________________________
|
||||
; Value Analysis Precision
|
||||
; >> Default(Always Widening)
|
||||
; __________________________________
|
||||
;PSIONIC_WIDENING_LIMIT=0
|
||||
;PSIONIC_NARROWING_LIMIT=5
|
||||
;PSIONIC_VALUE_MAX_VISIT=1000
|
||||
;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1
|
||||
|
||||
; Collect relations only directed relation in expression (less precise)
|
||||
;PSIONIC_ENABLE_VAR_CLUSTER=false
|
||||
|
||||
; The main trade-off for precision and speed
|
||||
; 1, interval analysis (default)
|
||||
; 2, pentagon analysis
|
||||
; 3, octagon analysis
|
||||
;PSIONIC_ANALYSIS_POWER=1
|
||||
|
||||
|
||||
;ENABLE_RESIZE_CHAR_ARRAY=true
|
||||
|
||||
; __________________________________
|
||||
; FixPoint Strategy for a Memory
|
||||
; Analysis (WTO, Worklist)
|
||||
; >> Default(Worklist)
|
||||
; __________________________________
|
||||
;PSIONIC_WITH_MEM_WTO=false
|
||||
|
||||
; __________________________________
|
||||
; Memory Analysis Precision
|
||||
; __________________________________
|
||||
;PSIONIC_MEM_MAX_VISIT=10
|
||||
;PSIONIC_MEM_MAX_STATE=2048
|
||||
|
||||
|
||||
; __________________________________
|
||||
; Dataflow Analysis Precision
|
||||
; __________________________________
|
||||
;PSIONIC_DATAFLOW_MAX_VISIT=100000
|
||||
|
||||
|
||||
; __________________________________
|
||||
; Memory Analysis Scalability
|
||||
; __________________________________
|
||||
;PSIONIC_MEM_CALLEE_BOUND=50
|
||||
|
||||
|
||||
;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false
|
||||
;
|
||||
;ENABLE_MEM_GLOBAL_POINTER_NULL=true
|
||||
;ENABLE_MEM_GLOBAL_ROBUSTNESS=true
|
||||
;
|
||||
;
|
||||
; __________________________________
|
||||
; Control Engine Runtime
|
||||
; __________________________________
|
||||
; Analysis specific target cluster only
|
||||
;PSIONIC_TARGET_CLUSTER=10
|
||||
;PSIONIC_EXCEPT_CLUSTER
|
||||
|
||||
; Value Only = 3, Memory Only = 2, Enable All = 4
|
||||
;PSIONIC_RUN_LEVEL=4
|
||||
@@ -0,0 +1,63 @@
|
||||
#ifndef SOURCE_OPER_H_
|
||||
#define SOURCE_OPER_H_
|
||||
|
||||
typedef struct ClassLedPattern
|
||||
{
|
||||
Uint16 Fault;
|
||||
Uint16 Operation;
|
||||
Uint16 Stop;
|
||||
} CLedPattern;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_APU_OPER_BOOT = 0U, // 0 부팅
|
||||
IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화
|
||||
IDX_APU_OPER_POST, // 2 자체 진단
|
||||
IDX_APU_OPER_EMERGENCY, // 3 비상 정지
|
||||
IDX_APU_OPER_STANDBY, // 4 대기
|
||||
IDX_APU_OPER_READY, // 5 준비 상태
|
||||
IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열
|
||||
IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동
|
||||
IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도
|
||||
IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기
|
||||
IDX_APU_OPER_GENERATING, // 10 발전 시작
|
||||
IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시)
|
||||
IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단
|
||||
} E_IDX_APU_OPER;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ECU_STAT_STANDBY = 0U, // 0
|
||||
IDX_ECU_STAT_STARTING, // 1
|
||||
IDX_ECU_STAT_IDLE, // 2
|
||||
IDX_ECU_STAT_OPERATION, // 3
|
||||
IDX_ECU_STAT_DERATING, // 4
|
||||
IDX_ECU_STAT_COOLDOWN, // 5
|
||||
IDX_ECU_STAT_STOP // 6
|
||||
} E_IDX_ECU_STAT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_GCU_CMD_STOP = 0U, // 0
|
||||
IDX_GCU_CMD_CRANKING, // 1
|
||||
IDX_GCU_CMD_STOP_CRANKING, // 2
|
||||
IDX_GCU_CMD_GENERATING // 3
|
||||
} E_IDX_GCU_CMD;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ECU_CMD_STOP = 0U, // 0
|
||||
IDX_ECU_CMD_START, // 1
|
||||
IDX_ECU_CMD_EMERGENCY // 2
|
||||
} E_IDX_ECU_CMD;
|
||||
|
||||
void CApuOperProcedure(void);
|
||||
void CDebugModeProcedure(void);
|
||||
void CLedControlProcedure(void);
|
||||
int16 CGetEngCoolantTemperature(void);
|
||||
Uint16 CGetGeneratorRpm(void);
|
||||
Uint16 CGetEngineActualRpm(void);
|
||||
void CSetGcuCommand(Uint16 Command);
|
||||
void CSetEcuCommand(Uint16 Command);
|
||||
|
||||
#endif /* SOURCE_OPER_H_ */
|
||||
@@ -0,0 +1,233 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 22, 2007 10:40:22 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2c.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
|
||||
// Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_I2C_H
|
||||
#define DSP2833x_I2C_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// I2C interrupt vector register bit definitions
|
||||
//
|
||||
struct I2CISRC_BITS { // bits description
|
||||
Uint16 INTCODE:3; // 2:0 Interrupt code
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union I2CISRC_REG {
|
||||
Uint16 all;
|
||||
struct I2CISRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C interrupt mask register bit definitions
|
||||
//
|
||||
struct I2CIER_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration lost interrupt
|
||||
Uint16 NACK:1; // 1 No ack interrupt
|
||||
Uint16 ARDY:1; // 2 Register access ready interrupt
|
||||
Uint16 RRDY:1; // 3 Recieve data ready interrupt
|
||||
Uint16 XRDY:1; // 4 Transmit data ready interrupt
|
||||
Uint16 SCD:1; // 5 Stop condition detection
|
||||
Uint16 AAS:1; // 6 Address as slave
|
||||
Uint16 rsvd:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union I2CIER_REG {
|
||||
Uint16 all;
|
||||
struct I2CIER_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C status register bit definitions
|
||||
//
|
||||
struct I2CSTR_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration lost interrupt
|
||||
Uint16 NACK:1; // 1 No ack interrupt
|
||||
Uint16 ARDY:1; // 2 Register access ready interrupt
|
||||
Uint16 RRDY:1; // 3 Recieve data ready interrupt
|
||||
Uint16 XRDY:1; // 4 Transmit data ready interrupt
|
||||
Uint16 SCD:1; // 5 Stop condition detection
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 AD0:1; // 8 Address Zero
|
||||
Uint16 AAS:1; // 9 Address as slave
|
||||
Uint16 XSMT:1; // 10 XMIT shift empty
|
||||
Uint16 RSFULL:1; // 11 Recieve shift full
|
||||
Uint16 BB:1; // 12 Bus busy
|
||||
Uint16 NACKSNT:1; // 13 A no ack sent
|
||||
Uint16 SDIR:1; // 14 Slave direction
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CSTR_REG {
|
||||
Uint16 all;
|
||||
struct I2CSTR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C mode control register bit definitions
|
||||
//
|
||||
struct I2CMDR_BITS { // bits description
|
||||
Uint16 BC:3; // 2:0 Bit count
|
||||
Uint16 FDF:1; // 3 Free data format
|
||||
Uint16 STB:1; // 4 Start byte
|
||||
Uint16 IRS:1; // 5 I2C Reset not
|
||||
Uint16 DLB:1; // 6 Digital loopback
|
||||
Uint16 RM:1; // 7 Repeat mode
|
||||
Uint16 XA:1; // 8 Expand address
|
||||
Uint16 TRX:1; // 9 Transmitter/reciever
|
||||
Uint16 MST:1; // 10 Master/slave
|
||||
Uint16 STP:1; // 11 Stop condition
|
||||
Uint16 rsvd1:1; // 12 reserved
|
||||
Uint16 STT:1; // 13 Start condition
|
||||
Uint16 FREE:1; // 14 Emulation mode
|
||||
Uint16 NACKMOD:1; // 15 No Ack mode
|
||||
};
|
||||
|
||||
union I2CMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CMDR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C extended mode control register bit definitions
|
||||
//
|
||||
struct I2CEMDR_BITS { // bits description
|
||||
Uint16 BCM:1; // 0 Backward compatibility mode
|
||||
Uint16 rsvd:15; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CEMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CEMDR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C pre-scaler register bit definitions
|
||||
//
|
||||
struct I2CPSC_BITS { // bits description
|
||||
Uint16 IPSC:8; // 7:0 pre-scaler
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union I2CPSC_REG {
|
||||
Uint16 all;
|
||||
struct I2CPSC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TX FIFO control register bit definitions
|
||||
//
|
||||
struct I2CFFTX_BITS { // bits description
|
||||
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
|
||||
Uint16 TXFFINTCLR:1; // 6 FIFO clear
|
||||
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO level status
|
||||
Uint16 TXFFRST:1; // 13 FIFO reset
|
||||
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
|
||||
Uint16 rsvd1:1; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CFFTX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RX FIFO control register bit definitions
|
||||
//
|
||||
struct I2CFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
|
||||
Uint16 RXFFINTCLR:1; // 6 FIFO clear
|
||||
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO level
|
||||
Uint16 RXFFRST:1; // 13 FIFO reset
|
||||
Uint16 rsvd1:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union I2CFFRX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFRX_BITS bit;
|
||||
};
|
||||
|
||||
struct I2C_REGS {
|
||||
Uint16 I2COAR; // Own address register
|
||||
union I2CIER_REG I2CIER; // Interrupt enable
|
||||
union I2CSTR_REG I2CSTR; // Interrupt status
|
||||
Uint16 I2CCLKL; // Clock divider low
|
||||
Uint16 I2CCLKH; // Clock divider high
|
||||
Uint16 I2CCNT; // Data count
|
||||
Uint16 I2CDRR; // Data recieve
|
||||
Uint16 I2CSAR; // Slave address
|
||||
Uint16 I2CDXR; // Data transmit
|
||||
union I2CMDR_REG I2CMDR; // Mode
|
||||
union I2CISRC_REG I2CISRC; // Interrupt source
|
||||
union I2CEMDR_REG I2CEMDR; // Extended Mode
|
||||
union I2CPSC_REG I2CPSC; // Pre-scaler
|
||||
Uint16 rsvd2[19]; // reserved
|
||||
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
|
||||
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
|
||||
};
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct I2C_REGS I2caRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_I2C_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,243 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:45:39 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm_defines.h
|
||||
//
|
||||
// TITLE: #defines used in ePWM examples examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EPWM_DEFINES_H
|
||||
#define DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// TBCTL (Time-Base Control)
|
||||
//
|
||||
// CTRMODE bits
|
||||
//
|
||||
#define TB_COUNT_UP 0x0
|
||||
#define TB_COUNT_DOWN 0x1
|
||||
#define TB_COUNT_UPDOWN 0x2
|
||||
#define TB_FREEZE 0x3
|
||||
|
||||
//
|
||||
// PHSEN bit
|
||||
//
|
||||
#define TB_DISABLE 0x0
|
||||
#define TB_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PRDLD bit
|
||||
//
|
||||
#define TB_SHADOW 0x0
|
||||
#define TB_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// SYNCOSEL bits
|
||||
//
|
||||
#define TB_SYNC_IN 0x0
|
||||
#define TB_CTR_ZERO 0x1
|
||||
#define TB_CTR_CMPB 0x2
|
||||
#define TB_SYNC_DISABLE 0x3
|
||||
|
||||
//
|
||||
// HSPCLKDIV and CLKDIV bits
|
||||
//
|
||||
#define TB_DIV1 0x0
|
||||
#define TB_DIV2 0x1
|
||||
#define TB_DIV4 0x2
|
||||
|
||||
//
|
||||
// PHSDIR bit
|
||||
//
|
||||
#define TB_DOWN 0x0
|
||||
#define TB_UP 0x1
|
||||
|
||||
//
|
||||
// CMPCTL (Compare Control)
|
||||
//
|
||||
// LOADAMODE and LOADBMODE bits
|
||||
//
|
||||
#define CC_CTR_ZERO 0x0
|
||||
#define CC_CTR_PRD 0x1
|
||||
#define CC_CTR_ZERO_PRD 0x2
|
||||
#define CC_LD_DISABLE 0x3
|
||||
|
||||
//
|
||||
// SHDWAMODE and SHDWBMODE bits
|
||||
//
|
||||
#define CC_SHADOW 0x0
|
||||
#define CC_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// AQCTLA and AQCTLB (Action Qualifier Control)
|
||||
//
|
||||
// ZRO, PRD, CAU, CAD, CBU, CBD bits
|
||||
//
|
||||
#define AQ_NO_ACTION 0x0
|
||||
#define AQ_CLEAR 0x1
|
||||
#define AQ_SET 0x2
|
||||
#define AQ_TOGGLE 0x3
|
||||
|
||||
//
|
||||
// DBCTL (Dead-Band Control)
|
||||
//
|
||||
// OUT MODE bits
|
||||
//
|
||||
#define DB_DISABLE 0x0
|
||||
#define DBB_ENABLE 0x1
|
||||
#define DBA_ENABLE 0x2
|
||||
#define DB_FULL_ENABLE 0x3
|
||||
|
||||
//
|
||||
// POLSEL bits
|
||||
//
|
||||
#define DB_ACTV_HI 0x0
|
||||
#define DB_ACTV_LOC 0x1
|
||||
#define DB_ACTV_HIC 0x2
|
||||
#define DB_ACTV_LO 0x3
|
||||
|
||||
//
|
||||
// IN MODE
|
||||
//
|
||||
#define DBA_ALL 0x0
|
||||
#define DBB_RED_DBA_FED 0x1
|
||||
#define DBA_RED_DBB_FED 0x2
|
||||
#define DBB_ALL 0x3
|
||||
|
||||
//
|
||||
// CHPCTL (chopper control)
|
||||
//
|
||||
// CHPEN bit
|
||||
//
|
||||
#define CHP_DISABLE 0x0
|
||||
#define CHP_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHPFREQ bits
|
||||
//
|
||||
#define CHP_DIV1 0x0
|
||||
#define CHP_DIV2 0x1
|
||||
#define CHP_DIV3 0x2
|
||||
#define CHP_DIV4 0x3
|
||||
#define CHP_DIV5 0x4
|
||||
#define CHP_DIV6 0x5
|
||||
#define CHP_DIV7 0x6
|
||||
#define CHP_DIV8 0x7
|
||||
|
||||
//
|
||||
// CHPDUTY bits
|
||||
//
|
||||
#define CHP1_8TH 0x0
|
||||
#define CHP2_8TH 0x1
|
||||
#define CHP3_8TH 0x2
|
||||
#define CHP4_8TH 0x3
|
||||
#define CHP5_8TH 0x4
|
||||
#define CHP6_8TH 0x5
|
||||
#define CHP7_8TH 0x6
|
||||
|
||||
//
|
||||
// TZSEL (Trip Zone Select)
|
||||
//
|
||||
// CBCn and OSHTn bits
|
||||
//
|
||||
#define TZ_DISABLE 0x0
|
||||
#define TZ_ENABLE 0x1
|
||||
|
||||
//
|
||||
// TZCTL (Trip Zone Control)
|
||||
//
|
||||
// TZA and TZB bits
|
||||
//
|
||||
#define TZ_HIZ 0x0
|
||||
#define TZ_FORCE_HI 0x1
|
||||
#define TZ_FORCE_LO 0x2
|
||||
#define TZ_NO_CHANGE 0x3
|
||||
|
||||
//
|
||||
// ETSEL (Event Trigger Select)
|
||||
//
|
||||
#define ET_CTR_ZERO 0x1
|
||||
#define ET_CTR_PRD 0x2
|
||||
#define ET_CTRU_CMPA 0x4
|
||||
#define ET_CTRD_CMPA 0x5
|
||||
#define ET_CTRU_CMPB 0x6
|
||||
#define ET_CTRD_CMPB 0x7
|
||||
|
||||
//
|
||||
// ETPS (Event Trigger Pre-scale)
|
||||
//
|
||||
// INTPRD, SOCAPRD, SOCBPRD bits
|
||||
//
|
||||
#define ET_DISABLE 0x0
|
||||
#define ET_1ST 0x1
|
||||
#define ET_2ND 0x2
|
||||
#define ET_3RD 0x3
|
||||
|
||||
//
|
||||
// HRPWM (High Resolution PWM)
|
||||
//
|
||||
// HRCNFG
|
||||
//
|
||||
#define HR_Disable 0x0
|
||||
#define HR_REP 0x1
|
||||
#define HR_FEP 0x2
|
||||
#define HR_BEP 0x3
|
||||
|
||||
#define HR_CMP 0x0
|
||||
#define HR_PHS 0x1
|
||||
|
||||
#define HR_CTR_ZERO 0x0
|
||||
#define HR_CTR_PRD 0x1
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,156 @@
|
||||
#ifndef SOURCE_DISPLAY_H_
|
||||
#define SOURCE_DISPLAY_H_
|
||||
|
||||
#define ZONE6_DAT *(volatile Uint16*)0x00100001
|
||||
#define ZONE6_COM *(volatile Uint16*)0x00100000
|
||||
|
||||
#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127
|
||||
#define OLED_HEIGHT (64U)
|
||||
#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7
|
||||
|
||||
#define TXT_ENG_WIDTH (6U)
|
||||
#define TXT_ENG_HEIGHT (12U)
|
||||
|
||||
#define TXT_TYPE_ENG (0U)
|
||||
#define TXT_TYPE_ETC (1U)
|
||||
|
||||
#define TXT_MAX_LEN (22U)
|
||||
#define TXT_LINE_LEN (5U)
|
||||
|
||||
#define OLED_LOAD_PROGRESS_X (14U)
|
||||
#define OLED_LOAD_PROGRESS_Y (52U)
|
||||
#define OLED_LOAD_PROGRESS_W (114U)
|
||||
#define OLED_LOAD_PROGRESS_H (10U)
|
||||
|
||||
#define MODE_COMMAND (0U)
|
||||
#define MODE_DATA (1U)
|
||||
|
||||
#define DIR_UP (1U)
|
||||
#define DIR_DOWN (0U)
|
||||
|
||||
typedef signed char int8;
|
||||
typedef unsigned char Uint8;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_LINE_TITLE = 0U,
|
||||
IDX_OLED_LINE_1 = 14U,
|
||||
IDX_OLED_LINE_2 = 27U,
|
||||
IDX_OLED_LINE_3 = 40U,
|
||||
IDX_OLED_LINE_4 = 53U
|
||||
} E_IDX_OLED_LINE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_ROW_0 = 0U,
|
||||
IDX_OLED_ROW_1,
|
||||
IDX_OLED_ROW_2,
|
||||
IDX_OLED_ROW_3,
|
||||
IDX_OLED_ROW_4
|
||||
} E_IDX_OLED_ROW;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_PASS_DIGIT_1 = 0U,
|
||||
IDX_OLED_PASS_DIGIT_2,
|
||||
IDX_OLED_PASS_DIGIT_3,
|
||||
IDX_OLED_PASS_DIGIT_4
|
||||
} E_IDX_OLED_PASS;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_PAGE_APU1 = 0U, // 0
|
||||
IDX_OLED_PAGE_APU2, // 1
|
||||
IDX_OLED_PAGE_MENU1, // 2
|
||||
IDX_OLED_PAGE_MENU2, // 3
|
||||
IDX_OLED_PAGE_TEMP, // 4
|
||||
IDX_OLED_PAGE_SENSOR1, // 5
|
||||
IDX_OLED_PAGE_SENSOR2, // 6
|
||||
IDX_OLED_PAGE_SENSOR3, // 7
|
||||
IDX_OLED_PAGE_SENSOR4, // 8
|
||||
IDX_OLED_PAGE_WARNING1, // 9
|
||||
IDX_OLED_PAGE_WARNING2, // 10
|
||||
IDX_OLED_PAGE_FAULT1, // 11
|
||||
IDX_OLED_PAGE_FAULT2, // 12
|
||||
IDX_OLED_PAGE_FAULT3, // 13
|
||||
IDX_OLED_PAGE_FAULT4, // 14
|
||||
IDX_OLED_PAGE_FAULT5, // 15
|
||||
IDX_OLED_PAGE_FAULT6, // 16
|
||||
IDX_OLED_PAGE_FAULT7, // 17
|
||||
IDX_OLED_PAGE_RESET_ALARM, // 18
|
||||
IDX_OLED_PAGE_PASSWORD, // 19
|
||||
IDX_OLED_PAGE_MAINTENANCE, // 20
|
||||
IDX_OLED_PAGE_VERSION, // 21
|
||||
IDX_OLED_PAGE_KEY_TEST, // 21
|
||||
IDX_OLED_PAGE_SHUTDOWN, // 23
|
||||
IDX_OLED_PAGE_MAX
|
||||
} E_IDX_OLED_PAGE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_MENU_APU = 0U, // 0
|
||||
IDX_OLED_MENU_TEMP, // 1
|
||||
IDX_OLED_MENU_SENSOR, // 2
|
||||
IDX_OLED_MENU_WARNING, // 3
|
||||
} E_IDX_OLED_MENU1;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_MENU_FAULT = 0U, // 0
|
||||
IDX_OLED_MENU_RESET, // 1
|
||||
IDX_OLED_MENU_DEBUG // 2
|
||||
} E_IDX_OLED_MENU2;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_LINE_FOCUS_1 = 0U,
|
||||
IDX_OLED_LINE_FOCUS_2,
|
||||
IDX_OLED_LINE_FOCUS_3,
|
||||
IDX_OLED_LINE_FOCUS_4
|
||||
} E_IDX_OLED_LINE_FOCUS;
|
||||
|
||||
typedef struct ClassPageHandler
|
||||
{
|
||||
Uint16 uiPage;
|
||||
void (*pAction) (void); // PageTable 참조
|
||||
} CPageHandler;
|
||||
|
||||
typedef struct ClassOledOperValue
|
||||
{
|
||||
Uint16 uiBuff[OLED_WIDTH][OLED_PAGE];
|
||||
Uint16 uiPageNum;
|
||||
Uint16 uiOldPageNum;
|
||||
Uint16 uiFocusLine;
|
||||
Uint16 uiPrevFocusLine;
|
||||
Uint16 uiFocusDigit;
|
||||
Uint16 uiProgressValue;
|
||||
Uint16 uiProgressDone;
|
||||
Uint16 uiResetAlarmAnswer;
|
||||
Uint16 uiResetHourAnswer;
|
||||
int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN];
|
||||
int8 cAlignBuffer[TXT_MAX_LEN];
|
||||
struct
|
||||
{
|
||||
Uint16 TxtColor;
|
||||
Uint16 BgColor;
|
||||
} Color;
|
||||
struct
|
||||
{
|
||||
Uint16 X;
|
||||
Uint16 Y;
|
||||
} Point;
|
||||
} COledOperValue;
|
||||
|
||||
void CInitXintf(void);
|
||||
void CInitOled(void);
|
||||
void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height);
|
||||
void CDisplayPostFail(void);
|
||||
void CSetPage(Uint16 PageNum);
|
||||
void CInitKeyOperValue(void);
|
||||
void CInitializePage(void);
|
||||
void COledBufferReset(void);
|
||||
void CDisplayAntiNoiseRefresh(void);
|
||||
|
||||
extern COledOperValue OledOperValue;
|
||||
|
||||
#endif /* SOURCE_DISPLAY_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c;
|
||||
extern unsigned int codescroll_built_in_line_macro;
|
||||
@@ -0,0 +1,208 @@
|
||||
// TI File $Revision: /main/3 $
|
||||
// Checkin $Date: April 17, 2008 11:08:27 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Spi.h
|
||||
//
|
||||
// TITLE: DSP2833x Device SPI Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SPI_H
|
||||
#define DSP2833x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// SPI Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// SPI FIFO Transmit register bit definitions
|
||||
//
|
||||
struct SPIFFTX_BITS { // bit description
|
||||
Uint16 TXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 TXFFINT:1; // 7 INT flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO status
|
||||
Uint16 TXFIFO:1; // 13 FIFO reset
|
||||
Uint16 SPIFFENA:1; // 14 Enhancement enable
|
||||
Uint16 SPIRST:1; // 15 Reset SPI
|
||||
};
|
||||
|
||||
union SPIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI FIFO recieve register bit definitions
|
||||
//
|
||||
struct SPIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 RXFFINT:1; // 7 INT flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO status
|
||||
Uint16 RXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
|
||||
Uint16 RXFFOVF:1; // 15 FIFO overflow
|
||||
};
|
||||
|
||||
union SPIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI FIFO control register bit definitions
|
||||
//
|
||||
struct SPIFFCT_BITS { // bits description
|
||||
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI configuration register bit definitions
|
||||
//
|
||||
struct SPICCR_BITS { // bits description
|
||||
Uint16 SPICHAR:4; // 3:0 Character length control
|
||||
Uint16 SPILBK:1; // 4 Loop-back enable/disable
|
||||
Uint16 rsvd1:1; // 5 reserved
|
||||
Uint16 CLKPOLARITY:1; // 6 Clock polarity
|
||||
Uint16 SPISWRESET:1; // 7 SPI SW Reset
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPICCR_REG {
|
||||
Uint16 all;
|
||||
struct SPICCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI operation control register bit definitions
|
||||
//
|
||||
struct SPICTL_BITS { // bits description
|
||||
Uint16 SPIINTENA:1; // 0 Interrupt enable
|
||||
Uint16 TALK:1; // 1 Master/Slave transmit enable
|
||||
Uint16 MASTER_SLAVE:1; // 2 Network control mode
|
||||
Uint16 CLK_PHASE:1; // 3 Clock phase select
|
||||
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
|
||||
Uint16 rsvd:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union SPICTL_REG {
|
||||
Uint16 all;
|
||||
struct SPICTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI status register bit definitions
|
||||
//
|
||||
struct SPISTS_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
|
||||
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
|
||||
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPISTS_REG {
|
||||
Uint16 all;
|
||||
struct SPISTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI priority control register bit definitions
|
||||
//
|
||||
struct SPIPRI_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 FREE:1; // 4 Free emulation mode control
|
||||
Uint16 SOFT:1; // 5 Soft emulation mode control
|
||||
Uint16 rsvd2:1; // 6 reserved
|
||||
Uint16 rsvd3:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union SPIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SPIPRI_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI Register File
|
||||
//
|
||||
struct SPI_REGS {
|
||||
union SPICCR_REG SPICCR; // Configuration register
|
||||
union SPICTL_REG SPICTL; // Operation control register
|
||||
union SPISTS_REG SPISTS; // Status register
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 SPIBRR; // Baud Rate
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 SPIRXEMU; // Emulation buffer
|
||||
Uint16 SPIRXBUF; // Serial input buffer
|
||||
Uint16 SPITXBUF; // Serial output buffer
|
||||
Uint16 SPIDAT; // Serial data
|
||||
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
|
||||
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
|
||||
union SPIFFCT_REG SPIFFCT; // FIFO control register
|
||||
Uint16 rsvd3[2]; // reserved
|
||||
union SPIPRI_REG SPIPRI; // FIFO Priority control
|
||||
};
|
||||
|
||||
//
|
||||
// SPI External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SPI_REGS SpiaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SPI_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,131 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: April 15, 2009 10:05:17 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DevEmu.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Emulation Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEV_EMU_H
|
||||
#define DSP2833x_DEV_EMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Device Emulation Register Bit Definitions:
|
||||
//
|
||||
|
||||
//
|
||||
// Device Configuration Register Bit Definitions
|
||||
//
|
||||
struct DEVICECNF_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 reserved
|
||||
Uint16 VMAPS:1; // 3 VMAP Status
|
||||
Uint16 rsvd2:1; // 4 reserved
|
||||
Uint16 XRSn:1; // 5 XRSn Signal Status
|
||||
Uint16 rsvd3:10; // 15:6
|
||||
Uint16 rsvd4:3; // 18:16
|
||||
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
|
||||
Uint16 rsvd5:7; // 26:20 reserved
|
||||
Uint16 TRSTN:1; // 27 Status of TRSTn signal
|
||||
Uint16 rsvd6:4; // 31:28 reserved
|
||||
};
|
||||
|
||||
union DEVICECNF_REG {
|
||||
Uint32 all;
|
||||
struct DEVICECNF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// CLASSID
|
||||
//
|
||||
struct CLASSID_BITS { // bits description
|
||||
Uint16 CLASSNO:8; // 7:0 Class Number
|
||||
Uint16 PARTTYPE:8; // 15:8 Part Type
|
||||
};
|
||||
|
||||
union CLASSID_REG {
|
||||
Uint16 all;
|
||||
struct CLASSID_BITS bit;
|
||||
};
|
||||
|
||||
struct DEV_EMU_REGS {
|
||||
union DEVICECNF_REG DEVICECNF; // device configuration
|
||||
union CLASSID_REG CLASSID; // Class ID
|
||||
Uint16 REVID; // Device ID
|
||||
Uint16 PROTSTART; // Write-Read protection start
|
||||
Uint16 PROTRANGE; // Write-Read protection range
|
||||
Uint16 rsvd2[202];
|
||||
};
|
||||
|
||||
//
|
||||
// PARTID
|
||||
//
|
||||
struct PARTID_BITS { // bits description
|
||||
Uint16 PARTNO:8; // 7:0 Part Number
|
||||
Uint16 PARTTYPE:8; // 15:8 Part Type
|
||||
};
|
||||
|
||||
union PARTID_REG {
|
||||
Uint16 all;
|
||||
struct PARTID_BITS bit;
|
||||
};
|
||||
|
||||
struct PARTID_REGS {
|
||||
union PARTID_REG PARTID; // Part ID
|
||||
};
|
||||
|
||||
//
|
||||
// Device Emulation Register References & Function Declarations
|
||||
//
|
||||
extern volatile struct DEV_EMU_REGS DevEmuRegs;
|
||||
extern volatile struct PARTID_REGS PartIdRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEV_EMU_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,179 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: April 16, 2008 17:16:47 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2cExample.h
|
||||
//
|
||||
// TITLE: 2833x I2C Example Code Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_I2C_DEFINES_H
|
||||
#define DSP2833x_I2C_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Error Messages
|
||||
//
|
||||
#define I2C_ERROR 0xFFFF
|
||||
#define I2C_ARB_LOST_ERROR 0x0001
|
||||
#define I2C_NACK_ERROR 0x0002
|
||||
#define I2C_BUS_BUSY_ERROR 0x1000
|
||||
#define I2C_STP_NOT_READY_ERROR 0x5555
|
||||
#define I2C_NO_FLAGS 0xAAAA
|
||||
#define I2C_SUCCESS 0x0000
|
||||
|
||||
//
|
||||
// Clear Status Flags
|
||||
//
|
||||
#define I2C_CLR_AL_BIT 0x0001
|
||||
#define I2C_CLR_NACK_BIT 0x0002
|
||||
#define I2C_CLR_ARDY_BIT 0x0004
|
||||
#define I2C_CLR_RRDY_BIT 0x0008
|
||||
#define I2C_CLR_SCD_BIT 0x0020
|
||||
|
||||
//
|
||||
// Interrupt Source Messages
|
||||
//
|
||||
#define I2C_NO_ISRC 0x0000
|
||||
#define I2C_ARB_ISRC 0x0001
|
||||
#define I2C_NACK_ISRC 0x0002
|
||||
#define I2C_ARDY_ISRC 0x0003
|
||||
#define I2C_RX_ISRC 0x0004
|
||||
#define I2C_TX_ISRC 0x0005
|
||||
#define I2C_SCD_ISRC 0x0006
|
||||
#define I2C_AAS_ISRC 0x0007
|
||||
|
||||
//
|
||||
// I2CMSG structure defines
|
||||
//
|
||||
#define I2C_NO_STOP 0
|
||||
#define I2C_YES_STOP 1
|
||||
#define I2C_RECEIVE 0
|
||||
#define I2C_TRANSMIT 1
|
||||
#define I2C_MAX_BUFFER_SIZE 16
|
||||
|
||||
//
|
||||
// I2C Slave State defines
|
||||
//
|
||||
#define I2C_NOTSLAVE 0
|
||||
#define I2C_ADDR_AS_SLAVE 1
|
||||
#define I2C_ST_MSG_READY 2
|
||||
|
||||
//
|
||||
// I2C Slave Receiver messages defines
|
||||
//
|
||||
#define I2C_SND_MSG1 1
|
||||
#define I2C_SND_MSG2 2
|
||||
|
||||
//
|
||||
// I2C State defines
|
||||
//
|
||||
#define I2C_IDLE 0
|
||||
#define I2C_SLAVE_RECEIVER 1
|
||||
#define I2C_SLAVE_TRANSMITTER 2
|
||||
#define I2C_MASTER_RECEIVER 3
|
||||
#define I2C_MASTER_TRANSMITTER 4
|
||||
|
||||
//
|
||||
// I2C Message Commands for I2CMSG struct
|
||||
//
|
||||
#define I2C_MSGSTAT_INACTIVE 0x0000
|
||||
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
|
||||
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
|
||||
#define I2C_MSGSTAT_RESTART 0x0022
|
||||
#define I2C_MSGSTAT_READ_BUSY 0x0023
|
||||
|
||||
//
|
||||
// Generic defines
|
||||
//
|
||||
#define I2C_TRUE 1
|
||||
#define I2C_FALSE 0
|
||||
#define I2C_YES 1
|
||||
#define I2C_NO 0
|
||||
#define I2C_DUMMY_BYTE 0
|
||||
|
||||
//
|
||||
// Structures
|
||||
//
|
||||
|
||||
//
|
||||
// I2C Message Structure
|
||||
//
|
||||
struct I2CMSG
|
||||
{
|
||||
Uint16 MsgStatus; // Word stating what state msg is in:
|
||||
// I2C_MSGCMD_INACTIVE = do not send msg
|
||||
// I2C_MSGCMD_BUSY = msg start has been sent,
|
||||
// awaiting stop
|
||||
// I2C_MSGCMD_SEND_WITHSTOP = command to send
|
||||
// master trans msg complete with a stop bit
|
||||
// I2C_MSGCMD_SEND_NOSTOP = command to send
|
||||
// master trans msg without the stop bit
|
||||
// I2C_MSGCMD_RESTART = command to send a restart
|
||||
// as a master receiver with a stop bit
|
||||
Uint16 SlaveAddress; // I2C address of slave msg is intended for
|
||||
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
|
||||
|
||||
//
|
||||
// EEPROM address of data associated with msg (high byte)
|
||||
//
|
||||
Uint16 MemoryHighAddr;
|
||||
|
||||
//
|
||||
// EEPROM address of data associated with msg (low byte)
|
||||
//
|
||||
Uint16 MemoryLowAddr;
|
||||
|
||||
//
|
||||
// Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to
|
||||
// the FIFO's
|
||||
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];
|
||||
};
|
||||
|
||||
|
||||
#endif // end of DSP2833x_I2C_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:39 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_XIntrupt.h
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interrupt Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_XINTRUPT_H
|
||||
#define DSP2833x_XINTRUPT_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct XINTCR_BITS {
|
||||
Uint16 ENABLE:1; // 0 enable/disable
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
|
||||
Uint16 rsvd2:12; //15:4 reserved
|
||||
};
|
||||
|
||||
union XINTCR_REG {
|
||||
Uint16 all;
|
||||
struct XINTCR_BITS bit;
|
||||
};
|
||||
|
||||
struct XNMICR_BITS {
|
||||
Uint16 ENABLE:1; // 0 enable/disable
|
||||
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
|
||||
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union XNMICR_REG {
|
||||
Uint16 all;
|
||||
struct XNMICR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// External Interrupt Register File
|
||||
//
|
||||
struct XINTRUPT_REGS {
|
||||
union XINTCR_REG XINT1CR;
|
||||
union XINTCR_REG XINT2CR;
|
||||
union XINTCR_REG XINT3CR;
|
||||
union XINTCR_REG XINT4CR;
|
||||
union XINTCR_REG XINT5CR;
|
||||
union XINTCR_REG XINT6CR;
|
||||
union XINTCR_REG XINT7CR;
|
||||
union XNMICR_REG XNMICR;
|
||||
Uint16 XINT1CTR;
|
||||
Uint16 XINT2CTR;
|
||||
Uint16 rsvd[5];
|
||||
Uint16 XNMICTR;
|
||||
};
|
||||
|
||||
//
|
||||
// External Interrupt References & Function Declarations
|
||||
//
|
||||
extern volatile struct XINTRUPT_REGS XIntruptRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_XINTF_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,291 @@
|
||||
// TI File $Revision: /main/11 $
|
||||
// Checkin $Date: May 12, 2008 14:30:08 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_GlobalPrototypes.h
|
||||
//
|
||||
// TITLE: Global prototypes for DSP2833x Examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_GLOBALPROTOTYPES_H
|
||||
#define DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// shared global function prototypes
|
||||
//
|
||||
extern void InitAdc(void);
|
||||
extern void DMAInitialize(void);
|
||||
|
||||
//
|
||||
// DMA Channel 1
|
||||
//
|
||||
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH1(void);
|
||||
|
||||
//
|
||||
// DMA Channel 2
|
||||
//
|
||||
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH2(void);
|
||||
|
||||
//
|
||||
// DMA Channel 3
|
||||
//
|
||||
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH3(void);
|
||||
|
||||
//
|
||||
// DMA Channel 4
|
||||
//
|
||||
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH4(void);
|
||||
|
||||
//
|
||||
// DMA Channel 5
|
||||
//
|
||||
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH5(void);
|
||||
|
||||
//
|
||||
// DMA Channel 6
|
||||
//
|
||||
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH6(void);
|
||||
|
||||
extern void InitPeripherals(void);
|
||||
#if DSP28_ECANA
|
||||
extern void InitECan(void);
|
||||
extern void InitECana(void);
|
||||
extern void InitECanGpio(void);
|
||||
extern void InitECanaGpio(void);
|
||||
#endif // endif DSP28_ECANA
|
||||
#if DSP28_ECANB
|
||||
extern void InitECanb(void);
|
||||
extern void InitECanbGpio(void);
|
||||
#endif // endif DSP28_ECANB
|
||||
extern void InitECap(void);
|
||||
extern void InitECapGpio(void);
|
||||
extern void InitECap1Gpio(void);
|
||||
extern void InitECap2Gpio(void);
|
||||
#if DSP28_ECAP3
|
||||
extern void InitECap3Gpio(void);
|
||||
#endif // endif DSP28_ECAP3
|
||||
#if DSP28_ECAP4
|
||||
extern void InitECap4Gpio(void);
|
||||
#endif // endif DSP28_ECAP4
|
||||
#if DSP28_ECAP5
|
||||
extern void InitECap5Gpio(void);
|
||||
#endif // endif DSP28_ECAP5
|
||||
#if DSP28_ECAP6
|
||||
extern void InitECap6Gpio(void);
|
||||
#endif // endif DSP28_ECAP6
|
||||
extern void InitEPwm(void);
|
||||
extern void InitEPwmGpio(void);
|
||||
extern void InitEPwm1Gpio(void);
|
||||
extern void InitEPwm2Gpio(void);
|
||||
extern void InitEPwm3Gpio(void);
|
||||
#if DSP28_EPWM4
|
||||
extern void InitEPwm4Gpio(void);
|
||||
#endif // endif DSP28_EPWM4
|
||||
#if DSP28_EPWM5
|
||||
extern void InitEPwm5Gpio(void);
|
||||
#endif // endif DSP28_EPWM5
|
||||
#if DSP28_EPWM6
|
||||
extern void InitEPwm6Gpio(void);
|
||||
#endif // endif DSP28_EPWM6
|
||||
#if DSP28_EQEP1
|
||||
extern void InitEQep(void);
|
||||
extern void InitEQepGpio(void);
|
||||
extern void InitEQep1Gpio(void);
|
||||
#endif // if DSP28_EQEP1
|
||||
#if DSP28_EQEP2
|
||||
extern void InitEQep2Gpio(void);
|
||||
#endif // endif DSP28_EQEP2
|
||||
extern void InitGpio(void);
|
||||
extern void InitI2CGpio(void);
|
||||
|
||||
extern void InitMcbsp(void);
|
||||
extern void InitMcbspa(void);
|
||||
extern void delay_loop(void);
|
||||
extern void InitMcbspaGpio(void);
|
||||
extern void InitMcbspa8bit(void);
|
||||
extern void InitMcbspa12bit(void);
|
||||
extern void InitMcbspa16bit(void);
|
||||
extern void InitMcbspa20bit(void);
|
||||
extern void InitMcbspa24bit(void);
|
||||
extern void InitMcbspa32bit(void);
|
||||
#if DSP28_MCBSPB
|
||||
extern void InitMcbspb(void);
|
||||
extern void InitMcbspbGpio(void);
|
||||
extern void InitMcbspb8bit(void);
|
||||
extern void InitMcbspb12bit(void);
|
||||
extern void InitMcbspb16bit(void);
|
||||
extern void InitMcbspb20bit(void);
|
||||
extern void InitMcbspb24bit(void);
|
||||
extern void InitMcbspb32bit(void);
|
||||
#endif // endif DSP28_MCBSPB
|
||||
|
||||
extern void InitPieCtrl(void);
|
||||
extern void InitPieVectTable(void);
|
||||
|
||||
extern void InitSci(void);
|
||||
extern void InitSciGpio(void);
|
||||
extern void InitSciaGpio(void);
|
||||
#if DSP28_SCIB
|
||||
extern void InitScibGpio(void);
|
||||
#endif // endif DSP28_SCIB
|
||||
#if DSP28_SCIC
|
||||
extern void InitScicGpio(void);
|
||||
#endif
|
||||
extern void InitSpi(void);
|
||||
extern void InitSpiGpio(void);
|
||||
extern void InitSpiaGpio(void);
|
||||
extern void InitSysCtrl(void);
|
||||
extern void InitTzGpio(void);
|
||||
extern void InitXIntrupt(void);
|
||||
extern void XintfInit(void);
|
||||
extern void InitXintf16Gpio();
|
||||
extern void InitXintf32Gpio();
|
||||
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
|
||||
extern void InitPeripheralClocks(void);
|
||||
extern void EnableInterrupts(void);
|
||||
extern void DSP28x_usDelay(Uint32 Count);
|
||||
extern void ADC_cal (void);
|
||||
#define KickDog ServiceDog // For compatiblity with previous versions
|
||||
extern void ServiceDog(void);
|
||||
extern void DisableDog(void);
|
||||
extern Uint16 CsmUnlock(void);
|
||||
|
||||
//
|
||||
// DSP28_DBGIER.asm
|
||||
//
|
||||
extern void SetDBGIER(Uint16 dbgier);
|
||||
|
||||
//
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
//
|
||||
extern void InitFlash(void);
|
||||
|
||||
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
|
||||
|
||||
//
|
||||
// External symbols created by the linker cmd file
|
||||
// DSP28 examples will use these to relocate code from one LOAD location
|
||||
// in either Flash or XINTF to a different RUN location in internal
|
||||
// RAM
|
||||
//
|
||||
extern Uint16 RamfuncsLoadStart;
|
||||
extern Uint16 RamfuncsLoadEnd;
|
||||
extern Uint16 RamfuncsRunStart;
|
||||
extern Uint16 RamfuncsLoadSize;
|
||||
|
||||
extern Uint16 XintffuncsLoadStart;
|
||||
extern Uint16 XintffuncsLoadEnd;
|
||||
extern Uint16 XintffuncsRunStart;
|
||||
extern Uint16 XintffuncsLoadSize;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,239 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: January 22, 2008 16:55:35 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Device.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEVICE_H
|
||||
#define DSP2833x_DEVICE_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define TARGET 1
|
||||
|
||||
//
|
||||
// User To Select Target Device
|
||||
//
|
||||
#define DSP28_28335 TARGET // Selects '28335/'28235
|
||||
#define DSP28_28334 0 // Selects '28334/'28234
|
||||
#define DSP28_28333 0 // Selects '28333/'
|
||||
#define DSP28_28332 0 // Selects '28332/'28232
|
||||
|
||||
//
|
||||
// Common CPU Definitions
|
||||
//
|
||||
extern cregister volatile unsigned int IFR;
|
||||
extern cregister volatile unsigned int IER;
|
||||
|
||||
#define EINT asm(" clrc INTM")
|
||||
#define DINT asm(" setc INTM")
|
||||
#define ERTM asm(" clrc DBGM")
|
||||
#define DRTM asm(" setc DBGM")
|
||||
#define EALLOW asm(" EALLOW")
|
||||
#define EDIS asm(" EDIS")
|
||||
#define ESTOP0 asm(" ESTOP0")
|
||||
|
||||
#define M_INT1 0x0001
|
||||
#define M_INT2 0x0002
|
||||
#define M_INT3 0x0004
|
||||
#define M_INT4 0x0008
|
||||
#define M_INT5 0x0010
|
||||
#define M_INT6 0x0020
|
||||
#define M_INT7 0x0040
|
||||
#define M_INT8 0x0080
|
||||
#define M_INT9 0x0100
|
||||
#define M_INT10 0x0200
|
||||
#define M_INT11 0x0400
|
||||
#define M_INT12 0x0800
|
||||
#define M_INT13 0x1000
|
||||
#define M_INT14 0x2000
|
||||
#define M_DLOG 0x4000
|
||||
#define M_RTOS 0x8000
|
||||
|
||||
#define BIT0 0x0001
|
||||
#define BIT1 0x0002
|
||||
#define BIT2 0x0004
|
||||
#define BIT3 0x0008
|
||||
#define BIT4 0x0010
|
||||
#define BIT5 0x0020
|
||||
#define BIT6 0x0040
|
||||
#define BIT7 0x0080
|
||||
#define BIT8 0x0100
|
||||
#define BIT9 0x0200
|
||||
#define BIT10 0x0400
|
||||
#define BIT11 0x0800
|
||||
#define BIT12 0x1000
|
||||
#define BIT13 0x2000
|
||||
#define BIT14 0x4000
|
||||
#define BIT15 0x8000
|
||||
|
||||
//
|
||||
// For Portability, User Is Recommended To Use Following Data Type Size
|
||||
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
|
||||
//
|
||||
#ifndef DSP28_DATA_TYPES
|
||||
#define DSP28_DATA_TYPES
|
||||
typedef int int16;
|
||||
typedef long int32;
|
||||
typedef long long int64;
|
||||
typedef unsigned int Uint16;
|
||||
typedef unsigned long Uint32;
|
||||
typedef unsigned long long Uint64;
|
||||
typedef float float32;
|
||||
typedef long double float64;
|
||||
#endif
|
||||
|
||||
//
|
||||
// Included Peripheral Header Files
|
||||
//
|
||||
#include "DSP2833x_Adc.h" // ADC Registers
|
||||
#include "DSP2833x_DevEmu.h" // Device Emulation Registers
|
||||
#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers
|
||||
#include "DSP2833x_ECan.h" // Enhanced eCAN Registers
|
||||
#include "DSP2833x_ECap.h" // Enhanced Capture
|
||||
#include "DSP2833x_DMA.h" // DMA Registers
|
||||
#include "DSP2833x_EPwm.h" // Enhanced PWM
|
||||
#include "DSP2833x_EQep.h" // Enhanced QEP
|
||||
#include "DSP2833x_Gpio.h" // General Purpose I/O Registers
|
||||
#include "DSP2833x_I2c.h" // I2C Registers
|
||||
#include "DSP2833x_Mcbsp.h" // McBSP
|
||||
#include "DSP2833x_PieCtrl.h" // PIE Control Registers
|
||||
#include "DSP2833x_PieVect.h" // PIE Vector Table
|
||||
#include "DSP2833x_Spi.h" // SPI Registers
|
||||
#include "DSP2833x_Sci.h" // SCI Registers
|
||||
#include "DSP2833x_SysCtrl.h" // System Control/Power Modes
|
||||
#include "DSP2833x_XIntrupt.h" // External Interrupts
|
||||
#include "DSP2833x_Xintf.h" // XINTF External Interface
|
||||
|
||||
#if DSP28_28335 || DSP28_28333
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 1
|
||||
#define DSP28_ECAP6 1
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 1
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 1
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28335 || DSP28_28333
|
||||
|
||||
#if DSP28_28334
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 0
|
||||
#define DSP28_ECAP6 0
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 1
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 1
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28334
|
||||
|
||||
#if DSP28_28332
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 0
|
||||
#define DSP28_ECAP6 0
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 0
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 0
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28332
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEVICE_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,179 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:07 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_ECap.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_ECAP_H
|
||||
#define DSP2833x_ECAP_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Capture control register 1 bit definitions
|
||||
//
|
||||
struct ECCTL1_BITS { // bits description
|
||||
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
|
||||
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
|
||||
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
|
||||
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
|
||||
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
|
||||
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
|
||||
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
|
||||
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
|
||||
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap
|
||||
// Event
|
||||
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union ECCTL1_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// In V1.1 the STOPVALUE bit field was changed to
|
||||
// STOP_WRAP. This correlated to a silicon change from
|
||||
// F2833x Rev 0 to Rev A.
|
||||
//
|
||||
|
||||
//
|
||||
// Capture control register 2 bit definitions
|
||||
//
|
||||
struct ECCTL2_BITS { // bits description
|
||||
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
|
||||
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
|
||||
Uint16 REARM:1; // 3 One-shot re-arm
|
||||
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
|
||||
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
|
||||
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
|
||||
Uint16 SWSYNC:1; // 8 SW forced counter sync
|
||||
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
|
||||
Uint16 APWMPOL:1; // 10 APWM output polarity select
|
||||
Uint16 rsvd1:5; // 15:11
|
||||
};
|
||||
|
||||
union ECCTL2_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// ECAP interrupt enable register bit definitions
|
||||
//
|
||||
struct ECEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
|
||||
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
|
||||
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ECEINT_REG {
|
||||
Uint16 all;
|
||||
struct ECEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// ECAP interrupt flag register bit definitions
|
||||
//
|
||||
struct ECFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global Flag
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
|
||||
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
|
||||
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ECFLG_REG {
|
||||
Uint16 all;
|
||||
struct ECFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct ECAP_REGS {
|
||||
Uint32 TSCTR; // Time stamp counter
|
||||
Uint32 CTRPHS; // Counter phase
|
||||
Uint32 CAP1; // Capture 1
|
||||
Uint32 CAP2; // Capture 2
|
||||
Uint32 CAP3; // Capture 3
|
||||
Uint32 CAP4; // Capture 4
|
||||
Uint16 rsvd1[8]; // reserved
|
||||
union ECCTL1_REG ECCTL1; // Capture Control Reg 1
|
||||
union ECCTL2_REG ECCTL2; // Capture Control Reg 2
|
||||
union ECEINT_REG ECEINT; // ECAP interrupt enable
|
||||
union ECFLG_REG ECFLG; // ECAP interrupt flags
|
||||
union ECFLG_REG ECCLR; // ECAP interrupt clear
|
||||
union ECEINT_REG ECFRC; // ECAP interrupt force
|
||||
Uint16 rsvd2[6]; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct ECAP_REGS ECap1Regs;
|
||||
extern volatile struct ECAP_REGS ECap2Regs;
|
||||
extern volatile struct ECAP_REGS ECap3Regs;
|
||||
extern volatile struct ECAP_REGS ECap4Regs;
|
||||
extern volatile struct ECAP_REGS ECap5Regs;
|
||||
extern volatile struct ECAP_REGS ECap6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_ECAP_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,265 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 16, 2007 09:00:21 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieVect.h
|
||||
//
|
||||
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_PIE_VECT_H
|
||||
#define DSP2833x_PIE_VECT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// PIE Interrupt Vector Table Definition
|
||||
//
|
||||
|
||||
//
|
||||
// Typedef used to create a user type called PINT (pointer to interrupt)
|
||||
//
|
||||
typedef interrupt void(*PINT)(void);
|
||||
|
||||
//
|
||||
// Vector Table Define
|
||||
//
|
||||
struct PIE_VECT_TABLE {
|
||||
//
|
||||
// Reset is never fetched from this table. It will always be fetched from
|
||||
// 0x3FFFC0 in boot ROM
|
||||
//
|
||||
PINT PIE1_RESERVED;
|
||||
PINT PIE2_RESERVED;
|
||||
PINT PIE3_RESERVED;
|
||||
PINT PIE4_RESERVED;
|
||||
PINT PIE5_RESERVED;
|
||||
PINT PIE6_RESERVED;
|
||||
PINT PIE7_RESERVED;
|
||||
PINT PIE8_RESERVED;
|
||||
PINT PIE9_RESERVED;
|
||||
PINT PIE10_RESERVED;
|
||||
PINT PIE11_RESERVED;
|
||||
PINT PIE12_RESERVED;
|
||||
PINT PIE13_RESERVED;
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts
|
||||
//
|
||||
PINT XINT13; // XINT13 / CPU-Timer1
|
||||
PINT TINT2; // CPU-Timer2
|
||||
PINT DATALOG; // Datalogging interrupt
|
||||
PINT RTOSINT; // RTOS interrupt
|
||||
PINT EMUINT; // Emulation interrupt
|
||||
PINT XNMI; // Non-maskable interrupt
|
||||
PINT ILLEGAL; // Illegal operation TRAP
|
||||
PINT USER1; // User Defined trap 1
|
||||
PINT USER2; // User Defined trap 2
|
||||
PINT USER3; // User Defined trap 3
|
||||
PINT USER4; // User Defined trap 4
|
||||
PINT USER5; // User Defined trap 5
|
||||
PINT USER6; // User Defined trap 6
|
||||
PINT USER7; // User Defined trap 7
|
||||
PINT USER8; // User Defined trap 8
|
||||
PINT USER9; // User Defined trap 9
|
||||
PINT USER10; // User Defined trap 10
|
||||
PINT USER11; // User Defined trap 11
|
||||
PINT USER12; // User Defined trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SEQ1INT;
|
||||
PINT SEQ2INT;
|
||||
PINT rsvd1_3;
|
||||
PINT XINT1;
|
||||
PINT XINT2;
|
||||
PINT ADCINT; // ADC
|
||||
PINT TINT0; // Timer 0
|
||||
PINT WAKEINT; // WD
|
||||
|
||||
//
|
||||
// Group 2 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EPWM1_TZINT; // EPWM-1
|
||||
PINT EPWM2_TZINT; // EPWM-2
|
||||
PINT EPWM3_TZINT; // EPWM-3
|
||||
PINT EPWM4_TZINT; // EPWM-4
|
||||
PINT EPWM5_TZINT; // EPWM-5
|
||||
PINT EPWM6_TZINT; // EPWM-6
|
||||
PINT rsvd2_7;
|
||||
PINT rsvd2_8;
|
||||
|
||||
//
|
||||
// Group 3 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EPWM1_INT; // EPWM-1
|
||||
PINT EPWM2_INT; // EPWM-2
|
||||
PINT EPWM3_INT; // EPWM-3
|
||||
PINT EPWM4_INT; // EPWM-4
|
||||
PINT EPWM5_INT; // EPWM-5
|
||||
PINT EPWM6_INT; // EPWM-6
|
||||
PINT rsvd3_7;
|
||||
PINT rsvd3_8;
|
||||
|
||||
//
|
||||
// Group 4 PIE Peripheral Vectors
|
||||
//
|
||||
PINT ECAP1_INT; // ECAP-1
|
||||
PINT ECAP2_INT; // ECAP-2
|
||||
PINT ECAP3_INT; // ECAP-3
|
||||
PINT ECAP4_INT; // ECAP-4
|
||||
PINT ECAP5_INT; // ECAP-5
|
||||
PINT ECAP6_INT; // ECAP-6
|
||||
PINT rsvd4_7;
|
||||
PINT rsvd4_8;
|
||||
|
||||
//
|
||||
// Group 5 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EQEP1_INT; // EQEP-1
|
||||
PINT EQEP2_INT; // EQEP-2
|
||||
PINT rsvd5_3;
|
||||
PINT rsvd5_4;
|
||||
PINT rsvd5_5;
|
||||
PINT rsvd5_6;
|
||||
PINT rsvd5_7;
|
||||
PINT rsvd5_8;
|
||||
|
||||
//
|
||||
// Group 6 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SPIRXINTA; // SPI-A
|
||||
PINT SPITXINTA; // SPI-A
|
||||
PINT MRINTB; // McBSP-B
|
||||
PINT MXINTB; // McBSP-B
|
||||
PINT MRINTA; // McBSP-A
|
||||
PINT MXINTA; // McBSP-A
|
||||
PINT rsvd6_7;
|
||||
PINT rsvd6_8;
|
||||
|
||||
//
|
||||
// Group 7 PIE Peripheral Vectors
|
||||
//
|
||||
PINT DINTCH1; // DMA
|
||||
PINT DINTCH2; // DMA
|
||||
PINT DINTCH3; // DMA
|
||||
PINT DINTCH4; // DMA
|
||||
PINT DINTCH5; // DMA
|
||||
PINT DINTCH6; // DMA
|
||||
PINT rsvd7_7;
|
||||
PINT rsvd7_8;
|
||||
|
||||
//
|
||||
// Group 8 PIE Peripheral Vectors
|
||||
//
|
||||
PINT I2CINT1A; // I2C-A
|
||||
PINT I2CINT2A; // I2C-A
|
||||
PINT rsvd8_3;
|
||||
PINT rsvd8_4;
|
||||
PINT SCIRXINTC; // SCI-C
|
||||
PINT SCITXINTC; // SCI-C
|
||||
PINT rsvd8_7;
|
||||
PINT rsvd8_8;
|
||||
|
||||
//
|
||||
// Group 9 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SCIRXINTA; // SCI-A
|
||||
PINT SCITXINTA; // SCI-A
|
||||
PINT SCIRXINTB; // SCI-B
|
||||
PINT SCITXINTB; // SCI-B
|
||||
PINT ECAN0INTA; // eCAN-A
|
||||
PINT ECAN1INTA; // eCAN-A
|
||||
PINT ECAN0INTB; // eCAN-B
|
||||
PINT ECAN1INTB; // eCAN-B
|
||||
|
||||
//
|
||||
// Group 10 PIE Peripheral Vectors
|
||||
//
|
||||
PINT rsvd10_1;
|
||||
PINT rsvd10_2;
|
||||
PINT rsvd10_3;
|
||||
PINT rsvd10_4;
|
||||
PINT rsvd10_5;
|
||||
PINT rsvd10_6;
|
||||
PINT rsvd10_7;
|
||||
PINT rsvd10_8;
|
||||
|
||||
//
|
||||
// Group 11 PIE Peripheral Vectors
|
||||
//
|
||||
PINT rsvd11_1;
|
||||
PINT rsvd11_2;
|
||||
PINT rsvd11_3;
|
||||
PINT rsvd11_4;
|
||||
PINT rsvd11_5;
|
||||
PINT rsvd11_6;
|
||||
PINT rsvd11_7;
|
||||
PINT rsvd11_8;
|
||||
|
||||
//
|
||||
// Group 12 PIE Peripheral Vectors
|
||||
//
|
||||
PINT XINT3; // External interrupt
|
||||
PINT XINT4;
|
||||
PINT XINT5;
|
||||
PINT XINT6;
|
||||
PINT XINT7;
|
||||
PINT rsvd12_6;
|
||||
PINT LVF; // Latched overflow
|
||||
PINT LUF; // Latched underflow
|
||||
};
|
||||
|
||||
//
|
||||
// PIE Interrupt Vector Table External References & Function Declarations
|
||||
//
|
||||
extern volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_PIE_VECT_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,493 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: November 15, 2007 09:58:53 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Gpio.h
|
||||
//
|
||||
// TITLE: DSP2833x General Purpose I/O Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_GPIO_H
|
||||
#define DSP2833x_GPIO_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// GPIO A control register bit definitions
|
||||
//
|
||||
struct GPACTRL_BITS { // bits description
|
||||
Uint16 QUALPRD0:8; // 7:0 Qual period
|
||||
Uint16 QUALPRD1:8; // 15:8 Qual period
|
||||
Uint16 QUALPRD2:8; // 23:16 Qual period
|
||||
Uint16 QUALPRD3:8; // 31:24 Qual period
|
||||
};
|
||||
|
||||
union GPACTRL_REG {
|
||||
Uint32 all;
|
||||
struct GPACTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO B control register bit definitions
|
||||
//
|
||||
struct GPBCTRL_BITS { // bits description
|
||||
Uint16 QUALPRD0:8; // 7:0 Qual period
|
||||
Uint16 QUALPRD1:8; // 15:8 Qual period
|
||||
Uint16 QUALPRD2:8; // 23:16 Qual period
|
||||
Uint16 QUALPRD3:8; // 31:24
|
||||
};
|
||||
|
||||
union GPBCTRL_REG {
|
||||
Uint32 all;
|
||||
struct GPBCTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO A Qual/MUX select register bit definitions
|
||||
//
|
||||
struct GPA1_BITS { // bits description
|
||||
Uint16 GPIO0:2; // 1:0 GPIO0
|
||||
Uint16 GPIO1:2; // 3:2 GPIO1
|
||||
Uint16 GPIO2:2; // 5:4 GPIO2
|
||||
Uint16 GPIO3:2; // 7:6 GPIO3
|
||||
Uint16 GPIO4:2; // 9:8 GPIO4
|
||||
Uint16 GPIO5:2; // 11:10 GPIO5
|
||||
Uint16 GPIO6:2; // 13:12 GPIO6
|
||||
Uint16 GPIO7:2; // 15:14 GPIO7
|
||||
Uint16 GPIO8:2; // 17:16 GPIO8
|
||||
Uint16 GPIO9:2; // 19:18 GPIO9
|
||||
Uint16 GPIO10:2; // 21:20 GPIO10
|
||||
Uint16 GPIO11:2; // 23:22 GPIO11
|
||||
Uint16 GPIO12:2; // 25:24 GPIO12
|
||||
Uint16 GPIO13:2; // 27:26 GPIO13
|
||||
Uint16 GPIO14:2; // 29:28 GPIO14
|
||||
Uint16 GPIO15:2; // 31:30 GPIO15
|
||||
};
|
||||
|
||||
struct GPA2_BITS { // bits description
|
||||
Uint16 GPIO16:2; // 1:0 GPIO16
|
||||
Uint16 GPIO17:2; // 3:2 GPIO17
|
||||
Uint16 GPIO18:2; // 5:4 GPIO18
|
||||
Uint16 GPIO19:2; // 7:6 GPIO19
|
||||
Uint16 GPIO20:2; // 9:8 GPIO20
|
||||
Uint16 GPIO21:2; // 11:10 GPIO21
|
||||
Uint16 GPIO22:2; // 13:12 GPIO22
|
||||
Uint16 GPIO23:2; // 15:14 GPIO23
|
||||
Uint16 GPIO24:2; // 17:16 GPIO24
|
||||
Uint16 GPIO25:2; // 19:18 GPIO25
|
||||
Uint16 GPIO26:2; // 21:20 GPIO26
|
||||
Uint16 GPIO27:2; // 23:22 GPIO27
|
||||
Uint16 GPIO28:2; // 25:24 GPIO28
|
||||
Uint16 GPIO29:2; // 27:26 GPIO29
|
||||
Uint16 GPIO30:2; // 29:28 GPIO30
|
||||
Uint16 GPIO31:2; // 31:30 GPIO31
|
||||
};
|
||||
|
||||
struct GPB1_BITS { // bits description
|
||||
Uint16 GPIO32:2; // 1:0 GPIO32
|
||||
Uint16 GPIO33:2; // 3:2 GPIO33
|
||||
Uint16 GPIO34:2; // 5:4 GPIO34
|
||||
Uint16 GPIO35:2; // 7:6 GPIO35
|
||||
Uint16 GPIO36:2; // 9:8 GPIO36
|
||||
Uint16 GPIO37:2; // 11:10 GPIO37
|
||||
Uint16 GPIO38:2; // 13:12 GPIO38
|
||||
Uint16 GPIO39:2; // 15:14 GPIO39
|
||||
Uint16 GPIO40:2; // 17:16 GPIO40
|
||||
Uint16 GPIO41:2; // 19:16 GPIO41
|
||||
Uint16 GPIO42:2; // 21:20 GPIO42
|
||||
Uint16 GPIO43:2; // 23:22 GPIO43
|
||||
Uint16 GPIO44:2; // 25:24 GPIO44
|
||||
Uint16 GPIO45:2; // 27:26 GPIO45
|
||||
Uint16 GPIO46:2; // 29:28 GPIO46
|
||||
Uint16 GPIO47:2; // 31:30 GPIO47
|
||||
};
|
||||
|
||||
struct GPB2_BITS { // bits description
|
||||
Uint16 GPIO48:2; // 1:0 GPIO48
|
||||
Uint16 GPIO49:2; // 3:2 GPIO49
|
||||
Uint16 GPIO50:2; // 5:4 GPIO50
|
||||
Uint16 GPIO51:2; // 7:6 GPIO51
|
||||
Uint16 GPIO52:2; // 9:8 GPIO52
|
||||
Uint16 GPIO53:2; // 11:10 GPIO53
|
||||
Uint16 GPIO54:2; // 13:12 GPIO54
|
||||
Uint16 GPIO55:2; // 15:14 GPIO55
|
||||
Uint16 GPIO56:2; // 17:16 GPIO56
|
||||
Uint16 GPIO57:2; // 19:18 GPIO57
|
||||
Uint16 GPIO58:2; // 21:20 GPIO58
|
||||
Uint16 GPIO59:2; // 23:22 GPIO59
|
||||
Uint16 GPIO60:2; // 25:24 GPIO60
|
||||
Uint16 GPIO61:2; // 27:26 GPIO61
|
||||
Uint16 GPIO62:2; // 29:28 GPIO62
|
||||
Uint16 GPIO63:2; // 31:30 GPIO63
|
||||
};
|
||||
|
||||
struct GPC1_BITS { // bits description
|
||||
Uint16 GPIO64:2; // 1:0 GPIO64
|
||||
Uint16 GPIO65:2; // 3:2 GPIO65
|
||||
Uint16 GPIO66:2; // 5:4 GPIO66
|
||||
Uint16 GPIO67:2; // 7:6 GPIO67
|
||||
Uint16 GPIO68:2; // 9:8 GPIO68
|
||||
Uint16 GPIO69:2; // 11:10 GPIO69
|
||||
Uint16 GPIO70:2; // 13:12 GPIO70
|
||||
Uint16 GPIO71:2; // 15:14 GPIO71
|
||||
Uint16 GPIO72:2; // 17:16 GPIO72
|
||||
Uint16 GPIO73:2; // 19:18 GPIO73
|
||||
Uint16 GPIO74:2; // 21:20 GPIO74
|
||||
Uint16 GPIO75:2; // 23:22 GPIO75
|
||||
Uint16 GPIO76:2; // 25:24 GPIO76
|
||||
Uint16 GPIO77:2; // 27:26 GPIO77
|
||||
Uint16 GPIO78:2; // 29:28 GPIO78
|
||||
Uint16 GPIO79:2; // 31:30 GPIO79
|
||||
};
|
||||
|
||||
struct GPC2_BITS { // bits description
|
||||
Uint16 GPIO80:2; // 1:0 GPIO80
|
||||
Uint16 GPIO81:2; // 3:2 GPIO81
|
||||
Uint16 GPIO82:2; // 5:4 GPIO82
|
||||
Uint16 GPIO83:2; // 7:6 GPIO83
|
||||
Uint16 GPIO84:2; // 9:8 GPIO84
|
||||
Uint16 GPIO85:2; // 11:10 GPIO85
|
||||
Uint16 GPIO86:2; // 13:12 GPIO86
|
||||
Uint16 GPIO87:2; // 15:14 GPIO87
|
||||
Uint16 rsvd:16; // 31:16 reserved
|
||||
};
|
||||
|
||||
union GPA1_REG {
|
||||
Uint32 all;
|
||||
struct GPA1_BITS bit;
|
||||
};
|
||||
|
||||
union GPA2_REG {
|
||||
Uint32 all;
|
||||
struct GPA2_BITS bit;
|
||||
};
|
||||
|
||||
union GPB1_REG {
|
||||
Uint32 all;
|
||||
struct GPB1_BITS bit;
|
||||
};
|
||||
|
||||
union GPB2_REG {
|
||||
Uint32 all;
|
||||
struct GPB2_BITS bit;
|
||||
};
|
||||
|
||||
union GPC1_REG {
|
||||
Uint32 all;
|
||||
struct GPC1_BITS bit;
|
||||
};
|
||||
|
||||
union GPC2_REG {
|
||||
Uint32 all;
|
||||
struct GPC2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions
|
||||
//
|
||||
struct GPADAT_BITS { // bits description
|
||||
Uint16 GPIO0:1; // 0 GPIO0
|
||||
Uint16 GPIO1:1; // 1 GPIO1
|
||||
Uint16 GPIO2:1; // 2 GPIO2
|
||||
Uint16 GPIO3:1; // 3 GPIO3
|
||||
Uint16 GPIO4:1; // 4 GPIO4
|
||||
Uint16 GPIO5:1; // 5 GPIO5
|
||||
Uint16 GPIO6:1; // 6 GPIO6
|
||||
Uint16 GPIO7:1; // 7 GPIO7
|
||||
Uint16 GPIO8:1; // 8 GPIO8
|
||||
Uint16 GPIO9:1; // 9 GPIO9
|
||||
Uint16 GPIO10:1; // 10 GPIO10
|
||||
Uint16 GPIO11:1; // 11 GPIO11
|
||||
Uint16 GPIO12:1; // 12 GPIO12
|
||||
Uint16 GPIO13:1; // 13 GPIO13
|
||||
Uint16 GPIO14:1; // 14 GPIO14
|
||||
Uint16 GPIO15:1; // 15 GPIO15
|
||||
Uint16 GPIO16:1; // 16 GPIO16
|
||||
Uint16 GPIO17:1; // 17 GPIO17
|
||||
Uint16 GPIO18:1; // 18 GPIO18
|
||||
Uint16 GPIO19:1; // 19 GPIO19
|
||||
Uint16 GPIO20:1; // 20 GPIO20
|
||||
Uint16 GPIO21:1; // 21 GPIO21
|
||||
Uint16 GPIO22:1; // 22 GPIO22
|
||||
Uint16 GPIO23:1; // 23 GPIO23
|
||||
Uint16 GPIO24:1; // 24 GPIO24
|
||||
Uint16 GPIO25:1; // 25 GPIO25
|
||||
Uint16 GPIO26:1; // 26 GPIO26
|
||||
Uint16 GPIO27:1; // 27 GPIO27
|
||||
Uint16 GPIO28:1; // 28 GPIO28
|
||||
Uint16 GPIO29:1; // 29 GPIO29
|
||||
Uint16 GPIO30:1; // 30 GPIO30
|
||||
Uint16 GPIO31:1; // 31 GPIO31
|
||||
};
|
||||
|
||||
struct GPBDAT_BITS { // bits description
|
||||
Uint16 GPIO32:1; // 0 GPIO32
|
||||
Uint16 GPIO33:1; // 1 GPIO33
|
||||
Uint16 GPIO34:1; // 2 GPIO34
|
||||
Uint16 GPIO35:1; // 3 GPIO35
|
||||
Uint16 GPIO36:1; // 4 GPIO36
|
||||
Uint16 GPIO37:1; // 5 GPIO37
|
||||
Uint16 GPIO38:1; // 6 GPIO38
|
||||
Uint16 GPIO39:1; // 7 GPIO39
|
||||
Uint16 GPIO40:1; // 8 GPIO40
|
||||
Uint16 GPIO41:1; // 9 GPIO41
|
||||
Uint16 GPIO42:1; // 10 GPIO42
|
||||
Uint16 GPIO43:1; // 11 GPIO43
|
||||
Uint16 GPIO44:1; // 12 GPIO44
|
||||
Uint16 GPIO45:1; // 13 GPIO45
|
||||
Uint16 GPIO46:1; // 14 GPIO46
|
||||
Uint16 GPIO47:1; // 15 GPIO47
|
||||
Uint16 GPIO48:1; // 16 GPIO48
|
||||
Uint16 GPIO49:1; // 17 GPIO49
|
||||
Uint16 GPIO50:1; // 18 GPIO50
|
||||
Uint16 GPIO51:1; // 19 GPIO51
|
||||
Uint16 GPIO52:1; // 20 GPIO52
|
||||
Uint16 GPIO53:1; // 21 GPIO53
|
||||
Uint16 GPIO54:1; // 22 GPIO54
|
||||
Uint16 GPIO55:1; // 23 GPIO55
|
||||
Uint16 GPIO56:1; // 24 GPIO56
|
||||
Uint16 GPIO57:1; // 25 GPIO57
|
||||
Uint16 GPIO58:1; // 26 GPIO58
|
||||
Uint16 GPIO59:1; // 27 GPIO59
|
||||
Uint16 GPIO60:1; // 28 GPIO60
|
||||
Uint16 GPIO61:1; // 29 GPIO61
|
||||
Uint16 GPIO62:1; // 30 GPIO62
|
||||
Uint16 GPIO63:1; // 31 GPIO63
|
||||
};
|
||||
|
||||
struct GPCDAT_BITS { // bits description
|
||||
Uint16 GPIO64:1; // 0 GPIO64
|
||||
Uint16 GPIO65:1; // 1 GPIO65
|
||||
Uint16 GPIO66:1; // 2 GPIO66
|
||||
Uint16 GPIO67:1; // 3 GPIO67
|
||||
Uint16 GPIO68:1; // 4 GPIO68
|
||||
Uint16 GPIO69:1; // 5 GPIO69
|
||||
Uint16 GPIO70:1; // 6 GPIO70
|
||||
Uint16 GPIO71:1; // 7 GPIO71
|
||||
Uint16 GPIO72:1; // 8 GPIO72
|
||||
Uint16 GPIO73:1; // 9 GPIO73
|
||||
Uint16 GPIO74:1; // 10 GPIO74
|
||||
Uint16 GPIO75:1; // 11 GPIO75
|
||||
Uint16 GPIO76:1; // 12 GPIO76
|
||||
Uint16 GPIO77:1; // 13 GPIO77
|
||||
Uint16 GPIO78:1; // 14 GPIO78
|
||||
Uint16 GPIO79:1; // 15 GPIO79
|
||||
Uint16 GPIO80:1; // 16 GPIO80
|
||||
Uint16 GPIO81:1; // 17 GPIO81
|
||||
Uint16 GPIO82:1; // 18 GPIO82
|
||||
Uint16 GPIO83:1; // 19 GPIO83
|
||||
Uint16 GPIO84:1; // 20 GPIO84
|
||||
Uint16 GPIO85:1; // 21 GPIO85
|
||||
Uint16 GPIO86:1; // 22 GPIO86
|
||||
Uint16 GPIO87:1; // 23 GPIO87
|
||||
Uint16 rsvd1:8; // 31:24 reserved
|
||||
};
|
||||
|
||||
union GPADAT_REG {
|
||||
Uint32 all;
|
||||
struct GPADAT_BITS bit;
|
||||
};
|
||||
|
||||
union GPBDAT_REG {
|
||||
Uint32 all;
|
||||
struct GPBDAT_BITS bit;
|
||||
};
|
||||
|
||||
union GPCDAT_REG {
|
||||
Uint32 all;
|
||||
struct GPCDAT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO Xint1/XINT2/XNMI select register bit definitions
|
||||
//
|
||||
struct GPIOXINT_BITS { // bits description
|
||||
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union GPIOXINT_REG {
|
||||
Uint16 all;
|
||||
struct GPIOXINT_BITS bit;
|
||||
};
|
||||
|
||||
struct GPIO_CTRL_REGS {
|
||||
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO A Qualifier Select 1 Register (GPIO0 to 15)
|
||||
//
|
||||
union GPA1_REG GPAQSEL1;
|
||||
|
||||
//
|
||||
// GPIO A Qualifier Select 2 Register (GPIO16 to 31)
|
||||
//
|
||||
union GPA2_REG GPAQSEL2;
|
||||
|
||||
//
|
||||
// GPIO A Mux 1 Register (GPIO0 to 15)
|
||||
//
|
||||
union GPA1_REG GPAMUX1;
|
||||
|
||||
//
|
||||
// GPIO A Mux 2 Register (GPIO16 to 31)
|
||||
//
|
||||
union GPA2_REG GPAMUX2;
|
||||
|
||||
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO A Pull Up Disable Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPAPUD;
|
||||
|
||||
Uint32 rsvd1;
|
||||
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO B Qualifier Select 1 Register (GPIO32 to 47)
|
||||
//
|
||||
union GPB1_REG GPBQSEL1;
|
||||
|
||||
//
|
||||
// GPIO B Qualifier Select 2 Register (GPIO48 to 63)
|
||||
//
|
||||
union GPB2_REG GPBQSEL2;
|
||||
|
||||
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
|
||||
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
|
||||
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO B Pull Up Disable Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBPUD;
|
||||
|
||||
Uint16 rsvd2[8];
|
||||
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
|
||||
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
|
||||
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
|
||||
|
||||
//
|
||||
// GPIO C Pull Up Disable Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCPUD;
|
||||
};
|
||||
|
||||
struct GPIO_DATA_REGS {
|
||||
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO Data Set Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPASET;
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPACLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPATOGGLE;
|
||||
|
||||
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO Data Set Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBSET;
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBCLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBTOGGLE;
|
||||
|
||||
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
|
||||
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCCLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCTOGGLE;
|
||||
Uint16 rsvd1[8];
|
||||
};
|
||||
|
||||
struct GPIO_INT_REGS {
|
||||
union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection
|
||||
union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
|
||||
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
|
||||
extern volatile struct GPIO_INT_REGS GpioIntRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_GPIO_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,252 @@
|
||||
#ifndef SOURCE_MAIN_H_
|
||||
#define SOURCE_MAIN_H_
|
||||
|
||||
#include <String.h>
|
||||
#include "DSP28x_Project.h"
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "State.h"
|
||||
#include "Oper.h"
|
||||
#include "Display.h"
|
||||
#include "Comm.h"
|
||||
|
||||
#define AUX_TEST
|
||||
|
||||
#define true (1U)
|
||||
#define false (0U)
|
||||
|
||||
// Key Input Port (Lo Active)
|
||||
#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active
|
||||
#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active
|
||||
#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active
|
||||
#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active
|
||||
#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active
|
||||
#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active
|
||||
#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active
|
||||
|
||||
// Read ChipSelect State
|
||||
#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active
|
||||
#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active
|
||||
#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active
|
||||
#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active
|
||||
#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active
|
||||
#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active
|
||||
#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active
|
||||
|
||||
// Active Read From ECU
|
||||
#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active
|
||||
#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active
|
||||
#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active
|
||||
#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active
|
||||
|
||||
// Fail-Safe Enable(ECU HW Emergency)
|
||||
#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active
|
||||
|
||||
// Auxiliary Read all
|
||||
#define STATUS_BIT_HEATER (0)
|
||||
#define STATUS_BIT_GLOW (1)
|
||||
#define STATUS_BIT_SOLENOID (2)
|
||||
#define STATUS_BIT_FUEL (3)
|
||||
#define STATUS_BIT_COOLANT (4)
|
||||
#define STATUS_BIT_FAN1 (5)
|
||||
#define STATUS_BIT_FAN2 (6)
|
||||
|
||||
#define GET_ALL_AUX_STATUS() \
|
||||
( \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \
|
||||
(GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \
|
||||
(GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \
|
||||
)
|
||||
|
||||
/* Comment Description
|
||||
* [!] : 변경시 주의
|
||||
* [?] : 결정이 필요
|
||||
* [*] : 주의보다 더 엄중
|
||||
*/
|
||||
|
||||
/* Firmware 버전 (Semantic Versioning) */
|
||||
#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때
|
||||
#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때
|
||||
#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때
|
||||
|
||||
/* Version History
|
||||
* [0.0.1] : DCU 프로젝트 생성
|
||||
* [0.0.2] : DCU 펌웨어 탑재 성공
|
||||
* [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현
|
||||
* [0.0.4] : OLED 표시 화면 구현
|
||||
* [0.0.5] : CAN-B 확인 및 맵핑
|
||||
* [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정
|
||||
* [0.1.6] : Suter 보조엔진 시동 완료 시점
|
||||
* [0.1.7] : 발전상태 전환 조건 추가 26-02-23
|
||||
* [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제>
|
||||
* [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26
|
||||
*/
|
||||
|
||||
#define MAINTENECE_PASSKEY {0,0,0,0}
|
||||
|
||||
#define ENABLED (1)
|
||||
#define DISABLED (!ENABLED)
|
||||
|
||||
/*
|
||||
* Bit mask
|
||||
*/
|
||||
#define MASK_LOW_NIBBLE (0x0FU)
|
||||
#define MASK_HIGH_NIBBLE (0xF0U)
|
||||
#define MASK_BYTE (0xFFU)
|
||||
#define MASK_WORD (0xFFFFU)
|
||||
#define MASK_6BIT (0x3FU)
|
||||
#define MASK_26BIT (0x3FFFFFFUL)
|
||||
|
||||
/*
|
||||
Timer Clock Per 100us
|
||||
*/
|
||||
#define SYSTEM_10MIN_TIME (6000000UL)
|
||||
#define TIME_01MS (10UL)
|
||||
#define TIME_10MS (100UL)
|
||||
#define TIME_20MS (200UL)
|
||||
#define TIME_50MS (500UL)
|
||||
#define TIME_100MS (1000UL)
|
||||
#define TIME_500MS (5000UL)
|
||||
#define TIME_1SEC (10000UL)
|
||||
#define TIME_5SEC (50000UL)
|
||||
#define TIME_10SEC (100000UL)
|
||||
#define TIME_60SEC (600000UL)
|
||||
|
||||
// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250
|
||||
#define SENSOR_LOW_LIMIT (2000) // 단선
|
||||
#define SENSOR_HIGH_LIMIT (4000) // 단락
|
||||
|
||||
#define TIME_OVER (1U)
|
||||
|
||||
enum
|
||||
{
|
||||
TIMER_01MS = 0U,
|
||||
TIMER_10MS,
|
||||
TIMER_20MS,
|
||||
TIMER_50MS,
|
||||
TIMER_100MS,
|
||||
TIMER_500MS,
|
||||
TIMER_1SEC,
|
||||
TIMER_MAX
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
SOFTTIMER_TIME_OVER = 0U,
|
||||
SOFTTIMER_RUNNING,
|
||||
SOFTTIMER_PAUSE,
|
||||
SOFTTIMER_DONT_EXIST
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
SOFTTIMER_WAIT_INIT = 0U,
|
||||
SOFTTIMER_WAIT_ALARM_RESET,
|
||||
SOFTTIMER_WAIT_ENG_COOLDOWN,
|
||||
SOFTTIMER_WAIT_PREHEAT,
|
||||
SOFTTIMER_WAIT_CRANKING,
|
||||
SOFTTIMER_WAIT_RETRY_CRANKING,
|
||||
SOFTTIMER_WAIT_OPERATION,
|
||||
SOFTTIMER_WAIT_SHUTDOWN,
|
||||
SOFTTIMER_WAIT_AFTER_COOLDOWN,
|
||||
SOFTTIMER_WAIT_MAX
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_CS_ENG_HEATER = 0,
|
||||
IDX_CS_GLOW_PLUG,
|
||||
IDX_CS_SOLENOID,
|
||||
IDX_CS_FUEL_PUMP,
|
||||
IDX_CS_COOLANT_PUMP,
|
||||
IDX_CS_FAN1,
|
||||
IDX_CS_FAN2,
|
||||
IDX_CS_MAX
|
||||
} E_AUX_CS_IDX;
|
||||
|
||||
typedef struct ClassSoftTimer
|
||||
{
|
||||
Uint32 ulSetValue;
|
||||
Uint32 ulDecreaseValue;
|
||||
int16 iTimer;
|
||||
int16 iStart;
|
||||
} CSoftTimer;
|
||||
|
||||
typedef struct ClassWaitTimer
|
||||
{
|
||||
Uint32 ulCountSoftClock;
|
||||
Uint16 uiSoftCountTarget;
|
||||
} CWaitTimer;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_SENSOR_ENGINE_HEATER = 0U, // 0
|
||||
IDX_SENSOR_GLOW_PLUG, // 1
|
||||
IDX_SENSOR_SOLENOID, // 2
|
||||
IDX_SENSOR_FUEL_PUMP, // 3
|
||||
IDX_SENSOR_COOLANT_PUMP, // 4
|
||||
IDX_SENSOR_FAN1, // 5
|
||||
IDX_SENSOR_FAN2, // 6
|
||||
IDX_SENSOR_MAX // 7
|
||||
} E_IDX_SENSOR;
|
||||
|
||||
typedef struct ClassGeneralOperValue
|
||||
{
|
||||
Uint16 uiFaultOccured;
|
||||
Uint16 uiDynamicRPM;
|
||||
Uint16 uiPassword[4];
|
||||
Uint16 uiSelfTestCheck;
|
||||
Uint16 uiSelfTestPass;
|
||||
Uint16 uiEmergency;
|
||||
Uint16 uiApuStart;
|
||||
Uint16 uiApuState;
|
||||
Uint16 uiAlarmReset;
|
||||
Uint16 uiMaintenance;
|
||||
Uint16 uiRetryCrankingCount;
|
||||
Uint16 uiWriteEepromDataStart;
|
||||
Uint32 ulTotalOperationHour;
|
||||
struct
|
||||
{
|
||||
Uint16 PlayCmd;
|
||||
} GcuCommand;
|
||||
struct
|
||||
{
|
||||
Uint16 EngineStart;
|
||||
Uint16 EngineStop;
|
||||
Uint16 RpmSetPoint;
|
||||
Uint16 ActiveOverride;
|
||||
Uint16 EmergencyStop;
|
||||
} EcuCommand;
|
||||
struct
|
||||
{
|
||||
Uint16 CarComputer;
|
||||
Uint16 Gcu;
|
||||
Uint16 Ecu;
|
||||
} Conection;
|
||||
struct
|
||||
{
|
||||
Uint16 ManualCranking;
|
||||
Uint16 LampTest;
|
||||
Uint16 KeyTest;
|
||||
} Maintenance;
|
||||
} CGeneralOperValue;
|
||||
|
||||
extern CGeneralOperValue GeneralOperValue;
|
||||
extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX];
|
||||
|
||||
Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime);
|
||||
void COffChipSelect(void);
|
||||
void CSoftWaitCountClear(Uint16 Index);
|
||||
Uint32 CGetSoftClock(void);
|
||||
void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond);
|
||||
void DELAY_USEC(Uint32 ulMicroSeconds);
|
||||
Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx);
|
||||
void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState);
|
||||
|
||||
#endif /* SOURCE_MAIN_H_ */
|
||||
@@ -0,0 +1,167 @@
|
||||
// TI File $Revision: /main/9 $
|
||||
// Checkin $Date: July 2, 2008 14:31:12 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Examples.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EXAMPLES_H
|
||||
#define DSP2833x_EXAMPLES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
|
||||
//
|
||||
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
|
||||
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
|
||||
|
||||
#define DSP28_PLLCR 10
|
||||
//#define DSP28_PLLCR 9
|
||||
//#define DSP28_PLLCR 8
|
||||
//#define DSP28_PLLCR 7
|
||||
//#define DSP28_PLLCR 6
|
||||
//#define DSP28_PLLCR 5
|
||||
//#define DSP28_PLLCR 4
|
||||
//#define DSP28_PLLCR 3
|
||||
//#define DSP28_PLLCR 2
|
||||
//#define DSP28_PLLCR 1
|
||||
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
|
||||
|
||||
//
|
||||
// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
|
||||
//
|
||||
// Take into account the input clock frequency and the PLL multiplier
|
||||
// selected in step 1.
|
||||
//
|
||||
// Use one of the values provided, or define your own.
|
||||
// The trailing L is required tells the compiler to treat
|
||||
// the number as a 64-bit value.
|
||||
//
|
||||
// Only one statement should be uncommented.
|
||||
//
|
||||
// Example 1:150 MHz devices:
|
||||
// CLKIN is a 30MHz crystal.
|
||||
//
|
||||
// In step 1 the user specified PLLCR = 0xA for a
|
||||
// 150Mhz CPU clock (SYSCLKOUT = 150MHz).
|
||||
//
|
||||
// In this case, the CPU_RATE will be 6.667L
|
||||
// Uncomment the line: #define CPU_RATE 6.667L
|
||||
//
|
||||
// Example 2: 100 MHz devices:
|
||||
// CLKIN is a 20MHz crystal.
|
||||
//
|
||||
// In step 1 the user specified PLLCR = 0xA for a
|
||||
// 100Mhz CPU clock (SYSCLKOUT = 100MHz).
|
||||
//
|
||||
// In this case, the CPU_RATE will be 10.000L
|
||||
// Uncomment the line: #define CPU_RATE 10.000L
|
||||
//
|
||||
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
|
||||
|
||||
//
|
||||
// Target device (in DSP2833x_Device.h) determines CPU frequency
|
||||
// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
|
||||
// (for 28332 and 28333). User does not have to change anything here.
|
||||
//
|
||||
#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only
|
||||
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
|
||||
#define CPU_FRQ_150MHZ 0
|
||||
#else
|
||||
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
|
||||
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
|
||||
#endif
|
||||
|
||||
//
|
||||
// Include Example Header Files
|
||||
//
|
||||
|
||||
//
|
||||
// Prototypes for global functions within the .c files.
|
||||
//
|
||||
#include "DSP2833x_GlobalPrototypes.h"
|
||||
#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples.
|
||||
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
|
||||
#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples.
|
||||
|
||||
#define PARTNO_28335 0xEF
|
||||
#define PARTNO_28334 0xEE
|
||||
#define PARTNO_28333 0xEA
|
||||
#define PARTNO_28332 0xED
|
||||
|
||||
//
|
||||
// Include files not used with DSP/BIOS
|
||||
//
|
||||
#ifndef DSP28_BIOS
|
||||
#include "DSP2833x_DefaultIsr.h"
|
||||
#endif
|
||||
|
||||
//
|
||||
// DO NOT MODIFY THIS LINE.
|
||||
//
|
||||
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \
|
||||
(long double)CPU_RATE) - 9.0L) / 5.0L)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EXAMPLES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: July 27, 2009 13:57:25 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Xintf.h
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interface Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_XINTF_H
|
||||
#define DSP2833x_XINTF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// XINTF timing register bit definitions
|
||||
//
|
||||
struct XTIMING_BITS { // bits description
|
||||
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
|
||||
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
|
||||
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
|
||||
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
|
||||
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
|
||||
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
|
||||
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
|
||||
Uint16 READYMODE:1; // 15 Ready mode
|
||||
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
|
||||
Uint16 rsvd1:4; // 21:18 reserved
|
||||
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
|
||||
Uint16 rsvd3:9; // 31:23 reserved
|
||||
};
|
||||
|
||||
union XTIMING_REG {
|
||||
Uint32 all;
|
||||
struct XTIMING_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF control register bit definitions
|
||||
//
|
||||
struct XINTCNF2_BITS { // bits description
|
||||
Uint16 WRBUFF:2; // 1:0 Write buffer depth
|
||||
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
|
||||
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
|
||||
Uint16 rsvd1:2; // 5:4 reserved
|
||||
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
|
||||
Uint16 rsvd2:1; // 8 reserved
|
||||
Uint16 HOLD:1; // 9 Hold enable/disable
|
||||
Uint16 HOLDS:1; // 10 Current state of HOLDn input
|
||||
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
|
||||
Uint16 rsvd3:4; // 15:12 reserved
|
||||
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
|
||||
Uint16 rsvd4:13; // 31:19 reserved
|
||||
};
|
||||
|
||||
union XINTCNF2_REG {
|
||||
Uint32 all;
|
||||
struct XINTCNF2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF bank switching register bit definitions
|
||||
//
|
||||
struct XBANK_BITS { // bits description
|
||||
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
|
||||
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
|
||||
Uint16 rsvd:10; // 15:6 reserved
|
||||
};
|
||||
|
||||
union XBANK_REG {
|
||||
Uint16 all;
|
||||
struct XBANK_BITS bit;
|
||||
};
|
||||
|
||||
struct XRESET_BITS {
|
||||
Uint16 XHARDRESET:1;
|
||||
Uint16 rsvd1:15;
|
||||
};
|
||||
|
||||
union XRESET_REG {
|
||||
Uint16 all;
|
||||
struct XRESET_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF Register File
|
||||
//
|
||||
struct XINTF_REGS {
|
||||
union XTIMING_REG XTIMING0;
|
||||
Uint32 rsvd1[5];
|
||||
union XTIMING_REG XTIMING6;
|
||||
union XTIMING_REG XTIMING7;
|
||||
Uint32 rsvd2[2];
|
||||
union XINTCNF2_REG XINTCNF2;
|
||||
Uint32 rsvd3;
|
||||
union XBANK_REG XBANK;
|
||||
Uint16 rsvd4;
|
||||
Uint16 XREVISION;
|
||||
Uint16 rsvd5[2];
|
||||
union XRESET_REG XRESET;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF External References & Function Declarations
|
||||
//
|
||||
extern volatile struct XINTF_REGS XintfRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_XINTF_H definition
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
|
||||
@@ -0,0 +1,454 @@
|
||||
/*****************************************************************************/
|
||||
/* string.h */
|
||||
/* */
|
||||
/* Copyright (c) 1993 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef _STRING_H_
|
||||
#define _STRING_H_
|
||||
|
||||
#include <_ti_config.h>
|
||||
|
||||
#if defined(__TMS320C2000__)
|
||||
#if defined(__TMS320C28XX_CLA__)
|
||||
#error "Header file <string.h> not supported by CLA compiler"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef _SIZE_T_DECLARED
|
||||
#define _SIZE_T_DECLARED
|
||||
#ifdef __clang__
|
||||
typedef __SIZE_TYPE__ size_t;
|
||||
#else
|
||||
typedef __SIZE_T_TYPE__ size_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
|
||||
|
||||
#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__))
|
||||
#define _OPT_IDECL
|
||||
#else
|
||||
#define _OPT_IDECL _IDECL
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_OPT_IDECL size_t strlen(const char *string);
|
||||
|
||||
_OPT_IDECL char *strcpy(char * __restrict dest,
|
||||
const char * __restrict src);
|
||||
_OPT_IDECL char *strncpy(char * __restrict dest,
|
||||
const char * __restrict src, size_t n);
|
||||
_OPT_IDECL char *strcat(char * __restrict string1,
|
||||
const char * __restrict string2);
|
||||
_OPT_IDECL char *strncat(char * __restrict dest,
|
||||
const char * __restrict src, size_t n);
|
||||
_OPT_IDECL char *strchr(const char *string, int c);
|
||||
_OPT_IDECL char *strrchr(const char *string, int c);
|
||||
|
||||
_OPT_IDECL int strcmp(const char *string1, const char *string2);
|
||||
_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n);
|
||||
|
||||
_CODE_ACCESS int strcoll(const char *string1, const char *_string2);
|
||||
_CODE_ACCESS size_t strxfrm(char * __restrict to,
|
||||
const char * __restrict from, size_t n);
|
||||
_CODE_ACCESS char *strpbrk(const char *string, const char *chs);
|
||||
_CODE_ACCESS size_t strspn(const char *string, const char *chs);
|
||||
_CODE_ACCESS size_t strcspn(const char *string, const char *chs);
|
||||
_CODE_ACCESS char *strstr(const char *string1, const char *string2);
|
||||
_CODE_ACCESS char *strtok(char * __restrict str1,
|
||||
const char * __restrict str2);
|
||||
_CODE_ACCESS char *strerror(int _errno);
|
||||
_CODE_ACCESS char *strdup(const char *string);
|
||||
|
||||
|
||||
_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n);
|
||||
|
||||
_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count);
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */
|
||||
_CODE_ACCESS void *memcpy(void * __restrict s1,
|
||||
const void * __restrict s2, size_t n);
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n);
|
||||
_OPT_IDECL void *memchr(const void *cs, int c, size_t n);
|
||||
|
||||
#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \
|
||||
defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__)
|
||||
_CODE_ACCESS void *memset(void *mem, int ch, size_t length);
|
||||
#else
|
||||
_OPT_IDECL void *memset(void *mem, int ch, size_t length);
|
||||
#endif
|
||||
|
||||
#if defined(__TMS320C2000__) && !defined(__TI_EABI__)
|
||||
|
||||
#ifndef __cplusplus
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
|
||||
/* keep macros as direct #defines and not function-like macros or function
|
||||
names surrounded by parentheses to support all original supported use cases
|
||||
including taking their address through the macros and prefixing with
|
||||
namespace macros */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
|
||||
#define far_memcpy __memcpy_ff
|
||||
#define far_strcpy strcpy_ff
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
size_t far_strlen(const char *s);
|
||||
char *strcpy_nf(char *s1, const char *s2);
|
||||
char *strcpy_fn(char *s1, const char *s2);
|
||||
char *strcpy_ff(char *s1, const char *s2);
|
||||
char *far_strncpy(char *s1, const char *s2, size_t n);
|
||||
char *far_strcat(char *s1, const char *s2);
|
||||
char *far_strncat(char *s1, const char *s2, size_t n);
|
||||
char *far_strchr(const char *s, int c);
|
||||
char *far_strrchr(const char *s, int c);
|
||||
int far_strcmp(const char *s1, const char *s2);
|
||||
int far_strncmp(const char *s1, const char *s2, size_t n);
|
||||
int far_strcoll(const char *s1, const char *s2);
|
||||
size_t far_strxfrm(char *s1, const char *s2, size_t n);
|
||||
char *far_strpbrk(const char *s1, const char *s2);
|
||||
size_t far_strspn(const char *s1, const char *s2);
|
||||
size_t far_strcspn(const char *s1, const char *s2);
|
||||
char *far_strstr(const char *s1, const char *s2);
|
||||
char *far_strtok(char *s1, const char *s2);
|
||||
char *far_strerror(int _errno);
|
||||
void *far_memmove(void *s1, const void *s2, size_t n);
|
||||
void *__memcpy_nf (void *_s1, const void *_s2, size_t _n);
|
||||
void *__memcpy_fn (void *_s1, const void *_s2, size_t _n);
|
||||
void *__memcpy_ff (void *_s1, const void *_s2, size_t _n);
|
||||
int far_memcmp(const void *s1, const void *s2, size_t n);
|
||||
void *far_memchr(const void *s, int c, size_t n);
|
||||
void *far_memset(void *s, int c, size_t n);
|
||||
void *far_memlcpy(void *to, const void *from,
|
||||
unsigned long n);
|
||||
void *far_memlmove(void *to, const void *from,
|
||||
unsigned long n);
|
||||
#else /* __cplusplus */
|
||||
long far_memlcpy(long to, long from, unsigned long n);
|
||||
long far_memlmove(long to, long from, unsigned long n);
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern "C" */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION)
|
||||
|
||||
#if (defined(_STRING_IMPLEMENTATION) || \
|
||||
!(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__))))
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
|
||||
|
||||
#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__)))
|
||||
#define _OPT_IDEFN
|
||||
#else
|
||||
#define _OPT_IDEFN _IDEFN
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */
|
||||
|
||||
/* MISRA exceptions to avoid changing inline versions of the functions that
|
||||
would be linked in instead of included inline at different mf levels */
|
||||
/* these functions are very well-tested, stable, and efficient; it would
|
||||
introduce a high risk to implement new, separate MISRA versions just for the
|
||||
inline headers */
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRLEN)
|
||||
_OPT_IDEFN size_t strlen(const char *string)
|
||||
{
|
||||
size_t n = (size_t)-1;
|
||||
const char *s = string;
|
||||
|
||||
do n++; while (*s++);
|
||||
return n;
|
||||
}
|
||||
#endif /* _INLINE || _STRLEN */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCPY)
|
||||
_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
|
||||
while ((*d++ = *s++));
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRCPY */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCPY)
|
||||
_OPT_IDEFN char *strncpy(char * __restrict dest,
|
||||
const char * __restrict src,
|
||||
size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
while ((*d++ = *s++) && --n); /* COPY STRING */
|
||||
if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCPY */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCAT)
|
||||
_OPT_IDEFN char *strcat(char * __restrict string1,
|
||||
const char * __restrict string2)
|
||||
{
|
||||
char *s1 = string1;
|
||||
const char *s2 = string2;
|
||||
|
||||
while (*s1) s1++; /* FIND END OF STRING */
|
||||
while ((*s1++ = *s2++)); /* APPEND SECOND STRING */
|
||||
return string1;
|
||||
}
|
||||
#endif /* _INLINE || _STRCAT */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCAT)
|
||||
_OPT_IDEFN char *strncat(char * __restrict dest,
|
||||
const char * __restrict src, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
|
||||
while (*d) d++; /* FIND END OF STRING */
|
||||
|
||||
while (n--)
|
||||
if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */
|
||||
*d = 0;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCAT */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCHR)
|
||||
_OPT_IDEFN char *strchr(const char *string, int c)
|
||||
{
|
||||
char tch, ch = c;
|
||||
const char *s = string;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
if ((tch = *s) == ch) return (char *) s;
|
||||
if (!tch) return (char *) 0;
|
||||
s++;
|
||||
}
|
||||
}
|
||||
#endif /* _INLINE || _STRCHR */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRRCHR)
|
||||
_OPT_IDEFN char *strrchr(const char *string, int c)
|
||||
{
|
||||
char tch, ch = c;
|
||||
char *result = 0;
|
||||
const char *s = string;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
if ((tch = *s) == ch) result = (char *) s;
|
||||
if (!tch) break;
|
||||
s++;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif /* _INLINE || _STRRCHR */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCMP)
|
||||
_OPT_IDEFN int strcmp(const char *string1, const char *string2)
|
||||
{
|
||||
int c1, res;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
c1 = (unsigned char)*string1++;
|
||||
res = c1 - (unsigned char)*string2++;
|
||||
|
||||
if (c1 == 0 || res != 0) break;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
#endif /* _INLINE || _STRCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCMP)
|
||||
_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const char *s1 = string1;
|
||||
const char *s2 = string2;
|
||||
unsigned char cp;
|
||||
int result;
|
||||
|
||||
do
|
||||
if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++)))
|
||||
return result;
|
||||
while (cp && --n);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_MEMCMP)
|
||||
_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const unsigned char *mem1 = (unsigned char *)cs;
|
||||
const unsigned char *mem2 = (unsigned char *)ct;
|
||||
int cp1, cp2;
|
||||
|
||||
while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n);
|
||||
return cp1 - cp2;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* _INLINE || _MEMCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_MEMCHR)
|
||||
_OPT_IDEFN void *memchr(const void *cs, int c, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const unsigned char *mem = (unsigned char *)cs;
|
||||
unsigned char ch = c;
|
||||
|
||||
do
|
||||
if ( *mem == ch ) return (void *)mem;
|
||||
else mem++;
|
||||
while (--n);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
#endif /* _INLINE || _MEMCHR */
|
||||
|
||||
#if (((defined(_INLINE) || defined(_MEMSET)) && \
|
||||
!(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \
|
||||
!defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__))
|
||||
_OPT_IDEFN void *memset(void *mem, int ch, size_t length)
|
||||
{
|
||||
char *m = (char *)mem;
|
||||
|
||||
while (length--) *m++ = ch;
|
||||
return mem;
|
||||
}
|
||||
#endif /* _INLINE || _MEMSET */
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */
|
||||
|
||||
#endif /* (_INLINE || _STRING_IMPLEMENTATION) */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */
|
||||
/* this file will have already included sys/cdefs.h. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#if __has_include(<sys/cdefs.h>)
|
||||
#include <sys/cdefs.h>
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Include xlocale/_string.h if POSIX is enabled. This will expose the */
|
||||
/* xlocale string interface. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
|
||||
__BEGIN_DECLS
|
||||
#include <xlocale/_string.h>
|
||||
__END_DECLS
|
||||
#endif
|
||||
|
||||
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
|
||||
_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict);
|
||||
_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t);
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* ! _STRING_H_ */
|
||||
@@ -0,0 +1,74 @@
|
||||
/*****************************************************************************/
|
||||
/* linkage.h */
|
||||
/* */
|
||||
/* Copyright (c) 1998 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef _LINKAGE
|
||||
#define _LINKAGE
|
||||
|
||||
#pragma diag_push
|
||||
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */
|
||||
|
||||
/* No modifiers needed to access code */
|
||||
|
||||
#define _CODE_ACCESS
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _DATA_ACCESS ==> how to access RTS global or static data */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#define _DATA_ACCESS
|
||||
#define _DATA_ACCESS_NEAR
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#ifndef _OPTIMIZE_FOR_SPACE
|
||||
#define _OPTIMIZE_FOR_SPACE 1
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _IDECL ==> how inline functions are declared */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#ifdef _INLINE
|
||||
#define _IDECL static __inline
|
||||
#define _IDEFN static __inline
|
||||
#else
|
||||
#define _IDECL extern _CODE_ACCESS
|
||||
#define _IDEFN _CODE_ACCESS
|
||||
#endif
|
||||
|
||||
#pragma diag_pop
|
||||
|
||||
#endif /* _LINKAGE */
|
||||
@@ -0,0 +1,145 @@
|
||||
/*****************************************************************************/
|
||||
/* _ti_config.h */
|
||||
/* */
|
||||
/* Copyright (c) 2017 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef __TI_CONFIG_H
|
||||
#define __TI_CONFIG_H
|
||||
|
||||
/*Unsupported pragmas are omitted */
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
# pragma diag_push
|
||||
# pragma CHECK_MISRA("-19.7")
|
||||
# pragma CHECK_MISRA("-19.4")
|
||||
# pragma CHECK_MISRA("-19.1")
|
||||
# pragma CHECK_MISRA("-19.15")
|
||||
# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg)
|
||||
# pragma diag_pop
|
||||
#else
|
||||
# define _TI_PROPRIETARY_PRAGMA(arg)
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")")
|
||||
|
||||
/* Hide uses of the TI proprietary macros behind other macros.
|
||||
Implementations that don't implement these features should leave
|
||||
these macros undefined. */
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
# ifdef __TI_STRICT_ANSI_MODE__
|
||||
# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
|
||||
# endif
|
||||
|
||||
# ifdef __TI_STRICT_FP_MODE__
|
||||
# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
|
||||
# endif
|
||||
|
||||
# ifdef __unsigned_chars__
|
||||
# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_UNSIGNED_CHARS__
|
||||
# endif
|
||||
#else
|
||||
# undef __TI_PROPRIETARY_UNSIGNED_CHARS__
|
||||
# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
|
||||
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
|
||||
#endif
|
||||
|
||||
/* Common definitions */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
/* C++ */
|
||||
# if (__cplusplus >= 201103L)
|
||||
/* C++11 */
|
||||
# define _TI_NORETURN [[noreturn]]
|
||||
# define _TI_NOEXCEPT noexcept
|
||||
# else
|
||||
/* C++98/03 */
|
||||
# define _TI_NORETURN __attribute__((noreturn))
|
||||
# define _TI_NOEXCEPT throw()
|
||||
# endif
|
||||
#else
|
||||
/* C */
|
||||
# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
|
||||
/* C11 */
|
||||
# define _TI_NORETURN _Noreturn
|
||||
# else
|
||||
/* C89/C99 */
|
||||
# define _TI_NORETURN __attribute__((noreturn))
|
||||
# endif
|
||||
# define _TI_NOEXCEPT
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus) && (__cplusplus >= 201103L)
|
||||
# define _TI_CPP11LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus) && (__cplusplus >= 201402L)
|
||||
# define _TI_CPP14LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \
|
||||
defined(_TI_CPP11LIB)
|
||||
# define _TI_C99LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \
|
||||
defined(_TI_CPP14LIB)
|
||||
# define _TI_C11LIB 1
|
||||
#endif
|
||||
|
||||
/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It
|
||||
is intended to be used for functions like abort and atexit that are supposed
|
||||
to be declared noexcept only in C++14 mode. */
|
||||
#ifdef _TI_CPP14LIB
|
||||
# define _TI_NOEXCEPT_CPP14 noexcept
|
||||
#else
|
||||
# define _TI_NOEXCEPT_CPP14
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Target-specific definitions */
|
||||
#include <linkage.h>
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* ifndef __TI_CONFIG_H */
|
||||
@@ -0,0 +1,270 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:13 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EQep.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
|
||||
// Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EQEP_H
|
||||
#define DSP2833x_EQEP_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Capture decoder control register bit definitions
|
||||
//
|
||||
struct QDECCTL_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 QSP:1; // 5 QEPS input polarity
|
||||
Uint16 QIP:1; // 6 QEPI input polarity
|
||||
Uint16 QBP:1; // 7 QEPB input polarity
|
||||
Uint16 QAP:1; // 8 QEPA input polarity
|
||||
Uint16 IGATE:1; // 9 Index pulse gating option
|
||||
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
|
||||
Uint16 XCR:1; // 11 External clock rate
|
||||
Uint16 SPSEL:1; // 12 Sync output pin select
|
||||
Uint16 SOEN:1; // 13 Enable position compare sync
|
||||
Uint16 QSRC:2; // 15:14 Position counter source
|
||||
};
|
||||
|
||||
union QDECCTL_REG {
|
||||
Uint16 all;
|
||||
struct QDECCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP control register bit definitions
|
||||
//
|
||||
struct QEPCTL_BITS { // bits description
|
||||
Uint16 WDE:1; // 0 QEP watchdog enable
|
||||
Uint16 UTE:1; // 1 QEP unit timer enable
|
||||
Uint16 QCLM:1; // 2 QEP capture latch mode
|
||||
Uint16 QPEN:1; // 3 Quadrature position counter enable
|
||||
Uint16 IEL:2; // 5:4 Index event latch
|
||||
Uint16 SEL:1; // 6 Strobe event latch
|
||||
Uint16 SWI:1; // 7 Software init position counter
|
||||
Uint16 IEI:2; // 9:8 Index event init of position count
|
||||
Uint16 SEI:2; // 11:10 Strobe event init
|
||||
Uint16 PCRM:2; // 13:12 Position counter reset
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union QEPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QEPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Quadrature capture control register bit definitions
|
||||
//
|
||||
struct QCAPCTL_BITS { // bits description
|
||||
Uint16 UPPS:4; // 3:0 Unit position pre-scale
|
||||
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
|
||||
Uint16 rsvd1:8; // 14:7 reserved
|
||||
Uint16 CEN:1; // 15 Enable QEP capture
|
||||
};
|
||||
|
||||
union QCAPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QCAPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Position compare control register bit definitions
|
||||
//
|
||||
struct QPOSCTL_BITS { // bits description
|
||||
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
|
||||
Uint16 PCE:1; // 12 Position compare enable/disable
|
||||
Uint16 PCPOL:1; // 13 Polarity of sync output
|
||||
Uint16 PCLOAD:1; // 14 Position compare of shadow load
|
||||
Uint16 PCSHDW:1; // 15 Position compare shadow enable
|
||||
};
|
||||
|
||||
union QPOSCTL_REG {
|
||||
Uint16 all;
|
||||
struct QPOSCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt control register bit definitions
|
||||
//
|
||||
struct QEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 QPE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union QEINT_REG {
|
||||
Uint16 all;
|
||||
struct QEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt status register bit definitions
|
||||
//
|
||||
struct QFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global interrupt
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 PHE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union QFLG_REG {
|
||||
Uint16 all;
|
||||
struct QFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt force register bit definitions
|
||||
//
|
||||
struct QFRC_BITS { // bits description
|
||||
Uint16 reserved:1; // 0 Reserved
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 PHE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
|
||||
union QFRC_REG {
|
||||
Uint16 all;
|
||||
struct QFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// V1.1 Added UPEVNT (bit 7) This reflects changes
|
||||
// made as of F2833x Rev A devices
|
||||
//
|
||||
|
||||
//
|
||||
// QEP status register bit definitions
|
||||
//
|
||||
struct QEPSTS_BITS { // bits description
|
||||
Uint16 PCEF:1; // 0 Position counter error
|
||||
Uint16 FIMF:1; // 1 First index marker
|
||||
Uint16 CDEF:1; // 2 Capture direction error
|
||||
Uint16 COEF:1; // 3 Capture overflow error
|
||||
Uint16 QDLF:1; // 4 QEP direction latch
|
||||
Uint16 QDF:1; // 5 Quadrature direction
|
||||
Uint16 FIDF:1; // 6 Direction on first index marker
|
||||
Uint16 UPEVNT:1; // 7 Unit position event flag
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union QEPSTS_REG {
|
||||
Uint16 all;
|
||||
struct QEPSTS_BITS bit;
|
||||
};
|
||||
|
||||
struct EQEP_REGS {
|
||||
Uint32 QPOSCNT; // Position counter
|
||||
Uint32 QPOSINIT; // Position counter init
|
||||
Uint32 QPOSMAX; // Maximum position count
|
||||
Uint32 QPOSCMP; // Position compare
|
||||
Uint32 QPOSILAT; // Index position latch
|
||||
Uint32 QPOSSLAT; // Strobe position latch
|
||||
Uint32 QPOSLAT; // Position latch
|
||||
Uint32 QUTMR; // Unit timer
|
||||
Uint32 QUPRD; // Unit period
|
||||
Uint16 QWDTMR; // QEP watchdog timer
|
||||
Uint16 QWDPRD; // QEP watchdog period
|
||||
union QDECCTL_REG QDECCTL; // Quadrature decoder control
|
||||
union QEPCTL_REG QEPCTL; // QEP control
|
||||
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
|
||||
union QPOSCTL_REG QPOSCTL; // Position compare control
|
||||
union QEINT_REG QEINT; // QEP interrupt control
|
||||
union QFLG_REG QFLG; // QEP interrupt flag
|
||||
union QFLG_REG QCLR; // QEP interrupt clear
|
||||
union QFRC_REG QFRC; // QEP interrupt force
|
||||
union QEPSTS_REG QEPSTS; // QEP status
|
||||
Uint16 QCTMR; // QEP capture timer
|
||||
Uint16 QCPRD; // QEP capture period
|
||||
Uint16 QCTMRLAT; // QEP capture latch
|
||||
Uint16 QCPRDLAT; // QEP capture period latch
|
||||
Uint16 rsvd1[30]; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct EQEP_REGS EQep1Regs;
|
||||
extern volatile struct EQEP_REGS EQep2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EQEP_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,465 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:10 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EPWM_H
|
||||
#define DSP2833x_EPWM_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Time base control register bit definitions
|
||||
//
|
||||
struct TBCTL_BITS { // bits description
|
||||
Uint16 CTRMODE:2; // 1:0 Counter Mode
|
||||
Uint16 PHSEN:1; // 2 Phase load enable
|
||||
Uint16 PRDLD:1; // 3 Active period load
|
||||
Uint16 SYNCOSEL:2; // 5:4 Sync output select
|
||||
Uint16 SWFSYNC:1; // 6 Software force sync pulse
|
||||
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
|
||||
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
|
||||
Uint16 PHSDIR:1; // 13 Phase Direction
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union TBCTL_REG {
|
||||
Uint16 all;
|
||||
struct TBCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Time base status register bit definitions
|
||||
//
|
||||
struct TBSTS_BITS { // bits description
|
||||
Uint16 CTRDIR:1; // 0 Counter direction status
|
||||
Uint16 SYNCI:1; // 1 External input sync status
|
||||
Uint16 CTRMAX:1; // 2 Counter max latched status
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TBSTS_REG {
|
||||
Uint16 all;
|
||||
struct TBSTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Compare control register bit definitions
|
||||
//
|
||||
struct CMPCTL_BITS { // bits description
|
||||
Uint16 LOADAMODE:2; // 0:1 Active compare A
|
||||
Uint16 LOADBMODE:2; // 3:2 Active compare B
|
||||
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
|
||||
Uint16 rsvd1:1; // 5 reserved
|
||||
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
|
||||
Uint16 rsvd2:1; // 7 reserved
|
||||
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
|
||||
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
|
||||
Uint16 rsvd3:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union CMPCTL_REG {
|
||||
Uint16 all;
|
||||
struct CMPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier register bit definitions
|
||||
//
|
||||
struct AQCTL_BITS { // bits description
|
||||
Uint16 ZRO:2; // 1:0 Action Counter = Zero
|
||||
Uint16 PRD:2; // 3:2 Action Counter = Period
|
||||
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
|
||||
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
|
||||
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
|
||||
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
|
||||
Uint16 rsvd:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union AQCTL_REG {
|
||||
Uint16 all;
|
||||
struct AQCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier SW force register bit definitions
|
||||
//
|
||||
struct AQSFRC_BITS { // bits description
|
||||
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
|
||||
Uint16 OTSFA:1; // 2 One-time SW Force A output
|
||||
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
|
||||
Uint16 OTSFB:1; // 5 One-time SW Force A output
|
||||
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union AQSFRC_REG {
|
||||
Uint16 all;
|
||||
struct AQSFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier continuous SW force register bit definitions
|
||||
//
|
||||
struct AQCSFRC_BITS { // bits description
|
||||
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
|
||||
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union AQCSFRC_REG {
|
||||
Uint16 all;
|
||||
struct AQCSFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// As of version 1.1
|
||||
// Changed the MODE bit-field to OUT_MODE
|
||||
// Added the bit-field IN_MODE
|
||||
// This corresponds to changes in silicon as of F2833x devices
|
||||
// Rev A silicon.
|
||||
//
|
||||
|
||||
//
|
||||
// Dead-band generator control register bit definitions
|
||||
//
|
||||
struct DBCTL_BITS { // bits description
|
||||
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
|
||||
Uint16 POLSEL:2; // 3:2 Polarity Select Control
|
||||
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
|
||||
Uint16 rsvd1:10; // 15:4 reserved
|
||||
};
|
||||
|
||||
union DBCTL_REG {
|
||||
Uint16 all;
|
||||
struct DBCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone select register bit definitions
|
||||
//
|
||||
struct TZSEL_BITS { // bits description
|
||||
Uint16 CBC1:1; // 0 TZ1 CBC select
|
||||
Uint16 CBC2:1; // 1 TZ2 CBC select
|
||||
Uint16 CBC3:1; // 2 TZ3 CBC select
|
||||
Uint16 CBC4:1; // 3 TZ4 CBC select
|
||||
Uint16 CBC5:1; // 4 TZ5 CBC select
|
||||
Uint16 CBC6:1; // 5 TZ6 CBC select
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 OSHT1:1; // 8 One-shot TZ1 select
|
||||
Uint16 OSHT2:1; // 9 One-shot TZ2 select
|
||||
Uint16 OSHT3:1; // 10 One-shot TZ3 select
|
||||
Uint16 OSHT4:1; // 11 One-shot TZ4 select
|
||||
Uint16 OSHT5:1; // 12 One-shot TZ5 select
|
||||
Uint16 OSHT6:1; // 13 One-shot TZ6 select
|
||||
Uint16 rsvd2:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union TZSEL_REG {
|
||||
Uint16 all;
|
||||
struct TZSEL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone control register bit definitions
|
||||
//
|
||||
struct TZCTL_BITS { // bits description
|
||||
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
|
||||
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
|
||||
Uint16 rsvd:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union TZCTL_REG {
|
||||
Uint16 all;
|
||||
struct TZCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone control register bit definitions
|
||||
//
|
||||
struct TZEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZEINT_REG {
|
||||
Uint16 all;
|
||||
struct TZEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag register bit definitions
|
||||
//
|
||||
struct TZFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global status
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZFLG_REG {
|
||||
Uint16 all;
|
||||
struct TZFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag clear register bit definitions
|
||||
//
|
||||
struct TZCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global status
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZCLR_REG {
|
||||
Uint16 all;
|
||||
struct TZCLR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag force register bit definitions
|
||||
//
|
||||
struct TZFRC_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZFRC_REG {
|
||||
Uint16 all;
|
||||
struct TZFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger select register bit definitions
|
||||
//
|
||||
struct ETSEL_BITS { // bits description
|
||||
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
|
||||
Uint16 INTEN:1; // 3 EPWMxINTn Enable
|
||||
Uint16 rsvd1:4; // 7:4 reserved
|
||||
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
|
||||
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
|
||||
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
|
||||
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
|
||||
};
|
||||
|
||||
union ETSEL_REG {
|
||||
Uint16 all;
|
||||
struct ETSEL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger pre-scale register bit definitions
|
||||
//
|
||||
struct ETPS_BITS { // bits description
|
||||
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
|
||||
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
|
||||
Uint16 rsvd1:4; // 7:4 reserved
|
||||
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
|
||||
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
|
||||
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
|
||||
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
|
||||
};
|
||||
|
||||
union ETPS_REG {
|
||||
Uint16 all;
|
||||
struct ETPS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Flag register bit definitions
|
||||
//
|
||||
struct ETFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Flag
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETFLG_REG {
|
||||
Uint16 all;
|
||||
struct ETFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Clear register bit definitions
|
||||
//
|
||||
struct ETCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Clear
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETCLR_REG {
|
||||
Uint16 all;
|
||||
struct ETCLR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Force register bit definitions
|
||||
//
|
||||
struct ETFRC_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Force
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Force
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Force
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETFRC_REG {
|
||||
Uint16 all;
|
||||
struct ETFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PWM chopper control register bit definitions
|
||||
//
|
||||
struct PCCTL_BITS { // bits description
|
||||
Uint16 CHPEN:1; // 0 PWM chopping enable
|
||||
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
|
||||
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
|
||||
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
|
||||
Uint16 rsvd1:5; // 15:11 reserved
|
||||
};
|
||||
|
||||
union PCCTL_REG {
|
||||
Uint16 all;
|
||||
struct PCCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct HRCNFG_BITS { // bits description
|
||||
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
|
||||
Uint16 CTLMODE:1; // 2 Control mode Select Bit
|
||||
Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union HRCNFG_REG {
|
||||
Uint16 all;
|
||||
struct HRCNFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TBPHS_HRPWM_REG { //bits description
|
||||
Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits)
|
||||
Uint16 TBPHS; //31:16 Phase offset register
|
||||
};
|
||||
|
||||
union TBPHS_HRPWM_GROUP {
|
||||
Uint32 all;
|
||||
struct TBPHS_HRPWM_REG half;
|
||||
};
|
||||
|
||||
struct CMPA_HRPWM_REG { // bits description
|
||||
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
|
||||
Uint16 CMPA; // 31:16 Compare A reg
|
||||
};
|
||||
|
||||
union CMPA_HRPWM_GROUP {
|
||||
Uint32 all;
|
||||
struct CMPA_HRPWM_REG half;
|
||||
};
|
||||
|
||||
struct EPWM_REGS {
|
||||
union TBCTL_REG TBCTL; //
|
||||
union TBSTS_REG TBSTS; //
|
||||
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
|
||||
Uint16 TBCTR; // Counter
|
||||
Uint16 TBPRD; // Period register set
|
||||
Uint16 rsvd1; //
|
||||
union CMPCTL_REG CMPCTL; // Compare control
|
||||
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
|
||||
Uint16 CMPB; // Compare B reg
|
||||
union AQCTL_REG AQCTLA; // Action qual output A
|
||||
union AQCTL_REG AQCTLB; // Action qual output B
|
||||
union AQSFRC_REG AQSFRC; // Action qual SW force
|
||||
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
|
||||
union DBCTL_REG DBCTL; // Dead-band control
|
||||
Uint16 DBRED; // Dead-band rising edge delay
|
||||
Uint16 DBFED; // Dead-band falling edge delay
|
||||
union TZSEL_REG TZSEL; // Trip zone select
|
||||
Uint16 rsvd2;
|
||||
union TZCTL_REG TZCTL; // Trip zone control
|
||||
union TZEINT_REG TZEINT; // Trip zone interrupt enable
|
||||
union TZFLG_REG TZFLG; // Trip zone interrupt flags
|
||||
union TZCLR_REG TZCLR; // Trip zone clear
|
||||
union TZFRC_REG TZFRC; // Trip zone force interrupt
|
||||
union ETSEL_REG ETSEL; // Event trigger selection
|
||||
union ETPS_REG ETPS; // Event trigger pre-scaler
|
||||
union ETFLG_REG ETFLG; // Event trigger flags
|
||||
union ETCLR_REG ETCLR; // Event trigger clear
|
||||
union ETFRC_REG ETFRC; // Event trigger force
|
||||
union PCCTL_REG PCCTL; // PWM chopper control
|
||||
Uint16 rsvd3; //
|
||||
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct EPWM_REGS EPwm1Regs;
|
||||
extern volatile struct EPWM_REGS EPwm2Regs;
|
||||
extern volatile struct EPWM_REGS EPwm3Regs;
|
||||
extern volatile struct EPWM_REGS EPwm4Regs;
|
||||
extern volatile struct EPWM_REGS EPwm5Regs;
|
||||
extern volatile struct EPWM_REGS EPwm6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EPWM_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,730 @@
|
||||
/* ========================================================================= */
|
||||
/* 1. Includes */
|
||||
/* ========================================================================= */
|
||||
#include "main.h"
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */
|
||||
/* ========================================================================= */
|
||||
static void CInitSystem(void);
|
||||
static void COledDisplay(void);
|
||||
static void CInitGeneralOperValue(void);
|
||||
static void CInitGpio(void);
|
||||
static void CSystemConfigure(void);
|
||||
static void CMappingInterrupt(void);
|
||||
static void CProcessSoftTimer(void);
|
||||
static void CShutdownProcedure(void);
|
||||
static Uint16 CPowerOnCheck(void);
|
||||
static void CSoftTimerWorkProcess(void);
|
||||
static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex);
|
||||
static void CReloadSoftTimer(Uint16 uiTimerIndex);
|
||||
static void CInitSoftTimers(void);
|
||||
static void CInitSoftTimer(void);
|
||||
static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay);
|
||||
static void CStartSoftTimer(Uint16 uiTimerIndex);
|
||||
static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock);
|
||||
static void CInitI2C(void);
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */
|
||||
/* ========================================================================= */
|
||||
Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U };
|
||||
|
||||
CGeneralOperValue GeneralOperValue;
|
||||
|
||||
static CSoftTimer SoftTimer[TIMER_MAX];
|
||||
static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX];
|
||||
static Uint32 ulSoftClock;
|
||||
|
||||
/* ========================================================================= */
|
||||
/* Function Definitions */
|
||||
/* ========================================================================= */
|
||||
int main(void)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT;
|
||||
|
||||
CInitSystem();
|
||||
|
||||
CInitOled();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL;
|
||||
|
||||
AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작
|
||||
|
||||
for ( ; ; )
|
||||
{
|
||||
CShutdownProcedure();
|
||||
|
||||
CSoftTimerWorkProcess();
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL)
|
||||
{
|
||||
if (OledOperValue.uiProgressDone == 1U)
|
||||
{
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
COledBufferReset();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST)
|
||||
{
|
||||
if (GeneralOperValue.uiSelfTestCheck == 0U)
|
||||
{
|
||||
GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함
|
||||
|
||||
GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상
|
||||
{
|
||||
COledBufferReset();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef AUX_TEST
|
||||
if (Rx400.AuxControl.AuxTestStart == 1U)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U);
|
||||
}
|
||||
// 정비 모드가 꺼져있어야 시퀀스 동작.
|
||||
else if (GeneralOperValue.uiMaintenance == 0U)
|
||||
#else
|
||||
if (GeneralOperValue.uiMaintenance == 0U)
|
||||
#endif
|
||||
{
|
||||
if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF
|
||||
{
|
||||
CApuOperProcedure(); // 엔진 운영 프로시저
|
||||
|
||||
CLedControlProcedure(); // LED 제어 프로시저
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CDebugModeProcedure();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CSoftTimerWorkProcess(void)
|
||||
{
|
||||
Uint16 ui01msExcute;
|
||||
Uint16 ui10msExcute;
|
||||
Uint16 ui100msExcute;
|
||||
|
||||
ui01msExcute = CIsStatusSoftTimer(TIMER_01MS);
|
||||
ui10msExcute = CIsStatusSoftTimer(TIMER_10MS);
|
||||
ui100msExcute = CIsStatusSoftTimer(TIMER_100MS);
|
||||
|
||||
if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_01MS);
|
||||
|
||||
if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지
|
||||
{
|
||||
CAlarmProcedure();
|
||||
CDisplayAlarmPopup();
|
||||
}
|
||||
|
||||
// (정비모드:키테스트)가 아니면 키 입력 처리 시작 함.
|
||||
if (GeneralOperValue.Maintenance.KeyTest == 0U)
|
||||
{
|
||||
CKeyCheckProcedure();
|
||||
CKeyWaitCount();
|
||||
}
|
||||
}
|
||||
|
||||
if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_10MS);
|
||||
|
||||
CSendECanDataB();
|
||||
COledDisplay();
|
||||
}
|
||||
|
||||
if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_100MS);
|
||||
CSendECanDataA();
|
||||
CDisplayAntiNoiseRefresh();
|
||||
}
|
||||
}
|
||||
|
||||
static void COledDisplay(void)
|
||||
{
|
||||
static Uint16 RefeshDelay = 0U;
|
||||
|
||||
// 부트 상태 이 후 프로그래스바 화면 표시용
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL)
|
||||
{
|
||||
CInitializePage();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RefeshDelay == 0U) // 10ms 주기를 위함
|
||||
{
|
||||
// POST 상태 표시 용
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST)
|
||||
{
|
||||
CDisplayPostFail();
|
||||
}
|
||||
else
|
||||
{
|
||||
// POST 이 후 화면 표시용
|
||||
CSetPage(OledOperValue.uiPageNum);
|
||||
}
|
||||
}
|
||||
RefeshDelay = (RefeshDelay + 1U) % 10U;
|
||||
}
|
||||
|
||||
COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT);
|
||||
}
|
||||
|
||||
void CSoftWaitCountClear(Uint16 Index)
|
||||
{
|
||||
WaitTimer[Index].ulCountSoftClock = 0U;
|
||||
WaitTimer[Index].uiSoftCountTarget = 0U;
|
||||
}
|
||||
|
||||
static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
Uint16 isRunning = 1U;
|
||||
|
||||
if (SoftTimer[uiTimerIndex].iStart != -1)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iStart == 1)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U)
|
||||
{
|
||||
isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success
|
||||
}
|
||||
else
|
||||
{
|
||||
isRunning = (Uint16)SOFTTIMER_RUNNING;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return isRunning;
|
||||
}
|
||||
|
||||
static void CReloadSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iTimer != -1)
|
||||
{
|
||||
SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue;
|
||||
}
|
||||
}
|
||||
|
||||
Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime)
|
||||
{
|
||||
Uint16 isCountOver = 0U;
|
||||
|
||||
switch (WaitTimer[uiIndex].uiSoftCountTarget)
|
||||
{
|
||||
case 0U:
|
||||
{
|
||||
WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock();
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 1U;
|
||||
break;
|
||||
}
|
||||
case 1U:
|
||||
{
|
||||
if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 2U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
WaitTimer[uiIndex].ulCountSoftClock = 0U;
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 0U;
|
||||
isCountOver = 1U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return isCountOver;
|
||||
}
|
||||
|
||||
static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock)
|
||||
{
|
||||
Uint16 isRunning = 1U;
|
||||
Uint32 ulCpuClock = CGetSoftClock();
|
||||
|
||||
if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock)
|
||||
{
|
||||
isRunning = 0U;
|
||||
}
|
||||
|
||||
return isRunning;
|
||||
}
|
||||
|
||||
Uint32 CGetSoftClock(void)
|
||||
{
|
||||
return ulSoftClock;
|
||||
}
|
||||
|
||||
static void CInitSystem(void)
|
||||
{
|
||||
DINT;
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitSysCtrl();
|
||||
|
||||
CInitGpio(); // GPIO Direction and mux
|
||||
|
||||
InitPieCtrl();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitPieVectTable();
|
||||
|
||||
InitCpuTimers();
|
||||
|
||||
ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec
|
||||
|
||||
CSystemConfigure();
|
||||
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
|
||||
CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0
|
||||
}
|
||||
|
||||
static void CInitGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// GPIO MUX Setting
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA
|
||||
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA)
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA)
|
||||
|
||||
// GPIO Direction Setting '1' Output, '0' Input
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR
|
||||
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA
|
||||
|
||||
// GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous
|
||||
GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling
|
||||
|
||||
// Gpio Default Value Initial
|
||||
GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
|
||||
GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N
|
||||
GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N
|
||||
GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void COffChipSelect(void)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, 0U);
|
||||
}
|
||||
|
||||
static interrupt void CMainTimer0Interrupt(void)
|
||||
{
|
||||
// Per 100uSec
|
||||
|
||||
DINT;
|
||||
|
||||
ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME;
|
||||
|
||||
CProcessSoftTimer();
|
||||
// Do Something
|
||||
|
||||
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
|
||||
EINT;
|
||||
}
|
||||
|
||||
static void CSystemConfigure(void)
|
||||
{
|
||||
CMappingInterrupt();
|
||||
|
||||
CInitGeneralOperValue();
|
||||
|
||||
CInitAdc();
|
||||
CInitEcan();
|
||||
|
||||
CInitI2C();
|
||||
|
||||
CInitXintf();
|
||||
|
||||
CInitSoftTimers();
|
||||
|
||||
CInitKeyOperValue();
|
||||
}
|
||||
|
||||
static void CInitGeneralOperValue(void)
|
||||
{
|
||||
(void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue));
|
||||
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0;
|
||||
|
||||
GeneralOperValue.EcuCommand.EngineStop = 1U;
|
||||
}
|
||||
|
||||
static void CMappingInterrupt(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Interrupt Vector Remapping
|
||||
PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0
|
||||
PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC
|
||||
PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA
|
||||
PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB
|
||||
|
||||
PieVectTable.TINT0 = &CMainTimer0Interrupt;
|
||||
PieVectTable.ECAN0INTA = &CECanInterruptA;
|
||||
PieVectTable.ECAN0INTB = &CECanInterruptB;
|
||||
PieVectTable.ADCINT = &CAdcInterrupt;
|
||||
|
||||
IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9);
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
static void CProcessSoftTimer(void)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
for (i = 0U; i < (Uint16)TIMER_MAX; i++)
|
||||
{
|
||||
if (SoftTimer[i].iTimer != -1)
|
||||
{
|
||||
if (SoftTimer[i].iStart == 1)
|
||||
{
|
||||
if (SoftTimer[i].ulDecreaseValue > 0UL)
|
||||
{
|
||||
SoftTimer[i].ulDecreaseValue--;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CInitSoftTimers(void)
|
||||
{
|
||||
CInitSoftTimer();
|
||||
CConfigSoftTimer(TIMER_01MS, TIME_01MS);
|
||||
CConfigSoftTimer(TIMER_10MS, TIME_10MS);
|
||||
CConfigSoftTimer(TIMER_20MS, TIME_20MS);
|
||||
CConfigSoftTimer(TIMER_50MS, TIME_50MS);
|
||||
CConfigSoftTimer(TIMER_100MS, TIME_100MS);
|
||||
CConfigSoftTimer(TIMER_500MS, TIME_500MS);
|
||||
|
||||
CStartSoftTimer(TIMER_01MS);
|
||||
CStartSoftTimer(TIMER_10MS);
|
||||
CStartSoftTimer(TIMER_20MS);
|
||||
CStartSoftTimer(TIMER_50MS);
|
||||
CStartSoftTimer(TIMER_100MS);
|
||||
CStartSoftTimer(TIMER_500MS);
|
||||
}
|
||||
|
||||
static void CStartSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iTimer != -1)
|
||||
{
|
||||
SoftTimer[uiTimerIndex].iStart = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void CInitSoftTimer(void)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
(void)memset(&SoftTimer, 0, sizeof(SoftTimer));
|
||||
(void)memset(&WaitTimer, 0, sizeof(WaitTimer));
|
||||
|
||||
for (i = 0; i < (Uint16)TIMER_MAX; i++)
|
||||
{
|
||||
SoftTimer[i].iTimer = -1;
|
||||
}
|
||||
}
|
||||
|
||||
static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay)
|
||||
{
|
||||
SoftTimer[TimerIndex].iTimer = (int16) TimerIndex;
|
||||
SoftTimer[TimerIndex].ulSetValue = Delay;
|
||||
SoftTimer[TimerIndex].ulDecreaseValue = Delay;
|
||||
SoftTimer[TimerIndex].iStart = 0;
|
||||
}
|
||||
|
||||
static Uint16 CPowerOnCheck(void)
|
||||
{
|
||||
Uint16 result = 1U;
|
||||
Uint16 uiTemp = 0U;
|
||||
Uint16 i;
|
||||
|
||||
// Check EngineHeater V/I Sensor
|
||||
uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp;
|
||||
|
||||
// Check GlowPlug V/I Sensor
|
||||
uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp;
|
||||
|
||||
// Check Solenoid V/I Sensor
|
||||
uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp;
|
||||
|
||||
// Check FuelPump V/I Sensor
|
||||
uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp;
|
||||
|
||||
// Check CoolantPump V/I Sensor
|
||||
uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp;
|
||||
|
||||
// Check Fan1 V/I Sensor
|
||||
uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp;
|
||||
|
||||
// Check Fan2 V/I Sensor
|
||||
uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp;
|
||||
|
||||
for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++)
|
||||
{
|
||||
if (PowerOnCheckSensor[i] > 0U)
|
||||
{
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return result; // '0' 정상
|
||||
}
|
||||
|
||||
static void CInitI2C(void)
|
||||
{
|
||||
/* I2C 모듈 리셋 */
|
||||
I2caRegs.I2CMDR.bit.IRS = 0U;
|
||||
|
||||
/*
|
||||
* 1. I2C 프리스케일러 (I2CPSC) 설정
|
||||
* SYSCLKOUT = 150MHz 기준
|
||||
* 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14
|
||||
*/
|
||||
I2caRegs.I2CPSC.all = 14U;
|
||||
|
||||
/*
|
||||
* 2. I2C 마스터 클럭 (SCL) 설정
|
||||
* 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25
|
||||
*/
|
||||
//I2caRegs.I2CCLKL = 45U; // 100kHz
|
||||
//I2caRegs.I2CCLKH = 45U; // 100kHz
|
||||
I2caRegs.I2CCLKL = 8U; // 400kHz
|
||||
I2caRegs.I2CCLKH = 7U; // 400kHz
|
||||
|
||||
/*
|
||||
* 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA)
|
||||
*/
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */
|
||||
EDIS;
|
||||
|
||||
/* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */
|
||||
I2caRegs.I2CMDR.all = 0x0020U;
|
||||
}
|
||||
|
||||
static void CShutdownProcedure(void)
|
||||
{
|
||||
if (KeyOperValue.KeyList.MainPower == 1U)
|
||||
{
|
||||
// 장치의 전원을 끄기 전 모든 제어상태를 정지 한다.
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY);
|
||||
COffChipSelect();
|
||||
|
||||
if (GeneralOperValue.uiWriteEepromDataStart == 0U)
|
||||
{
|
||||
GeneralOperValue.uiWriteEepromDataStart = 1U;
|
||||
}
|
||||
|
||||
// 최대 3초 경과 후 꺼짐
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond)
|
||||
{
|
||||
Uint32 ulMask;
|
||||
|
||||
if (pData != NULL)
|
||||
{
|
||||
ulMask = 1UL << (Uint32)uiIdx;
|
||||
*pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask);
|
||||
}
|
||||
}
|
||||
|
||||
Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx)
|
||||
{
|
||||
Uint32 ulMask;
|
||||
|
||||
ulMask = 1UL << (Uint32)uiIdx;
|
||||
|
||||
return (((ulData & ulMask) != 0UL) ? 1U : 0U);
|
||||
}
|
||||
|
||||
void DELAY_USEC(Uint32 ulMicroSeconds)
|
||||
{
|
||||
Uint32 ulDelayCount;
|
||||
|
||||
ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L));
|
||||
|
||||
DSP28x_usDelay(ulDelayCount);
|
||||
}
|
||||
|
||||
void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState)
|
||||
{
|
||||
switch (eIdx)
|
||||
{
|
||||
case IDX_CS_ENG_HEATER:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_GLOW_PLUG:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; }
|
||||
else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_SOLENOID:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_FUEL_PUMP:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; }
|
||||
else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_COOLANT_PUMP:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_FAN1:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; }
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
if (eIdx == IDX_CS_FAN2)
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; }
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,696 @@
|
||||
#ifndef SOURCE_COMM_H_
|
||||
#define SOURCE_COMM_H_
|
||||
|
||||
typedef struct ClassCommCheck
|
||||
{
|
||||
Uint16 CarComputer;
|
||||
Uint16 Gcu;
|
||||
Uint16 Ecu;
|
||||
} CCommCheck;
|
||||
|
||||
typedef struct ClassTx100
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Heartbit;
|
||||
|
||||
/* BYTE 2~4 Reserved */
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 VersionPatch;
|
||||
} CTx100;
|
||||
|
||||
typedef struct ClassTx101
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PlayState; // 0~3 bit
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe
|
||||
|
||||
/* BYTE 2~7 Reserved */
|
||||
|
||||
} CTx101;
|
||||
|
||||
typedef struct ClassTx102
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency
|
||||
|
||||
/* BYTE 1~7 Reserved */
|
||||
|
||||
} CTx102;
|
||||
|
||||
|
||||
typedef struct ClassTx103
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 EngineStart;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 EngineStop;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 FaultReset;
|
||||
|
||||
/* BYTE 3 Reserved */
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 RpmSetpoint;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 ActiveOverride;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 EmergencyStop;
|
||||
|
||||
} CTx103;
|
||||
|
||||
typedef struct ClassTx110
|
||||
{
|
||||
/* BYTE 0~3 */
|
||||
Uint16 DcuFaultB0;
|
||||
Uint16 DcuFaultB1;
|
||||
Uint16 DcuFaultB2;
|
||||
Uint16 DcuFaultB3;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx110;
|
||||
|
||||
typedef struct ClassTx120
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CTx120;
|
||||
|
||||
typedef struct ClassTx121
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 EngHeatVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 EngHeatCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 GlowPlugVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 GlowPlugCurrent;
|
||||
} CTx121;
|
||||
|
||||
typedef struct ClassTx122
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 SolenoidVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SolenoidCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 FuelPumpVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 FuelPumpCurrent;
|
||||
} CTx122;
|
||||
|
||||
typedef struct ClassTx123
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 CoolantPumpVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 CoolantPumpCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Fan1Voltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Fan1Current;
|
||||
} CTx123;
|
||||
|
||||
typedef struct ClassTx124
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Fan2Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Fan2Current;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx124;
|
||||
|
||||
typedef struct ClassRx200
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 HeartBit;
|
||||
|
||||
/* BYTE 2~4 - Reserved */
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 VersionPatch;
|
||||
} CRx200;
|
||||
|
||||
typedef struct ClassRx201
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PlayState; // 0:3 bit PlayState
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 State; // bit 0:AlarmOccured, 1:Shutdown
|
||||
|
||||
/* BYTE 2~7 - Reserved */
|
||||
|
||||
} CRx201;
|
||||
|
||||
typedef struct ClassRx210
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:PcbOverHeat
|
||||
* 1:FetOverHeat
|
||||
* 2:GenOverHeat1
|
||||
* 3:GenOverHeat2
|
||||
*/
|
||||
Uint16 GcuWarning;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:HwTrip
|
||||
* 1:HwIgbt
|
||||
* 2:HwDc
|
||||
* 3:GenOverCurrentU
|
||||
* 4:GenOverCurrentV
|
||||
* 5:GenOverCurrentW
|
||||
* 6:DcOverVoltage
|
||||
* 7:DcOverCurrent
|
||||
*
|
||||
* 8:CrankningOverCurrent
|
||||
* 9:PcbOverHeat
|
||||
* 10:FetOverHeat
|
||||
* 11:GenTempOverHeat1
|
||||
* 12:GenTempOverHeat2
|
||||
* 13:GenOverSpeed
|
||||
* 14:ResolverIC
|
||||
* 15:ResolverParity
|
||||
*/
|
||||
Uint16 GcuFault;
|
||||
|
||||
/* BYTE 4~7 - Reserved*/
|
||||
|
||||
} CRx210;
|
||||
|
||||
typedef struct ClassRx220
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 DcVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 DcCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Rpm;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Power;
|
||||
} CRx220;
|
||||
|
||||
typedef struct ClassRx221
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PcbTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 FetTemperature;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 GenTemperature1;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 GenTemperature2;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CRx221;
|
||||
|
||||
typedef struct ClassRx300
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 VersionPatch;
|
||||
|
||||
/* BYTE 3~7 - Reserved */
|
||||
|
||||
} CRx300;
|
||||
|
||||
typedef struct ClassRx301
|
||||
{
|
||||
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:AlarmOccured
|
||||
* 1~3:PlayState
|
||||
* 4:OverrideActive
|
||||
* 5:GlowPlugActive
|
||||
* 6:HeaterActive
|
||||
* 7:OilPressureMissing
|
||||
*/
|
||||
Uint16 State;
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CRx301;
|
||||
|
||||
typedef struct ClassRx310
|
||||
{
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineOverHeat
|
||||
* 1:Reserved
|
||||
* 2:LoOilPressure
|
||||
* 3:IntakeOverHeat
|
||||
* 4:IntakeLoPressure
|
||||
* 5:EngineLoTemperature
|
||||
* 6:EngineSensor
|
||||
* 7:DefaltValueActive
|
||||
*/
|
||||
Uint16 EcuWarning;
|
||||
|
||||
/* BYTE 1 - Reserved */
|
||||
|
||||
/* BYTE 2 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:OilPressureMissing
|
||||
* 1:IntakeOverHeat
|
||||
* 2:EngineOverHeat
|
||||
* 3:Actuator
|
||||
* 4:RpmSignal
|
||||
* 5:EngineStartFail
|
||||
* 6:Reserved
|
||||
* 7:Reserved
|
||||
*/
|
||||
Uint16 EcuFault;
|
||||
|
||||
/* BYTE 3~7 - Reserved */
|
||||
|
||||
} CRx310;
|
||||
|
||||
typedef struct ClassRx320
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 ActualRpm;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SetRpm;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 ActualTorque;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 SetTorque;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 SystemVoltage;
|
||||
} CRx320;
|
||||
|
||||
typedef struct ClassRx321
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 CoolantTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 Fan1Speed;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Fan2Speed;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 CoolantPumpSpeed;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 BarometricPressure;
|
||||
|
||||
/* BYTE 6~7 - Reserved */
|
||||
|
||||
} CRx321;
|
||||
|
||||
typedef struct ClassRx322
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 TotalOperTimeL : 16;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 TotalOperTimeH : 16;
|
||||
|
||||
/* BYTE 4~7 - Reserved*/
|
||||
|
||||
} CRx322;
|
||||
|
||||
typedef struct ClassTx700
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 HeartBit;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 DCUversionMajor;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 DCUversionMinor;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 GCUversionMajor;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 GCUversionMinor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 ECUversionMajor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 ECUversionMinor;
|
||||
} CTx700;
|
||||
|
||||
typedef struct ClassTx701
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 DcuPlayState; // bit 0~3:PlayState
|
||||
|
||||
/* BYTE 1 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:DcuAlarmOccured
|
||||
* 1:DcuEmergencyStop
|
||||
* 2:PowerSwitchPush
|
||||
* 3:EcuFailSafe
|
||||
*/
|
||||
Uint16 DcuState;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 GcuPlayState; // bit 0~2:GcuPlayState
|
||||
|
||||
/* BYTE 3 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:GcuAlarmOccured
|
||||
* 1:GcuShutdown
|
||||
*/
|
||||
Uint16 GcuState;
|
||||
|
||||
/* BYTE 4 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EcuAlarmOccured
|
||||
* 1~3:EcuPlayState
|
||||
* 4:ActiveOverride
|
||||
* 5:ActiveGlowPlug
|
||||
* 6:ActiveEngHeater
|
||||
* 7:OilPressureMissing
|
||||
*/
|
||||
Uint16 EcuState;
|
||||
|
||||
/* BYTE 5~7 - Reserved */
|
||||
|
||||
} CTx701;
|
||||
|
||||
typedef struct ClassTx710
|
||||
{
|
||||
/* BYTE 0 - GCU Warning */
|
||||
/*
|
||||
* bit description
|
||||
* 0:PcbOverHeat
|
||||
* 1:FetOverHeat
|
||||
* 2:Winding1OverHeat
|
||||
* 3:Winding2OverHeat
|
||||
*/
|
||||
Uint16 GcuWarning;
|
||||
|
||||
/* BYTE 1 - ECU Warning */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineOverHeat
|
||||
* 1:Reserved
|
||||
* 2:LoOilPressure
|
||||
* 3:IntakeOverHeat
|
||||
* 4:IntakeLoPressure
|
||||
* 5:EngineLoTemperature
|
||||
* 6:EngineSensorFault
|
||||
* 7:DefaultValueActive
|
||||
*/
|
||||
Uint16 EcuWarning;
|
||||
|
||||
/* BYTE 2~7 - Reserved */
|
||||
|
||||
} CTx710;
|
||||
|
||||
typedef struct ClassTx720
|
||||
{
|
||||
/* BYTE 0~3 - DCU Fault */
|
||||
Uint16 DcuFault0;
|
||||
Uint16 DcuFault1;
|
||||
Uint16 DcuFault2;
|
||||
Uint16 DcuFault3;
|
||||
|
||||
/* BYTE 4~5 - GCU Fault */
|
||||
Uint16 GcuFault0;
|
||||
Uint16 GcuFault1;
|
||||
|
||||
/* BYTE 6 - Reserved */
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 EcuFault;
|
||||
} CTx720;
|
||||
|
||||
typedef struct ClassTx730
|
||||
{
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineHeater
|
||||
* 1:GlowPlug
|
||||
* 2:Solenoid
|
||||
* 3:FuelPump
|
||||
* 4:CoolantPump
|
||||
* 5:Fan1
|
||||
* 6:Fan2
|
||||
* 7:Reserved
|
||||
*/
|
||||
Uint16 AuxState;
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CTx730;
|
||||
|
||||
typedef struct ClassTx731
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 EngineHeaterVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 EngineHeaterCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 GlowPlugVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 GlowPlugCurrent;
|
||||
} CTx731;
|
||||
|
||||
typedef struct ClassTx732
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 SolenoidVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SolenoidCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 FuelPumpVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 FuelPumpCurrent;
|
||||
} CTx732;
|
||||
|
||||
typedef struct ClassTx733
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 CoolantPumpVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 CoolantPumpCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Fan1Voltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Fan1Current;
|
||||
} CTx733;
|
||||
|
||||
typedef struct ClassTx734
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Fan2Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Fan2Current;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx734;
|
||||
|
||||
typedef struct ClassTx740
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Current;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Rpm;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Power;
|
||||
} CTx740;
|
||||
|
||||
typedef struct ClassTx741
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PcbTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 FetTemperature;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Winding1Temperature;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 Winding2Temperature;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx741;
|
||||
|
||||
typedef struct ClassTx750
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 ActualRpm;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SetRpm;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 ActualTorque;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 SetTorque;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 SystemVoltage;
|
||||
} CTx750;
|
||||
|
||||
typedef struct ClassTx751
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 CoolantTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 Fan1Speed;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Fan2Speed;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 CoolantPumpSpeed;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Barometric;
|
||||
|
||||
/* BYTE 6~7 - Reserved */
|
||||
|
||||
} CTx751;
|
||||
|
||||
typedef struct ClassTx752
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 OperationTimeL;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 OperationTimeH;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx752;
|
||||
|
||||
interrupt void CECanInterruptA(void);
|
||||
interrupt void CECanInterruptB(void);
|
||||
void CSendECanDataA(void);
|
||||
void CSendECanDataB(void);
|
||||
void CInitEcan(void);
|
||||
|
||||
extern CCommCheck CommCheck;
|
||||
extern CRx200 Rx200;
|
||||
extern CRx210 Rx210;
|
||||
extern CRx220 Rx220;
|
||||
extern CRx221 Rx221;
|
||||
extern CRx300 Rx300;
|
||||
extern CRx301 Rx301;
|
||||
extern CRx310 Rx310;
|
||||
extern CRx320 Rx320;
|
||||
extern CRx321 Rx321;
|
||||
extern CRx322 Rx322;
|
||||
|
||||
typedef struct ClassRx400
|
||||
{
|
||||
struct
|
||||
{
|
||||
Uint16 BYTE0 : 8;
|
||||
Uint16 BYTE1 : 8;
|
||||
Uint16 BYTE2 : 8;
|
||||
Uint16 BYTE3 : 8;
|
||||
Uint16 BYTE4 : 8;
|
||||
Uint16 BYTE5 : 8;
|
||||
Uint16 BYTE6 : 8;
|
||||
Uint16 BYTE7 : 8;
|
||||
} Bytes;
|
||||
struct
|
||||
{
|
||||
Uint16 EngineHeater : 1;
|
||||
Uint16 GlowPlug : 1;
|
||||
Uint16 Solenoid : 1;
|
||||
Uint16 FuelPump : 1;
|
||||
Uint16 CoolantPump : 1;
|
||||
Uint16 Fan1 : 1;
|
||||
Uint16 Fan2 : 1;
|
||||
Uint16 AuxTestStart : 1;
|
||||
Uint16 rsvd_padding : 8;
|
||||
} AuxControl;
|
||||
} CRx400;
|
||||
|
||||
extern CRx400 Rx400;
|
||||
|
||||
#endif /* SOURCE_COMM_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,195 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:24 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieCtrl.h
|
||||
//
|
||||
// TITLE: DSP2833x Device PIE Control Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_PIE_CTRL_H
|
||||
#define DSP2833x_PIE_CTRL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// PIE Control Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// PIECTRL: Register bit definitions
|
||||
//
|
||||
struct PIECTRL_BITS { // bits description
|
||||
Uint16 ENPIE:1; // 0 Enable PIE block
|
||||
Uint16 PIEVECT:15; // 15:1 Fetched vector address
|
||||
};
|
||||
|
||||
union PIECTRL_REG {
|
||||
Uint16 all;
|
||||
struct PIECTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEIER: Register bit definitions
|
||||
//
|
||||
struct PIEIER_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 INTx.1
|
||||
Uint16 INTx2:1; // 1 INTx.2
|
||||
Uint16 INTx3:1; // 2 INTx.3
|
||||
Uint16 INTx4:1; // 3 INTx.4
|
||||
Uint16 INTx5:1; // 4 INTx.5
|
||||
Uint16 INTx6:1; // 5 INTx.6
|
||||
Uint16 INTx7:1; // 6 INTx.7
|
||||
Uint16 INTx8:1; // 7 INTx.8
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union PIEIER_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEIFR: Register bit definitions
|
||||
//
|
||||
struct PIEIFR_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 INTx.1
|
||||
Uint16 INTx2:1; // 1 INTx.2
|
||||
Uint16 INTx3:1; // 2 INTx.3
|
||||
Uint16 INTx4:1; // 3 INTx.4
|
||||
Uint16 INTx5:1; // 4 INTx.5
|
||||
Uint16 INTx6:1; // 5 INTx.6
|
||||
Uint16 INTx7:1; // 6 INTx.7
|
||||
Uint16 INTx8:1; // 7 INTx.8
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union PIEIFR_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEACK: Register bit definitions
|
||||
//
|
||||
struct PIEACK_BITS { // bits description
|
||||
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
|
||||
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
|
||||
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
|
||||
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
|
||||
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
|
||||
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
|
||||
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
|
||||
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
|
||||
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
|
||||
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
|
||||
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
|
||||
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
|
||||
Uint16 rsvd:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union PIEACK_REG {
|
||||
Uint16 all;
|
||||
struct PIEACK_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIE Control Register File
|
||||
//
|
||||
struct PIE_CTRL_REGS {
|
||||
union PIECTRL_REG PIECTRL; // PIE control register
|
||||
union PIEACK_REG PIEACK; // PIE acknowledge
|
||||
union PIEIER_REG PIEIER1; // PIE int1 IER register
|
||||
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
|
||||
union PIEIER_REG PIEIER2; // PIE INT2 IER register
|
||||
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
|
||||
union PIEIER_REG PIEIER3; // PIE INT3 IER register
|
||||
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
|
||||
union PIEIER_REG PIEIER4; // PIE INT4 IER register
|
||||
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
|
||||
union PIEIER_REG PIEIER5; // PIE INT5 IER register
|
||||
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
|
||||
union PIEIER_REG PIEIER6; // PIE INT6 IER register
|
||||
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
|
||||
union PIEIER_REG PIEIER7; // PIE INT7 IER register
|
||||
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
|
||||
union PIEIER_REG PIEIER8; // PIE INT8 IER register
|
||||
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
|
||||
union PIEIER_REG PIEIER9; // PIE INT9 IER register
|
||||
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
|
||||
union PIEIER_REG PIEIER10; // PIE int10 IER register
|
||||
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
|
||||
union PIEIER_REG PIEIER11; // PIE int11 IER register
|
||||
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
|
||||
union PIEIER_REG PIEIER12; // PIE int12 IER register
|
||||
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
|
||||
};
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define PIEACK_GROUP1 0x0001
|
||||
#define PIEACK_GROUP2 0x0002
|
||||
#define PIEACK_GROUP3 0x0004
|
||||
#define PIEACK_GROUP4 0x0008
|
||||
#define PIEACK_GROUP5 0x0010
|
||||
#define PIEACK_GROUP6 0x0020
|
||||
#define PIEACK_GROUP7 0x0040
|
||||
#define PIEACK_GROUP8 0x0080
|
||||
#define PIEACK_GROUP9 0x0100
|
||||
#define PIEACK_GROUP10 0x0200
|
||||
#define PIEACK_GROUP11 0x0400
|
||||
#define PIEACK_GROUP12 0x0800
|
||||
|
||||
//
|
||||
// PIE Control Registers External References & Function Declarations
|
||||
//
|
||||
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_PIE_CTRL_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,255 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: March 20, 2007 15:33:42 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_CpuTimers.h
|
||||
//
|
||||
// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
|
||||
//
|
||||
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
|
||||
// other realtime operating systems.
|
||||
//
|
||||
// Do not use these two timers in your application if you ever plan
|
||||
// on integrating DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// For this reason, comment out the code to manipulate these two
|
||||
// timers if using DSP-BIOS or another realtime OS.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_CPU_TIMERS_H
|
||||
#define DSP2833x_CPU_TIMERS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// CPU Timer Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// TCR: Control register bit definitions
|
||||
//
|
||||
struct TCR_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 TSS:1; // 4 Timer Start/Stop
|
||||
Uint16 TRB:1; // 5 Timer reload
|
||||
Uint16 rsvd2:4; // 9:6 reserved
|
||||
Uint16 SOFT:1; // 10 Emulation modes
|
||||
Uint16 FREE:1; // 11
|
||||
Uint16 rsvd3:2; // 12:13 reserved
|
||||
Uint16 TIE:1; // 14 Output enable
|
||||
Uint16 TIF:1; // 15 Interrupt flag
|
||||
};
|
||||
|
||||
union TCR_REG {
|
||||
Uint16 all;
|
||||
struct TCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TPR: Pre-scale low bit definitions
|
||||
//
|
||||
struct TPR_BITS { // bits description
|
||||
Uint16 TDDR:8; // 7:0 Divide-down low
|
||||
Uint16 PSC:8; // 15:8 Prescale counter low
|
||||
};
|
||||
|
||||
union TPR_REG {
|
||||
Uint16 all;
|
||||
struct TPR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TPRH: Pre-scale high bit definitions
|
||||
//
|
||||
struct TPRH_BITS { // bits description
|
||||
Uint16 TDDRH:8; // 7:0 Divide-down high
|
||||
Uint16 PSCH:8; // 15:8 Prescale counter high
|
||||
};
|
||||
|
||||
union TPRH_REG {
|
||||
Uint16 all;
|
||||
struct TPRH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TIM, TIMH: Timer register definitions
|
||||
//
|
||||
struct TIM_REG {
|
||||
Uint16 LSW;
|
||||
Uint16 MSW;
|
||||
};
|
||||
|
||||
union TIM_GROUP {
|
||||
Uint32 all;
|
||||
struct TIM_REG half;
|
||||
};
|
||||
|
||||
//
|
||||
// PRD, PRDH: Period register definitions
|
||||
//
|
||||
struct PRD_REG {
|
||||
Uint16 LSW;
|
||||
Uint16 MSW;
|
||||
};
|
||||
|
||||
union PRD_GROUP {
|
||||
Uint32 all;
|
||||
struct PRD_REG half;
|
||||
};
|
||||
|
||||
//
|
||||
// CPU Timer Register File
|
||||
//
|
||||
struct CPUTIMER_REGS {
|
||||
union TIM_GROUP TIM; // Timer counter register
|
||||
union PRD_GROUP PRD; // Period register
|
||||
union TCR_REG TCR; // Timer control register
|
||||
Uint16 rsvd1; // reserved
|
||||
union TPR_REG TPR; // Timer pre-scale low
|
||||
union TPRH_REG TPRH; // Timer pre-scale high
|
||||
};
|
||||
|
||||
//
|
||||
// CPU Timer Support Variables
|
||||
//
|
||||
struct CPUTIMER_VARS {
|
||||
volatile struct CPUTIMER_REGS *RegsAddr;
|
||||
Uint32 InterruptCount;
|
||||
float CPUFreqInMHz;
|
||||
float PeriodInUSec;
|
||||
};
|
||||
|
||||
//
|
||||
// Function prototypes and external definitions
|
||||
//
|
||||
void InitCpuTimers(void);
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
|
||||
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
extern struct CPUTIMER_VARS CpuTimer0;
|
||||
|
||||
//
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS.
|
||||
// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
|
||||
//
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
|
||||
extern struct CPUTIMER_VARS CpuTimer1;
|
||||
extern struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//
|
||||
// Defines for useful Timer Operations:
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer
|
||||
//
|
||||
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer
|
||||
//
|
||||
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value
|
||||
//
|
||||
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value
|
||||
//
|
||||
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value
|
||||
//
|
||||
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
|
||||
|
||||
//
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
|
||||
// Do not use these two timers if you ever plan on integrating
|
||||
// DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// For this reason, comment out the code to manipulate these two timers
|
||||
// if using DSP-BIOS or another realtime OS.
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer
|
||||
//
|
||||
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
|
||||
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer
|
||||
//
|
||||
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
|
||||
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value
|
||||
//
|
||||
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
|
||||
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value
|
||||
//
|
||||
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
|
||||
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value
|
||||
//
|
||||
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
|
||||
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_CPU_TIMERS_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,251 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 1, 2007 15:57:02 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Sci.h
|
||||
//
|
||||
// TITLE: DSP2833x Device SCI Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SCI_H
|
||||
#define DSP2833x_SCI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// SCI Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// SCICCR communication control register bit definitions
|
||||
//
|
||||
struct SCICCR_BITS { // bit description
|
||||
Uint16 SCICHAR:3; // 2:0 Character length control
|
||||
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
|
||||
Uint16 LOOPBKENA:1; // 4 Loop Back enable
|
||||
Uint16 PARITYENA:1; // 5 Parity enable
|
||||
Uint16 PARITY:1; // 6 Even or Odd Parity
|
||||
Uint16 STOPBITS:1; // 7 Number of Stop Bits
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SCICCR_REG {
|
||||
Uint16 all;
|
||||
struct SCICCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCICTL1 control register 1 bit definitions
|
||||
//
|
||||
struct SCICTL1_BITS { // bit description
|
||||
Uint16 RXENA:1; // 0 SCI receiver enable
|
||||
Uint16 TXENA:1; // 1 SCI transmitter enable
|
||||
Uint16 SLEEP:1; // 2 SCI sleep
|
||||
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
|
||||
Uint16 rsvd:1; // 4 reserved
|
||||
Uint16 SWRESET:1; // 5 Software reset
|
||||
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
|
||||
Uint16 rsvd1:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union SCICTL1_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCICTL2 control register 2 bit definitions
|
||||
//
|
||||
struct SCICTL2_BITS { // bit description
|
||||
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
|
||||
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
|
||||
Uint16 rsvd:4; // 5:2 reserved
|
||||
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
|
||||
Uint16 TXRDY:1; // 7 Transmitter ready flag
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SCICTL2_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIRXST Receiver status register bit definitions
|
||||
//
|
||||
struct SCIRXST_BITS { // bit description
|
||||
Uint16 rsvd:1; // 0 reserved
|
||||
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
|
||||
Uint16 PE:1; // 2 Parity error flag
|
||||
Uint16 OE:1; // 3 Overrun error flag
|
||||
Uint16 FE:1; // 4 Framing error flag
|
||||
Uint16 BRKDT:1; // 5 Break-detect flag
|
||||
Uint16 RXRDY:1; // 6 Receiver ready flag
|
||||
Uint16 RXERROR:1; // 7 Receiver error flag
|
||||
};
|
||||
|
||||
union SCIRXST_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXST_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions
|
||||
//
|
||||
struct SCIRXBUF_BITS { // bits description
|
||||
Uint16 RXDT:8; // 7:0 Receive word
|
||||
Uint16 rsvd:6; // 13:8 reserved
|
||||
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
|
||||
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
|
||||
};
|
||||
|
||||
union SCIRXBUF_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXBUF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIPRI Priority control register bit definitions
|
||||
//
|
||||
struct SCIPRI_BITS { // bit description
|
||||
Uint16 rsvd:3; // 2:0 reserved
|
||||
Uint16 FREE:1; // 3 Free emulation suspend mode
|
||||
Uint16 SOFT:1; // 4 Soft emulation suspend mode
|
||||
Uint16 rsvd1:3; // 7:5 reserved
|
||||
};
|
||||
|
||||
union SCIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SCIPRI_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO Transmit register bit definitions
|
||||
//
|
||||
struct SCIFFTX_BITS { // bit description
|
||||
Uint16 TXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 TXFFINT:1; // 7 INT flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO status
|
||||
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
|
||||
Uint16 SCIFFENA:1; // 14 Enhancement enable
|
||||
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
|
||||
};
|
||||
|
||||
union SCIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO recieve register bit definitions
|
||||
//
|
||||
struct SCIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 RXFFINT:1; // 7 INT flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO status
|
||||
Uint16 RXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
|
||||
Uint16 RXFFOVF:1; // 15 FIFO overflow
|
||||
};
|
||||
|
||||
union SCIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO control register bit definitions
|
||||
//
|
||||
struct SCIFFCT_BITS { // bits description
|
||||
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
|
||||
Uint16 rsvd:5; // 12:8 reserved
|
||||
Uint16 CDC:1; // 13 Auto baud mode enable
|
||||
Uint16 ABDCLR:1; // 14 Auto baud clear
|
||||
Uint16 ABD:1; // 15 Auto baud detect
|
||||
};
|
||||
|
||||
union SCIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI Register File
|
||||
//
|
||||
struct SCI_REGS {
|
||||
union SCICCR_REG SCICCR; // Communications control register
|
||||
union SCICTL1_REG SCICTL1; // Control register 1
|
||||
Uint16 SCIHBAUD; // Baud rate (high) register
|
||||
Uint16 SCILBAUD; // Baud rate (low) register
|
||||
union SCICTL2_REG SCICTL2; // Control register 2
|
||||
union SCIRXST_REG SCIRXST; // Recieve status register
|
||||
Uint16 SCIRXEMU; // Recieve emulation buffer register
|
||||
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 SCITXBUF; // Transmit data buffer
|
||||
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
|
||||
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
|
||||
union SCIFFCT_REG SCIFFCT; // FIFO control register
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 rsvd3; // reserved
|
||||
union SCIPRI_REG SCIPRI; // FIFO Priority control
|
||||
};
|
||||
|
||||
//
|
||||
// SCI External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SCI_REGS SciaRegs;
|
||||
extern volatile struct SCI_REGS ScibRegs;
|
||||
extern volatile struct SCI_REGS ScicRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SCI_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,586 @@
|
||||
/* ========================================================================= */
|
||||
/* 1. Includes */
|
||||
/* ========================================================================= */
|
||||
#include "main.h"
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */
|
||||
/* ========================================================================= */
|
||||
#define ENGINE_MAXIMUM_SPEED (2800U)
|
||||
#define ENGINE_OPERATION_SPEED (2400U)
|
||||
#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400
|
||||
|
||||
#define LED_OFF (0U)
|
||||
#define LED_ON (1U)
|
||||
#define LED_BLINK (2U)
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */
|
||||
/* ========================================================================= */
|
||||
static void CInitialStandby(void);
|
||||
static void CEmergencyStop(void);
|
||||
static void CProcessApuStateReady(void);
|
||||
static void CProcessApuStatePreheat(void);
|
||||
static void CProcessApuStateCranking(void);
|
||||
static void CProcessApuStateRetryCranking(void);
|
||||
static void CProcessApuStateEngineIdle(void);
|
||||
static void CProcessApuStateGenerating(void);
|
||||
static void CProcessApuStateCooldown(void);
|
||||
static void CProcessApuStateStopping(void);
|
||||
static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용
|
||||
static void CSetEngineActualRpm(Uint16 Rpm);
|
||||
static float32 CGetGcuLoadPower(void);
|
||||
static Uint16 CDynamicRpmControl(void);
|
||||
static void CLedControl(Uint16 idx, Uint16 state);
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* Function Definitions */
|
||||
/* ========================================================================= */
|
||||
static void CProcessApuStateReady(void)
|
||||
{
|
||||
// 냉각수 펌프 및 냉각팬 시작
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, 1U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, 1U);
|
||||
|
||||
// ECU 동작 명령 송신, 2400 RPM 설정
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_START);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT;
|
||||
}
|
||||
|
||||
static void CProcessApuStatePreheat(void)
|
||||
{
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING;
|
||||
}
|
||||
else
|
||||
{
|
||||
// PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
// 알람처리를 할지 무기한 대기 할 지 검토 필요
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateCranking(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING);
|
||||
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE;
|
||||
GeneralOperValue.uiRetryCrankingCount = 0U;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
}
|
||||
else
|
||||
{
|
||||
// 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateRetryCranking(void)
|
||||
{
|
||||
if (GeneralOperValue.uiRetryCrankingCount < 3U)
|
||||
{
|
||||
// 5초 대기 후 재시도
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GeneralOperValue.uiRetryCrankingCount++;
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL);
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateEngineIdle(void)
|
||||
{
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION)
|
||||
{
|
||||
// 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환
|
||||
if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM
|
||||
{
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateGenerating(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신
|
||||
GeneralOperValue.uiDynamicRPM = CDynamicRpmControl();
|
||||
CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작
|
||||
}
|
||||
|
||||
static void CProcessApuStateCooldown(void)
|
||||
{
|
||||
Uint16 IsRpmZero;
|
||||
Uint16 IsTimeout;
|
||||
|
||||
// 쿨다운: 발전 중지 -> 엔진 IDLE로 변경
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP);
|
||||
|
||||
IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U;
|
||||
IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U;
|
||||
|
||||
if ((IsRpmZero == 1U) || (IsTimeout == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING;
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateStopping(void)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING)
|
||||
{
|
||||
CInitialStandby();
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateTransition(void)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
CInitialStandby();
|
||||
}
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY)
|
||||
{
|
||||
if (KeyOperValue.KeyList.EngineStartStop == 1U)
|
||||
{
|
||||
GeneralOperValue.uiRetryCrankingCount = 0U;
|
||||
if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U;
|
||||
CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING))
|
||||
{
|
||||
if (KeyOperValue.KeyList.EngineStartStop == 0U)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN;
|
||||
}
|
||||
else
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CApuOperProcedure(void)
|
||||
{
|
||||
// 입력 신호 Lo Active
|
||||
Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U;
|
||||
|
||||
// 비상 상황 체크
|
||||
if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY;
|
||||
CEmergencyStop();
|
||||
}
|
||||
else
|
||||
{
|
||||
// 외부 조작에 의한 상태 변경 확인
|
||||
CProcessApuStateTransition();
|
||||
|
||||
// ECU Aux Bypass 제어
|
||||
if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig);
|
||||
}
|
||||
|
||||
// 각 상태별 동작 수행
|
||||
switch (GeneralOperValue.uiApuState)
|
||||
{
|
||||
case (Uint16)IDX_APU_OPER_READY:
|
||||
{
|
||||
CProcessApuStateReady();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_PREHEAT:
|
||||
{
|
||||
CProcessApuStatePreheat();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_CRANKING:
|
||||
{
|
||||
CProcessApuStateCranking();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_RETRY_CRANKING:
|
||||
{
|
||||
CProcessApuStateRetryCranking();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_ENGINE_IDLE:
|
||||
{
|
||||
CProcessApuStateEngineIdle();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_GENERATING:
|
||||
{
|
||||
CProcessApuStateGenerating();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_COOLDOWN:
|
||||
{
|
||||
CProcessApuStateCooldown();
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
CProcessApuStateStopping();
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static Uint16 CDynamicRpmControl(void)
|
||||
{
|
||||
float32 TargetRPM;
|
||||
Uint16 ReturnRpm;
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
// 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산
|
||||
TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw
|
||||
|
||||
ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림
|
||||
}
|
||||
else
|
||||
{
|
||||
// 발전 상태가 아닐 때는 기본 2400 RPM 반환
|
||||
ReturnRpm = ENGINE_OPERATION_SPEED;
|
||||
}
|
||||
|
||||
ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED;
|
||||
|
||||
return ReturnRpm;
|
||||
}
|
||||
|
||||
static void CInitialStandby(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP);
|
||||
|
||||
COffChipSelect();
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN);
|
||||
|
||||
GeneralOperValue.uiEmergency = 0U;
|
||||
|
||||
GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD
|
||||
}
|
||||
|
||||
static void CEmergencyStop(void)
|
||||
{
|
||||
KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화
|
||||
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY);
|
||||
|
||||
COffChipSelect();
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN);
|
||||
|
||||
GeneralOperValue.uiEmergency = 1U;
|
||||
|
||||
GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD
|
||||
}
|
||||
|
||||
static void CSetEngineActualRpm(Uint16 Rpm)
|
||||
{
|
||||
GeneralOperValue.EcuCommand.RpmSetPoint = Rpm;
|
||||
}
|
||||
|
||||
Uint16 CGetEngineActualRpm(void)
|
||||
{
|
||||
return (Uint16)Rx320.ActualRpm;
|
||||
}
|
||||
|
||||
static float32 CGetGcuLoadPower(void)
|
||||
{
|
||||
float32 power = ((float32)Rx220.Power * 0.1F);
|
||||
|
||||
// 범위를 0.0 ~ 17.0 으로 제한
|
||||
if (power > 17.0F)
|
||||
{
|
||||
power = 17.0F;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (power < 0.0F)
|
||||
{
|
||||
power = 0.0;
|
||||
}
|
||||
}
|
||||
return power;
|
||||
}
|
||||
|
||||
Uint16 CGetGeneratorRpm(void)
|
||||
{
|
||||
return Rx220.Rpm;
|
||||
}
|
||||
|
||||
void CSetGcuCommand(Uint16 Command)
|
||||
{
|
||||
GeneralOperValue.GcuCommand.PlayCmd = Command;
|
||||
}
|
||||
|
||||
void CSetEcuCommand(Uint16 Command)
|
||||
{
|
||||
if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY))
|
||||
{
|
||||
GeneralOperValue.EcuCommand.EngineStart = 0U;
|
||||
GeneralOperValue.EcuCommand.EngineStop = 1U;
|
||||
CSetEngineActualRpm(0U);
|
||||
}
|
||||
else
|
||||
{
|
||||
// [ECU_OPER_CMD_START]
|
||||
GeneralOperValue.EcuCommand.EngineStart = 1U;
|
||||
GeneralOperValue.EcuCommand.EngineStop = 0U;
|
||||
#if 0 // RPM 테스트
|
||||
CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM);
|
||||
#else
|
||||
CSetEngineActualRpm(2400U);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
int16 CGetEngCoolantTemperature(void)
|
||||
{
|
||||
return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도
|
||||
}
|
||||
|
||||
void CDebugModeProcedure(void)
|
||||
{
|
||||
if (GeneralOperValue.Maintenance.ManualCranking == 1U)
|
||||
{
|
||||
if (GeneralOperValue.uiFaultOccured == 0U)
|
||||
{
|
||||
// 알람이 없을 경우만 동작 하도록 함.
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
}
|
||||
|
||||
if (GeneralOperValue.Maintenance.LampTest == 1U)
|
||||
{
|
||||
CLedControl(0U, 1U);
|
||||
CLedControl(1U, 1U);
|
||||
CLedControl(2U, 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(0U, 0U);
|
||||
CLedControl(1U, 0U);
|
||||
CLedControl(2U, 0U);
|
||||
}
|
||||
|
||||
if (GeneralOperValue.Maintenance.KeyTest == 1U)
|
||||
{
|
||||
Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U;
|
||||
Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U;
|
||||
|
||||
if ((uiKeyUp == 1U) && (uiKeyDn == 1U))
|
||||
{
|
||||
GeneralOperValue.Maintenance.KeyTest = 0U;
|
||||
OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CLedControlProcedure(void)
|
||||
{
|
||||
static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블
|
||||
{
|
||||
// FAULT, OPER, STOP
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 0: BOOT
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 2: POST
|
||||
{LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY
|
||||
|
||||
// --- OPER 깜빡임 구간 (준비~예열) ---
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 5: READY
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP
|
||||
|
||||
{LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전)
|
||||
|
||||
// --- STOP 깜빡임 구간 (APU 정지 시) ---
|
||||
{LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠)
|
||||
{LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정)
|
||||
};
|
||||
|
||||
CLedPattern TargetLeds = {0, 0, 0};
|
||||
|
||||
Uint64 SoftClock = CGetSoftClock();
|
||||
Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함
|
||||
Uint16 WarningValue = 0U;
|
||||
|
||||
TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState];
|
||||
|
||||
// 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U;
|
||||
}
|
||||
|
||||
// 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응
|
||||
if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U))
|
||||
{
|
||||
TargetLeds.Fault = (Uint16)LED_BLINK;
|
||||
}
|
||||
|
||||
// FAULT LED 제어
|
||||
if (TargetLeds.Fault == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(0U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(0U, TargetLeds.Fault);
|
||||
}
|
||||
|
||||
// OPERATION LED 제어
|
||||
if (TargetLeds.Operation == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(1U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(1U, TargetLeds.Operation);
|
||||
}
|
||||
|
||||
// STOP LED 제어
|
||||
if (TargetLeds.Stop == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(2U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(2U, TargetLeds.Stop);
|
||||
}
|
||||
}
|
||||
|
||||
static void CLedControl(Uint16 idx, Uint16 state)
|
||||
{
|
||||
/*
|
||||
* idx
|
||||
* 0 : FAULT LED
|
||||
* 1 : OPER LED
|
||||
* 2 : STOP LED
|
||||
*/
|
||||
|
||||
if (idx == 0U)
|
||||
{
|
||||
// GPIO_CPU_LED_FAULT
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO14 = 1U;
|
||||
}
|
||||
}
|
||||
else if (idx == 1U)
|
||||
{
|
||||
// GPIO_CPU_LED_OPERATION
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO13 = 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// GPIO_CPU_LED_STOP
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO12 = 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,206 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:45:37 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DefaultIsr.h
|
||||
//
|
||||
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEFAULT_ISR_H
|
||||
#define DSP2833x_DEFAULT_ISR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Default Interrupt Service Routine Declarations:
|
||||
//
|
||||
// The following function prototypes are for the
|
||||
// default ISR routines used with the default PIE vector table.
|
||||
// This default vector table is found in the DSP2833x_PieVect.h
|
||||
// file.
|
||||
//
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts
|
||||
//
|
||||
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
|
||||
interrupt void INT14_ISR(void); // CPU-Timer2
|
||||
interrupt void DATALOG_ISR(void); // Datalogging interrupt
|
||||
interrupt void RTOSINT_ISR(void); // RTOS interrupt
|
||||
interrupt void EMUINT_ISR(void); // Emulation interrupt
|
||||
interrupt void NMI_ISR(void); // Non-maskable interrupt
|
||||
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
|
||||
interrupt void USER1_ISR(void); // User Defined trap 1
|
||||
interrupt void USER2_ISR(void); // User Defined trap 2
|
||||
interrupt void USER3_ISR(void); // User Defined trap 3
|
||||
interrupt void USER4_ISR(void); // User Defined trap 4
|
||||
interrupt void USER5_ISR(void); // User Defined trap 5
|
||||
interrupt void USER6_ISR(void); // User Defined trap 6
|
||||
interrupt void USER7_ISR(void); // User Defined trap 7
|
||||
interrupt void USER8_ISR(void); // User Defined trap 8
|
||||
interrupt void USER9_ISR(void); // User Defined trap 9
|
||||
interrupt void USER10_ISR(void); // User Defined trap 10
|
||||
interrupt void USER11_ISR(void); // User Defined trap 11
|
||||
interrupt void USER12_ISR(void); // User Defined trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
|
||||
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
|
||||
interrupt void XINT1_ISR(void); // External interrupt 1
|
||||
interrupt void XINT2_ISR(void); // External interrupt 2
|
||||
interrupt void ADCINT_ISR(void); // ADC
|
||||
interrupt void TINT0_ISR(void); // Timer 0
|
||||
interrupt void WAKEINT_ISR(void); // WD
|
||||
|
||||
//
|
||||
// Group 2 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
|
||||
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
|
||||
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
|
||||
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
|
||||
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
|
||||
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
|
||||
|
||||
//
|
||||
// Group 3 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EPWM1_INT_ISR(void); // EPWM-1
|
||||
interrupt void EPWM2_INT_ISR(void); // EPWM-2
|
||||
interrupt void EPWM3_INT_ISR(void); // EPWM-3
|
||||
interrupt void EPWM4_INT_ISR(void); // EPWM-4
|
||||
interrupt void EPWM5_INT_ISR(void); // EPWM-5
|
||||
interrupt void EPWM6_INT_ISR(void); // EPWM-6
|
||||
|
||||
//
|
||||
// Group 4 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void ECAP1_INT_ISR(void); // ECAP-1
|
||||
interrupt void ECAP2_INT_ISR(void); // ECAP-2
|
||||
interrupt void ECAP3_INT_ISR(void); // ECAP-3
|
||||
interrupt void ECAP4_INT_ISR(void); // ECAP-4
|
||||
interrupt void ECAP5_INT_ISR(void); // ECAP-5
|
||||
interrupt void ECAP6_INT_ISR(void); // ECAP-6
|
||||
|
||||
//
|
||||
// Group 5 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EQEP1_INT_ISR(void); // EQEP-1
|
||||
interrupt void EQEP2_INT_ISR(void); // EQEP-2
|
||||
|
||||
//
|
||||
// Group 6 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SPIRXINTA_ISR(void); // SPI-A
|
||||
interrupt void SPITXINTA_ISR(void); // SPI-A
|
||||
interrupt void MRINTA_ISR(void); // McBSP-A
|
||||
interrupt void MXINTA_ISR(void); // McBSP-A
|
||||
interrupt void MRINTB_ISR(void); // McBSP-B
|
||||
interrupt void MXINTB_ISR(void); // McBSP-B
|
||||
|
||||
//
|
||||
// Group 7 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
|
||||
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
|
||||
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
|
||||
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
|
||||
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
|
||||
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
|
||||
|
||||
//
|
||||
// Group 8 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void I2CINT1A_ISR(void); // I2C-A
|
||||
interrupt void I2CINT2A_ISR(void); // I2C-A
|
||||
interrupt void SCIRXINTC_ISR(void); // SCI-C
|
||||
interrupt void SCITXINTC_ISR(void); // SCI-C
|
||||
|
||||
//
|
||||
// Group 9 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SCIRXINTA_ISR(void); // SCI-A
|
||||
interrupt void SCITXINTA_ISR(void); // SCI-A
|
||||
interrupt void SCIRXINTB_ISR(void); // SCI-B
|
||||
interrupt void SCITXINTB_ISR(void); // SCI-B
|
||||
interrupt void ECAN0INTA_ISR(void); // eCAN-A
|
||||
interrupt void ECAN1INTA_ISR(void); // eCAN-A
|
||||
interrupt void ECAN0INTB_ISR(void); // eCAN-B
|
||||
interrupt void ECAN1INTB_ISR(void); // eCAN-B
|
||||
|
||||
//
|
||||
// Group 10 PIE Interrupt Service Routines
|
||||
//
|
||||
|
||||
//
|
||||
// Group 11 PIE Interrupt Service Routines
|
||||
//
|
||||
|
||||
//
|
||||
// Group 12 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void XINT3_ISR(void); // External interrupt 3
|
||||
interrupt void XINT4_ISR(void); // External interrupt 4
|
||||
interrupt void XINT5_ISR(void); // External interrupt 5
|
||||
interrupt void XINT6_ISR(void); // External interrupt 6
|
||||
interrupt void XINT7_ISR(void); // External interrupt 7
|
||||
interrupt void LVF_ISR(void); // Latched overflow flag
|
||||
interrupt void LUF_ISR(void); // Latched underflow flag
|
||||
|
||||
//
|
||||
// Catch-all for Reserved Locations For testing purposes
|
||||
//
|
||||
interrupt void PIE_RESERVED(void); // Reserved for test
|
||||
interrupt void rsvd_ISR(void); // for test
|
||||
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEFAULT_ISR_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,484 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: May 12, 2008 09:34:58 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SysCtrl.h
|
||||
//
|
||||
// TITLE: DSP2833x Device System Control Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SYS_CTRL_H
|
||||
#define DSP2833x_SYS_CTRL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// System Control Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// PLL Status Register
|
||||
//
|
||||
struct PLLSTS_BITS { // bits description
|
||||
Uint16 PLLLOCKS:1; // 0 PLL lock status
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 PLLOFF:1; // 2 PLL off bit
|
||||
Uint16 MCLKSTS:1; // 3 Missing clock status bit
|
||||
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
|
||||
Uint16 OSCOFF:1; // 5 Oscillator clock off
|
||||
Uint16 MCLKOFF:1; // 6 Missing clock detect
|
||||
Uint16 DIVSEL:2; // 7 Divide Select
|
||||
Uint16 rsvd2:7; // 15:7 reserved
|
||||
};
|
||||
|
||||
union PLLSTS_REG {
|
||||
Uint16 all;
|
||||
struct PLLSTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// High speed peripheral clock register bit definitions
|
||||
//
|
||||
struct HISPCP_BITS { // bits description
|
||||
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union HISPCP_REG {
|
||||
Uint16 all;
|
||||
struct HISPCP_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Low speed peripheral clock register bit definitions
|
||||
//
|
||||
struct LOSPCP_BITS { // bits description
|
||||
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union LOSPCP_REG {
|
||||
Uint16 all;
|
||||
struct LOSPCP_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 0 bit definitions
|
||||
//
|
||||
struct PCLKCR0_BITS { // bits description
|
||||
Uint16 rsvd1:2; // 1:0 reserved
|
||||
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
|
||||
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
|
||||
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
|
||||
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
|
||||
Uint16 rsvd2:2; // 7:6 reserved
|
||||
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
|
||||
Uint16 rsvd3:1; // 9 reserved
|
||||
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
|
||||
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
|
||||
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
|
||||
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
|
||||
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
|
||||
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
|
||||
};
|
||||
|
||||
union PCLKCR0_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR0_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 1 bit definitions
|
||||
//
|
||||
struct PCLKCR1_BITS { // bits description
|
||||
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
|
||||
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
|
||||
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
|
||||
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
|
||||
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
|
||||
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
|
||||
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
|
||||
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
|
||||
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
|
||||
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
|
||||
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
|
||||
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
|
||||
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
|
||||
};
|
||||
|
||||
union PCLKCR1_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 2 bit definitions
|
||||
//
|
||||
struct PCLKCR3_BITS { // bits description
|
||||
Uint16 rsvd1:8; // 7:0 reserved
|
||||
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
|
||||
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
|
||||
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
|
||||
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
|
||||
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
|
||||
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
|
||||
Uint16 rsvd2:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union PCLKCR3_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR3_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PLL control register bit definitions
|
||||
//
|
||||
struct PLLCR_BITS { // bits description
|
||||
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union PLLCR_REG {
|
||||
Uint16 all;
|
||||
struct PLLCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Low Power Mode 0 control register bit definitions
|
||||
//
|
||||
struct LPMCR0_BITS { // bits description
|
||||
Uint16 LPM:2; // 1:0 Set the low power mode
|
||||
Uint16 QUALSTDBY:6; // 7:2 Qualification
|
||||
Uint16 rsvd1:7; // 14:8 reserved
|
||||
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
|
||||
};
|
||||
|
||||
union LPMCR0_REG {
|
||||
Uint16 all;
|
||||
struct LPMCR0_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Dual-mapping configuration register bit definitions
|
||||
//
|
||||
struct MAPCNF_BITS { // bits description
|
||||
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
|
||||
Uint16 rsvd1:15; // 15:1 reserved
|
||||
};
|
||||
|
||||
union MAPCNF_REG {
|
||||
Uint16 all;
|
||||
struct MAPCNF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// System Control Register File
|
||||
//
|
||||
struct SYS_CTRL_REGS {
|
||||
Uint16 rsvd1; // 0
|
||||
union PLLSTS_REG PLLSTS; // 1
|
||||
Uint16 rsvd2[8]; // 2-9
|
||||
|
||||
//
|
||||
// 10: High-speed peripheral clock pre-scaler
|
||||
//
|
||||
union HISPCP_REG HISPCP;
|
||||
|
||||
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
|
||||
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
|
||||
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
|
||||
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
|
||||
Uint16 rsvd3; // 15: reserved
|
||||
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
|
||||
union PLLCR_REG PLLCR; // 17: PLL control register
|
||||
|
||||
//
|
||||
// No bit definitions are defined for SCSR because
|
||||
// a read-modify-write instruction can clear the WDOVERRIDE bit
|
||||
//
|
||||
Uint16 SCSR; // 18: System control and status register
|
||||
|
||||
Uint16 WDCNTR; // 19: WD counter register
|
||||
Uint16 rsvd4; // 20
|
||||
Uint16 WDKEY; // 21: WD reset key register
|
||||
Uint16 rsvd5[3]; // 22-24
|
||||
|
||||
//
|
||||
// No bit definitions are defined for WDCR because
|
||||
// the proper value must be written to the WDCHK field
|
||||
// whenever writing to this register.
|
||||
//
|
||||
Uint16 WDCR; // 25: WD timer control register
|
||||
|
||||
Uint16 rsvd6[4]; // 26-29
|
||||
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
|
||||
Uint16 rsvd7[1]; // 31
|
||||
};
|
||||
|
||||
//
|
||||
// CSM Registers
|
||||
//
|
||||
|
||||
//
|
||||
// CSM Status & Control register bit definitions
|
||||
//
|
||||
struct CSMSCR_BITS { // bit description
|
||||
Uint16 SECURE:1; // 0 Secure flag
|
||||
Uint16 rsvd1:14; // 14-1 reserved
|
||||
Uint16 FORCESEC:1; // 15 Force Secure control bit
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union CSMSCR_REG {
|
||||
Uint16 all;
|
||||
struct CSMSCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// CSM Register File
|
||||
//
|
||||
struct CSM_REGS {
|
||||
Uint16 KEY0; // KEY reg bits 15-0
|
||||
Uint16 KEY1; // KEY reg bits 31-16
|
||||
Uint16 KEY2; // KEY reg bits 47-32
|
||||
Uint16 KEY3; // KEY reg bits 63-48
|
||||
Uint16 KEY4; // KEY reg bits 79-64
|
||||
Uint16 KEY5; // KEY reg bits 95-80
|
||||
Uint16 KEY6; // KEY reg bits 111-96
|
||||
Uint16 KEY7; // KEY reg bits 127-112
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 rsvd3; // reserved
|
||||
Uint16 rsvd4; // reserved
|
||||
Uint16 rsvd5; // reserved
|
||||
Uint16 rsvd6; // reserved
|
||||
Uint16 rsvd7; // reserved
|
||||
union CSMSCR_REG CSMSCR; // CSM Status & Control register
|
||||
};
|
||||
|
||||
//
|
||||
// Password locations
|
||||
//
|
||||
struct CSM_PWL {
|
||||
Uint16 PSWD0; // PSWD bits 15-0
|
||||
Uint16 PSWD1; // PSWD bits 31-16
|
||||
Uint16 PSWD2; // PSWD bits 47-32
|
||||
Uint16 PSWD3; // PSWD bits 63-48
|
||||
Uint16 PSWD4; // PSWD bits 79-64
|
||||
Uint16 PSWD5; // PSWD bits 95-80
|
||||
Uint16 PSWD6; // PSWD bits 111-96
|
||||
Uint16 PSWD7; // PSWD bits 127-112
|
||||
};
|
||||
|
||||
//
|
||||
// Defines for Flash Registers
|
||||
//
|
||||
#define FLASH_SLEEP 0x0000;
|
||||
#define FLASH_STANDBY 0x0001;
|
||||
#define FLASH_ACTIVE 0x0003;
|
||||
|
||||
//
|
||||
// Flash Option Register bit definitions
|
||||
//
|
||||
struct FOPT_BITS { // bit description
|
||||
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
|
||||
Uint16 rsvd:15; // 1-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FOPT_REG {
|
||||
Uint16 all;
|
||||
struct FOPT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Power Modes Register bit definitions
|
||||
//
|
||||
struct FPWR_BITS { // bit description
|
||||
Uint16 PWR:2; // 0-1 Power Mode bits
|
||||
Uint16 rsvd:14; // 2-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FPWR_REG {
|
||||
Uint16 all;
|
||||
struct FPWR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Status Register bit definitions
|
||||
//
|
||||
struct FSTATUS_BITS { // bit description
|
||||
Uint16 PWRS:2; // 0-1 Power Mode Status bits
|
||||
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
|
||||
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
|
||||
Uint16 rsvd1:4; // 4-7 reserved
|
||||
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
|
||||
Uint16 rsvd2:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FSTATUS_REG {
|
||||
Uint16 all;
|
||||
struct FSTATUS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Sleep to Standby Wait Counter Register bit definitions
|
||||
//
|
||||
struct FSTDBYWAIT_BITS { // bit description
|
||||
//
|
||||
// 0-8 Bank/Pump Sleep to Standby Wait Count bits
|
||||
//
|
||||
Uint16 STDBYWAIT:9;
|
||||
|
||||
Uint16 rsvd:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FSTDBYWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FSTDBYWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Standby to Active Wait Counter Register bit definitions
|
||||
//
|
||||
struct FACTIVEWAIT_BITS { // bit description
|
||||
//
|
||||
// 0-8 Bank/Pump Standby to Active Wait Count bits
|
||||
//
|
||||
Uint16 ACTIVEWAIT:9;
|
||||
|
||||
Uint16 rsvd:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FACTIVEWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FACTIVEWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Bank Read Access Wait State Register bit definitions
|
||||
//
|
||||
struct FBANKWAIT_BITS { // bit description
|
||||
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
|
||||
Uint16 rsvd1:4; // 4-7 reserved
|
||||
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
|
||||
Uint16 rsvd2:4; // 12-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FBANKWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FBANKWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// OTP Read Access Wait State Register bit definitions
|
||||
//
|
||||
struct FOTPWAIT_BITS { // bit description
|
||||
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
|
||||
Uint16 rsvd:11; // 5-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FOTPWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FOTPWAIT_BITS bit;
|
||||
};
|
||||
|
||||
struct FLASH_REGS {
|
||||
union FOPT_REG FOPT; // Option Register
|
||||
Uint16 rsvd1; // reserved
|
||||
union FPWR_REG FPWR; // Power Modes Register
|
||||
union FSTATUS_REG FSTATUS; // Status Register
|
||||
|
||||
//
|
||||
// Pump/Bank Sleep to Standby Wait State Register
|
||||
//
|
||||
union FSTDBYWAIT_REG FSTDBYWAIT;
|
||||
|
||||
//
|
||||
// Pump/Bank Standby to Active Wait State Register
|
||||
//
|
||||
union FACTIVEWAIT_REG FACTIVEWAIT;
|
||||
|
||||
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
|
||||
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
|
||||
};
|
||||
|
||||
//
|
||||
// System Control External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
|
||||
extern volatile struct CSM_REGS CsmRegs;
|
||||
extern volatile struct CSM_PWL CsmPwl;
|
||||
extern volatile struct FLASH_REGS FlashRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SYS_CTRL_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: August 14, 2007 16:32:29 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Dma_defines.h
|
||||
//
|
||||
// TITLE: #defines used in DMA examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DMA_DEFINES_H
|
||||
#define DSP2833x_DMA_DEFINES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// MODE
|
||||
//
|
||||
// PERINTSEL bits
|
||||
//
|
||||
#define DMA_SEQ1INT 1
|
||||
#define DMA_SEQ2INT 2
|
||||
#define DMA_XINT1 3
|
||||
#define DMA_XINT2 4
|
||||
#define DMA_XINT3 5
|
||||
#define DMA_XINT4 6
|
||||
#define DMA_XINT5 7
|
||||
#define DMA_XINT6 8
|
||||
#define DMA_XINT7 9
|
||||
#define DMA_XINT13 10
|
||||
#define DMA_TINT0 11
|
||||
#define DMA_TINT1 12
|
||||
#define DMA_TINT2 13
|
||||
#define DMA_MXEVTA 14
|
||||
#define DMA_MREVTA 15
|
||||
#define DMA_MXREVTB 16
|
||||
#define DMA_MREVTB 17
|
||||
|
||||
//
|
||||
// OVERINTE bit
|
||||
//
|
||||
#define OVRFLOW_DISABLE 0x0
|
||||
#define OVEFLOW_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PERINTE bit
|
||||
//
|
||||
#define PERINT_DISABLE 0x0
|
||||
#define PERINT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHINTMODE bits
|
||||
//
|
||||
#define CHINT_BEGIN 0x0
|
||||
#define CHINT_END 0x1
|
||||
|
||||
//
|
||||
// ONESHOT bits
|
||||
//
|
||||
#define ONESHOT_DISABLE 0x0
|
||||
#define ONESHOT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CONTINOUS bit
|
||||
//
|
||||
#define CONT_DISABLE 0x0
|
||||
#define CONT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCE bit
|
||||
//
|
||||
#define SYNC_DISABLE 0x0
|
||||
#define SYNC_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCSEL bit
|
||||
//
|
||||
#define SYNC_SRC 0x0
|
||||
#define SYNC_DST 0x1
|
||||
|
||||
//
|
||||
// DATASIZE bit
|
||||
//
|
||||
#define SIXTEEN_BIT 0x0
|
||||
#define THIRTYTWO_BIT 0x1
|
||||
|
||||
//
|
||||
// CHINTE bit
|
||||
//
|
||||
#define CHINT_DISABLE 0x0
|
||||
#define CHINT_ENABLE 0x1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,285 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:51:50 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Adc.h
|
||||
//
|
||||
// TITLE: DSP2833x Device ADC Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_ADC_H
|
||||
#define DSP2833x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// ADC Individual Register Bit Definitions:
|
||||
//
|
||||
struct ADCTRL1_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
|
||||
Uint16 SEQ_OVRD:1; // 5 Sequencer override
|
||||
Uint16 CONT_RUN:1; // 6 Continuous run
|
||||
Uint16 CPS:1; // 7 ADC core clock pre-scalar
|
||||
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
|
||||
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
|
||||
Uint16 RESET:1; // 14 ADC reset
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union ADCTRL1_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL1_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCTRL2_BITS { // bits description
|
||||
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
|
||||
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
|
||||
Uint16 rsvd2:1; // 4 reserved
|
||||
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
|
||||
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
|
||||
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
|
||||
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
|
||||
Uint16 rsvd3:1; // 9 reserved
|
||||
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
|
||||
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
|
||||
Uint16 rsvd4:1; // 12 reserved
|
||||
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
|
||||
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
|
||||
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
|
||||
};
|
||||
|
||||
union ADCTRL2_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL2_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCASEQSR_BITS { // bits description
|
||||
Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
|
||||
Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
|
||||
Uint16 rsvd1:1; // 7 reserved
|
||||
Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union ADCASEQSR_REG {
|
||||
Uint16 all;
|
||||
struct ADCASEQSR_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCMAXCONV_BITS { // bits description
|
||||
Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
|
||||
Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
|
||||
Uint16 rsvd1:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union ADCMAXCONV_REG {
|
||||
Uint16 all;
|
||||
struct ADCMAXCONV_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ1_BITS { // bits description
|
||||
Uint16 CONV00:4; // 3:0 Conversion selection 00
|
||||
Uint16 CONV01:4; // 7:4 Conversion selection 01
|
||||
Uint16 CONV02:4; // 11:8 Conversion selection 02
|
||||
Uint16 CONV03:4; // 15:12 Conversion selection 03
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ1_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ1_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ2_BITS { // bits description
|
||||
Uint16 CONV04:4; // 3:0 Conversion selection 04
|
||||
Uint16 CONV05:4; // 7:4 Conversion selection 05
|
||||
Uint16 CONV06:4; // 11:8 Conversion selection 06
|
||||
Uint16 CONV07:4; // 15:12 Conversion selection 07
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ2_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ2_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ3_BITS { // bits description
|
||||
Uint16 CONV08:4; // 3:0 Conversion selection 08
|
||||
Uint16 CONV09:4; // 7:4 Conversion selection 09
|
||||
Uint16 CONV10:4; // 11:8 Conversion selection 10
|
||||
Uint16 CONV11:4; // 15:12 Conversion selection 11
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ3_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ3_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ4_BITS { // bits description
|
||||
Uint16 CONV12:4; // 3:0 Conversion selection 12
|
||||
Uint16 CONV13:4; // 7:4 Conversion selection 13
|
||||
Uint16 CONV14:4; // 11:8 Conversion selection 14
|
||||
Uint16 CONV15:4; // 15:12 Conversion selection 15
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ4_REG {
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ4_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCTRL3_BITS { // bits description
|
||||
Uint16 SMODE_SEL:1; // 0 Sampling mode select
|
||||
Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
|
||||
Uint16 ADCPWDN:1; // 5 ADC powerdown
|
||||
Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ADCTRL3_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL3_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCST_BITS { // bits description
|
||||
Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
|
||||
Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
|
||||
Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
|
||||
Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
|
||||
Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
|
||||
Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
|
||||
Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
|
||||
Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ADCST_REG {
|
||||
Uint16 all;
|
||||
struct ADCST_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCREFSEL_BITS { // bits description
|
||||
Uint16 rsvd1:14; // 13:0 reserved
|
||||
Uint16 REF_SEL:2; // 15:14 Reference select
|
||||
};
|
||||
union ADCREFSEL_REG {
|
||||
Uint16 all;
|
||||
struct ADCREFSEL_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCOFFTRIM_BITS{ // bits description
|
||||
int16 OFFSET_TRIM:9; // 8:0 Offset Trim
|
||||
Uint16 rsvd1:7; // 15:9 reserved
|
||||
};
|
||||
|
||||
union ADCOFFTRIM_REG{
|
||||
Uint16 all;
|
||||
struct ADCOFFTRIM_BITS bit;
|
||||
};
|
||||
|
||||
struct ADC_REGS {
|
||||
union ADCTRL1_REG ADCTRL1; //ADC Control 1
|
||||
union ADCTRL2_REG ADCTRL2; //ADC Control 2
|
||||
union ADCMAXCONV_REG ADCMAXCONV; //Max conversions
|
||||
union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1
|
||||
union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2
|
||||
union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3
|
||||
union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4
|
||||
union ADCASEQSR_REG ADCASEQSR; //Autosequence status register
|
||||
Uint16 ADCRESULT0; //Conversion Result Buffer 0
|
||||
Uint16 ADCRESULT1; //Conversion Result Buffer 1
|
||||
Uint16 ADCRESULT2; //Conversion Result Buffer 2
|
||||
Uint16 ADCRESULT3; //Conversion Result Buffer 3
|
||||
Uint16 ADCRESULT4; //Conversion Result Buffer 4
|
||||
Uint16 ADCRESULT5; //Conversion Result Buffer 5
|
||||
Uint16 ADCRESULT6; //Conversion Result Buffer 6
|
||||
Uint16 ADCRESULT7; //Conversion Result Buffer 7
|
||||
Uint16 ADCRESULT8; //Conversion Result Buffer 8
|
||||
Uint16 ADCRESULT9; //Conversion Result Buffer 9
|
||||
Uint16 ADCRESULT10; //Conversion Result Buffer 10
|
||||
Uint16 ADCRESULT11; //Conversion Result Buffer 11
|
||||
Uint16 ADCRESULT12; //Conversion Result Buffer 12
|
||||
Uint16 ADCRESULT13; //Conversion Result Buffer 13
|
||||
Uint16 ADCRESULT14; //Conversion Result Buffer 14
|
||||
Uint16 ADCRESULT15; //Conversion Result Buffer 15
|
||||
union ADCTRL3_REG ADCTRL3; //ADC Control 3
|
||||
union ADCST_REG ADCST; //ADC Status Register
|
||||
Uint16 rsvd1;
|
||||
Uint16 rsvd2;
|
||||
union ADCREFSEL_REG ADCREFSEL; //Reference Select Register
|
||||
union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register
|
||||
};
|
||||
|
||||
struct ADC_RESULT_MIRROR_REGS
|
||||
{
|
||||
Uint16 ADCRESULT0; // Conversion Result Buffer 0
|
||||
Uint16 ADCRESULT1; // Conversion Result Buffer 1
|
||||
Uint16 ADCRESULT2; // Conversion Result Buffer 2
|
||||
Uint16 ADCRESULT3; // Conversion Result Buffer 3
|
||||
Uint16 ADCRESULT4; // Conversion Result Buffer 4
|
||||
Uint16 ADCRESULT5; // Conversion Result Buffer 5
|
||||
Uint16 ADCRESULT6; // Conversion Result Buffer 6
|
||||
Uint16 ADCRESULT7; // Conversion Result Buffer 7
|
||||
Uint16 ADCRESULT8; // Conversion Result Buffer 8
|
||||
Uint16 ADCRESULT9; // Conversion Result Buffer 9
|
||||
Uint16 ADCRESULT10; // Conversion Result Buffer 10
|
||||
Uint16 ADCRESULT11; // Conversion Result Buffer 11
|
||||
Uint16 ADCRESULT12; // Conversion Result Buffer 12
|
||||
Uint16 ADCRESULT13; // Conversion Result Buffer 13
|
||||
Uint16 ADCRESULT14; // Conversion Result Buffer 14
|
||||
Uint16 ADCRESULT15; // Conversion Result Buffer 15
|
||||
};
|
||||
|
||||
//
|
||||
// ADC External References & Function Declarations:
|
||||
//
|
||||
extern volatile struct ADC_REGS AdcRegs;
|
||||
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_ADC_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,807 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: May 14, 2008 16:30:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Mcbsp.h
|
||||
//
|
||||
// TITLE: DSP2833x Device McBSP Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_MCBSP_H
|
||||
#define DSP2833x_MCBSP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// McBSP Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// McBSP DRR2 register bit definitions
|
||||
//
|
||||
struct DRR2_BITS { // bit description
|
||||
Uint16 HWLB:8; // 16:23 High word low byte
|
||||
Uint16 HWHB:8; // 24:31 High word high byte
|
||||
};
|
||||
|
||||
union DRR2_REG {
|
||||
Uint16 all;
|
||||
struct DRR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DRR1 register bit definitions
|
||||
//
|
||||
struct DRR1_BITS { // bit description
|
||||
Uint16 LWLB:8; // 16:23 Low word low byte
|
||||
Uint16 LWHB:8; // 24:31 low word high byte
|
||||
};
|
||||
|
||||
union DRR1_REG {
|
||||
Uint16 all;
|
||||
struct DRR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DXR2 register bit definitions
|
||||
//
|
||||
struct DXR2_BITS { // bit description
|
||||
Uint16 HWLB:8; // 16:23 High word low byte
|
||||
Uint16 HWHB:8; // 24:31 High word high byte
|
||||
};
|
||||
|
||||
union DXR2_REG {
|
||||
Uint16 all;
|
||||
struct DXR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DXR1 register bit definitions
|
||||
//
|
||||
struct DXR1_BITS { // bit description
|
||||
Uint16 LWLB:8; // 16:23 Low word low byte
|
||||
Uint16 LWHB:8; // 24:31 low word high byte
|
||||
};
|
||||
|
||||
union DXR1_REG {
|
||||
Uint16 all;
|
||||
struct DXR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPCR2 control register bit definitions
|
||||
//
|
||||
struct SPCR2_BITS { // bit description
|
||||
Uint16 XRST:1; // 0 transmit reset
|
||||
Uint16 XRDY:1; // 1 transmit ready
|
||||
Uint16 XEMPTY:1; // 2 Transmit empty
|
||||
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
|
||||
Uint16 XINTM:2; // 5:4 Transmit interrupt types
|
||||
Uint16 GRST:1; // 6 CLKG reset
|
||||
Uint16 FRST:1; // 7 Frame sync reset
|
||||
Uint16 SOFT:1; // 8 SOFT bit
|
||||
Uint16 FREE:1; // 9 FREE bit
|
||||
Uint16 rsvd:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union SPCR2_REG {
|
||||
Uint16 all;
|
||||
struct SPCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPCR1 control register bit definitions
|
||||
//
|
||||
struct SPCR1_BITS { // bit description
|
||||
Uint16 RRST:1; // 0 Receive reset
|
||||
Uint16 RRDY:1; // 1 Receive ready
|
||||
Uint16 RFULL:1; // 2 Receive full
|
||||
Uint16 RSYNCERR:1; // 7 Receive syn error
|
||||
Uint16 RINTM:2; // 5:4 Receive interrupt types
|
||||
Uint16 rsvd1:1; // 6 reserved
|
||||
Uint16 DXENA:1; // 7 DX hi-z enable
|
||||
Uint16 rsvd2:3; // 10:8 reserved
|
||||
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
|
||||
Uint16 RJUST:2; // 13:14 Right justified
|
||||
Uint16 DLB:1; // 15 Digital loop back
|
||||
};
|
||||
|
||||
union SPCR1_REG {
|
||||
Uint16 all;
|
||||
struct SPCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCR2 control register bit definitions
|
||||
//
|
||||
struct RCR2_BITS { // bit description
|
||||
Uint16 RDATDLY:2; // 1:0 Receive data delay
|
||||
Uint16 RFIG:1; // 2 Receive frame sync ignore
|
||||
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
|
||||
Uint16 RWDLEN2:3; // 7:5 Receive word length
|
||||
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
|
||||
Uint16 RPHASE:1; // 15 Receive Phase
|
||||
};
|
||||
|
||||
union RCR2_REG {
|
||||
Uint16 all;
|
||||
struct RCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCR1 control register bit definitions
|
||||
//
|
||||
struct RCR1_BITS { // bit description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 RWDLEN1:3; // 7:5 Receive word length
|
||||
Uint16 RFRLEN1:7; // 14:8 Receive frame length
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union RCR1_REG {
|
||||
Uint16 all;
|
||||
struct RCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCR2 control register bit definitions
|
||||
//
|
||||
struct XCR2_BITS { // bit description
|
||||
Uint16 XDATDLY:2; // 1:0 Transmit data delay
|
||||
Uint16 XFIG:1; // 2 Transmit frame sync ignore
|
||||
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
|
||||
Uint16 XWDLEN2:3; // 7:5 Transmit word length
|
||||
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
|
||||
Uint16 XPHASE:1; // 15 Transmit Phase
|
||||
};
|
||||
|
||||
union XCR2_REG {
|
||||
Uint16 all;
|
||||
struct XCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCR1 control register bit definitions
|
||||
//
|
||||
struct XCR1_BITS { // bit description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 XWDLEN1:3; // 7:5 Transmit word length
|
||||
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union XCR1_REG {
|
||||
Uint16 all;
|
||||
struct XCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SRGR2 Sample rate generator control register bit definitions
|
||||
//
|
||||
struct SRGR2_BITS { // bit description
|
||||
Uint16 FPER:12; // 11:0 Frame period
|
||||
Uint16 FSGM:1; // 12 Frame sync generator mode
|
||||
Uint16 CLKSM:1; // 13 Sample rate generator mode
|
||||
Uint16 rsvd:1; // 14 reserved
|
||||
Uint16 GSYNC:1; // 15 CLKG sync
|
||||
};
|
||||
|
||||
union SRGR2_REG {
|
||||
Uint16 all;
|
||||
struct SRGR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SRGR1 control register bit definitions
|
||||
//
|
||||
struct SRGR1_BITS { // bit description
|
||||
Uint16 CLKGDV:8; // 7:0 CLKG divider
|
||||
Uint16 FWID:8; // 15:8 Frame width
|
||||
};
|
||||
|
||||
union SRGR1_REG {
|
||||
Uint16 all;
|
||||
struct SRGR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// MCR2 Multichannel control register bit definitions
|
||||
//
|
||||
struct MCR2_BITS { // bit description
|
||||
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
|
||||
Uint16 XCBLK:3; // 2:4 Transmit current block
|
||||
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
|
||||
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
|
||||
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
|
||||
Uint16 rsvd:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union MCR2_REG {
|
||||
Uint16 all;
|
||||
struct MCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// MCR1 Multichannel control register bit definitions
|
||||
//
|
||||
struct MCR1_BITS { // bit description
|
||||
Uint16 RMCM:1; // 0 Receive multichannel mode
|
||||
Uint16 rsvd:1; // 1 reserved
|
||||
Uint16 RCBLK:3; // 4:2 Receive current block
|
||||
Uint16 RPABLK:2; // 6:5 Receive partition A Block
|
||||
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
|
||||
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
|
||||
Uint16 rsvd1:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union MCR1_REG {
|
||||
Uint16 all;
|
||||
struct MCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERA control register bit definitions
|
||||
//
|
||||
struct RCERA_BITS { // bit description
|
||||
Uint16 RCEA0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEA1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEA2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEA3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEA4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEA5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEA6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEA7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEA8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEA9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEA10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEA11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEA12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEA13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEA14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEA15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERA_REG {
|
||||
Uint16 all;
|
||||
struct RCERA_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERB control register bit definitions
|
||||
//
|
||||
struct RCERB_BITS { // bit description
|
||||
Uint16 RCEB0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEB1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEB2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEB3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEB4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEB5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEB6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEB7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEB8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEB9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEB10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEB11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEB12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEB13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEB14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEB15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERB_REG {
|
||||
Uint16 all;
|
||||
struct RCERB_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERA control register bit definitions
|
||||
//
|
||||
struct XCERA_BITS { // bit description
|
||||
Uint16 XCERA0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERA1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERA2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERA3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERA4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERA5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERA6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERA7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERA8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERA9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERA10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERA11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERA12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERA13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERA14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERA15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERA_REG {
|
||||
Uint16 all;
|
||||
struct XCERA_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERB control register bit definitions
|
||||
//
|
||||
struct XCERB_BITS { // bit description
|
||||
Uint16 XCERB0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERB1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERB2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERB3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERB4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERB5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERB6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERB7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERB8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERB9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERB10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERB11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERB12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERB13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERB14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERB15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERB_REG {
|
||||
Uint16 all;
|
||||
struct XCERB_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PCR control register bit definitions
|
||||
//
|
||||
struct PCR_BITS { // bit description
|
||||
Uint16 CLKRP:1; // 0 Receive Clock polarity
|
||||
Uint16 CLKXP:1; // 1 Transmit clock polarity
|
||||
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
|
||||
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
|
||||
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
|
||||
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
|
||||
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
|
||||
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
|
||||
Uint16 CLKRM:1; // 8 Receiver Clock Mode
|
||||
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
|
||||
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
|
||||
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
|
||||
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in
|
||||
// this 28x-McBSP
|
||||
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in
|
||||
// this 28x-McBSP
|
||||
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
|
||||
Uint16 rsvd:1 ; // 15 reserved
|
||||
};
|
||||
|
||||
union PCR_REG {
|
||||
Uint16 all;
|
||||
struct PCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERC control register bit definitions
|
||||
//
|
||||
struct RCERC_BITS { // bit description
|
||||
Uint16 RCEC0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEC1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEC2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEC3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEC4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEC5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEC6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEC7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEC8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEC9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEC10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEC11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEC12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEC13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEC14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEC15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERC_REG {
|
||||
Uint16 all;
|
||||
struct RCERC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERD control register bit definitions
|
||||
//
|
||||
struct RCERD_BITS { // bit description
|
||||
Uint16 RCED0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCED1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCED2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCED3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCED4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCED5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCED6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCED7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCED8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCED9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCED10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCED11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCED12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCED13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCED14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCED15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERD_REG {
|
||||
Uint16 all;
|
||||
struct RCERD_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERC control register bit definitions
|
||||
//
|
||||
struct XCERC_BITS { // bit description
|
||||
Uint16 XCERC0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERC1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERC2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERC3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERC4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERC5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERC6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERC7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERC8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERC9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERC10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERC11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERC12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERC13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERC14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERC15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERC_REG {
|
||||
Uint16 all;
|
||||
struct XCERC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERD control register bit definitions
|
||||
//
|
||||
struct XCERD_BITS { // bit description
|
||||
Uint16 XCERD0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERD1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERD2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERD3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERD4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERD5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERD6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERD7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERD8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERD9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERD10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERD11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERD12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERD13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERD14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERD15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERD_REG {
|
||||
Uint16 all;
|
||||
struct XCERD_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERE control register bit definitions
|
||||
//
|
||||
struct RCERE_BITS { // bit description
|
||||
Uint16 RCEE0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEE1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEE2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEE3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEE4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEE5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEE6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEE7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEE8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEE9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEE10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEE11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEE12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEE13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEE14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEE15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERE_REG {
|
||||
Uint16 all;
|
||||
struct RCERE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERF control register bit definitions
|
||||
//
|
||||
struct RCERF_BITS { // bit description
|
||||
Uint16 RCEF0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEF1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEF2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEF3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEF4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEF5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEF6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEF7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEF8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEF9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEF10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEF11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEF12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEF13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEF14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEF15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERF_REG {
|
||||
Uint16 all;
|
||||
struct RCERF_BITS bit;
|
||||
};
|
||||
|
||||
// XCERE control register bit definitions:
|
||||
struct XCERE_BITS { // bit description
|
||||
Uint16 XCERE0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERE1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERE2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERE3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERE4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERE5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERE6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERE7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERE8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERE9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERE10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERE11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERE12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERE13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERE14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERE15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERE_REG {
|
||||
Uint16 all;
|
||||
struct XCERE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERF control register bit definitions
|
||||
//
|
||||
struct XCERF_BITS { // bit description
|
||||
Uint16 XCERF0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERF1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERF2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERF3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERF4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERF5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERF6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERF7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERF8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERF9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERF10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERF11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERF12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERF13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERF14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERF15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERF_REG {
|
||||
Uint16 all;
|
||||
struct XCERF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERG control register bit definitions
|
||||
//
|
||||
struct RCERG_BITS { // bit description
|
||||
Uint16 RCEG0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEG1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEG2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEG3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEG4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEG5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEG6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEG7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEG8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEG9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEG10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEG11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEG12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEG13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEG14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEG15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERG_REG {
|
||||
Uint16 all;
|
||||
struct RCERG_BITS bit;
|
||||
};
|
||||
|
||||
// RCERH control register bit definitions:
|
||||
struct RCERH_BITS { // bit description
|
||||
Uint16 RCEH0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEH1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEH2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEH3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEH4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEH5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEH6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEH7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEH8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEH9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEH10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEH11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEH12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEH13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEH14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEH15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERH_REG {
|
||||
Uint16 all;
|
||||
struct RCERH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERG control register bit definitions
|
||||
//
|
||||
struct XCERG_BITS { // bit description
|
||||
Uint16 XCERG0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERG1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERG2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERG3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERG4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERG5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERG6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERG7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERG8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERG9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERG10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERG11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERG12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERG13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERG14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERG15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERG_REG {
|
||||
Uint16 all;
|
||||
struct XCERG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERH control register bit definitions
|
||||
//
|
||||
struct XCERH_BITS { // bit description
|
||||
Uint16 XCEH0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCEH1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCEH2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCEH3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCEH4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCEH5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCEH6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCEH7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCEH8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCEH9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCEH10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCEH11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCEH12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCEH13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCEH14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCEH15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERH_REG {
|
||||
Uint16 all;
|
||||
struct XCERH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP Interrupt enable register for RINT/XINT
|
||||
//
|
||||
struct MFFINT_BITS { // bits description
|
||||
Uint16 XINT:1; // 0 XINT interrupt enable
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 RINT:1; // 2 RINT interrupt enable
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union MFFINT_REG {
|
||||
Uint16 all;
|
||||
struct MFFINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP Register File
|
||||
//
|
||||
struct MCBSP_REGS {
|
||||
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
|
||||
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
|
||||
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
|
||||
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
|
||||
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
|
||||
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
|
||||
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
|
||||
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
|
||||
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
|
||||
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
|
||||
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
|
||||
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
|
||||
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
|
||||
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
|
||||
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
|
||||
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
|
||||
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
|
||||
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
|
||||
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
|
||||
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
|
||||
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
|
||||
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
|
||||
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
|
||||
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
|
||||
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
|
||||
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
|
||||
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
|
||||
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
|
||||
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
|
||||
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
|
||||
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
|
||||
Uint16 rsvd1[4]; // reserved
|
||||
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for
|
||||
// RINT/XINT
|
||||
Uint16 rsvd2; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP External References & Function Declarations
|
||||
//
|
||||
extern volatile struct MCBSP_REGS McbspaRegs;
|
||||
extern volatile struct MCBSP_REGS McbspbRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_MCBSP_H definition
|
||||
|
||||
//
|
||||
// No more
|
||||
//
|
||||
|
||||
@@ -0,0 +1,397 @@
|
||||
// TI File $Revision: /main/11 $
|
||||
// Checkin $Date: June 23, 2008 11:34:15 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DMA.h
|
||||
//
|
||||
// TITLE: DSP2833x DMA Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DMA_H
|
||||
#define DSP2833x_DMA_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Channel MODE register bit definitions
|
||||
//
|
||||
struct MODE_BITS { // bits description
|
||||
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
|
||||
// 0 no interrupt
|
||||
// 1 SEQ1INT & ADCSYNC
|
||||
// 2 SEQ2INT
|
||||
// 3 XINT1
|
||||
// 4 XINT2
|
||||
// 5 XINT3
|
||||
// 6 XINT4
|
||||
// 7 XINT5
|
||||
// 8 XINT6
|
||||
// 9 XINT7
|
||||
// 10 XINT13
|
||||
// 11 TINT0
|
||||
// 12 TINT1
|
||||
// 13 TINT2
|
||||
// 14 MXEVTA & MXSYNCA
|
||||
// 15 MREVTA & MRSYNCA
|
||||
// 16 MXEVTB & MXSYNCB
|
||||
// 17 MREVTB & MRSYNCB
|
||||
// 18 ePWM1SOCA
|
||||
// 19 ePWM1SOCB
|
||||
// 20 ePWM2SOCA
|
||||
// 21 ePWM2SOCB
|
||||
// 22 ePWM3SOCA
|
||||
// 23 ePWM3SOCB
|
||||
// 24 ePWM4SOCA
|
||||
// 25 ePWM4SOCB
|
||||
// 26 ePWM5SOCA
|
||||
// 27 ePWM5SOCB
|
||||
// 28 ePWM6SOCA
|
||||
// 29 ePWM6SOCB
|
||||
// 30:31 no interrupt
|
||||
Uint16 rsvd1:2; // 6:5 (R=0:0)
|
||||
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
|
||||
// 0 overflow interrupt disabled
|
||||
// 1 overflow interrupt enabled
|
||||
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
|
||||
// 0 peripheral interrupt disabled
|
||||
// 1 peripheral interrupt enabled
|
||||
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
|
||||
// 0 generate interrupt at beginning of new
|
||||
// transfer
|
||||
// 1 generate interrupt at end of transfer
|
||||
Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
|
||||
// 0 only interrupt event triggers single
|
||||
// burst transfer
|
||||
// 1 first interrupt triggers burst,
|
||||
// continue until transfer count is zero
|
||||
Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
|
||||
// 0 stop when transfer count is zero
|
||||
// 1 re-initialize when transfer count is
|
||||
// zero
|
||||
Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
|
||||
// 0 ignore selected interrupt sync signal
|
||||
// 1 enable selected interrupt sync signal
|
||||
Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
|
||||
// 0 sync signal controls source wrap
|
||||
// counter
|
||||
// 1 sync signal controls destination wrap
|
||||
// counter
|
||||
Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
|
||||
// 0 16-bit data transfer size
|
||||
// 1 32-bit data transfer size
|
||||
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
|
||||
// 0 channel interrupt disabled
|
||||
// 1 channel interrupt enabled
|
||||
};
|
||||
|
||||
union MODE_REG {
|
||||
Uint16 all;
|
||||
struct MODE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Channel CONTROL register bit definitions
|
||||
//
|
||||
struct CONTROL_BITS { // bits description
|
||||
Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
|
||||
Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
|
||||
Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
|
||||
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
|
||||
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
|
||||
Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
|
||||
Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
|
||||
Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
|
||||
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
|
||||
// 0 no interrupt pending
|
||||
// 1 interrupt pending
|
||||
Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
|
||||
// 0 no sync pending
|
||||
// 1 sync pending
|
||||
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
|
||||
// 0 no sync error
|
||||
// 1 sync error detected
|
||||
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
|
||||
// 0 no transfer in progress or pending
|
||||
// 1 transfer in progress or pending
|
||||
Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
|
||||
// 0 no burst in progress or pending
|
||||
// 1 burst in progress or pending
|
||||
Uint16 RUNSTS:1; // 13 Run Status Bit (R):
|
||||
// 0 channel not running or halted
|
||||
// 1 channel running
|
||||
Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
|
||||
// 0 no overflow event
|
||||
// 1 overflow event
|
||||
Uint16 rsvd1:1; // 15 (R=0)
|
||||
};
|
||||
|
||||
union CONTROL_REG {
|
||||
Uint16 all;
|
||||
struct CONTROL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DMACTRL register bit definitions
|
||||
//
|
||||
struct DMACTRL_BITS { // bits description
|
||||
Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
|
||||
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
|
||||
Uint16 rsvd1:14; // 15:2 (R=0:0)
|
||||
};
|
||||
|
||||
union DMACTRL_REG {
|
||||
Uint16 all;
|
||||
struct DMACTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DEBUGCTRL register bit definitions
|
||||
//
|
||||
struct DEBUGCTRL_BITS { // bits description
|
||||
Uint16 rsvd1:15; // 14:0 (R=0:0)
|
||||
Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
|
||||
// 0 halt after current read-write operation
|
||||
// 1 continue running
|
||||
};
|
||||
|
||||
union DEBUGCTRL_REG {
|
||||
Uint16 all;
|
||||
struct DEBUGCTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PRIORITYCTRL1 register bit definitions
|
||||
//
|
||||
struct PRIORITYCTRL1_BITS { // bits description
|
||||
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
|
||||
// 0 same priority as all other channels
|
||||
// 1 highest priority channel
|
||||
Uint16 rsvd1:15; // 15:1 (R=0:0)
|
||||
};
|
||||
|
||||
union PRIORITYCTRL1_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYCTRL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PRIORITYSTAT register bit definitions:
|
||||
//
|
||||
struct PRIORITYSTAT_BITS { // bits description
|
||||
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
|
||||
// 0,0,0 no channel active
|
||||
// 0,0,1 Ch1 channel active
|
||||
// 0,1,0 Ch2 channel active
|
||||
// 0,1,1 Ch3 channel active
|
||||
// 1,0,0 Ch4 channel active
|
||||
// 1,0,1 Ch5 channel active
|
||||
// 1,1,0 Ch6 channel active
|
||||
Uint16 rsvd1:1; // 3 (R=0)
|
||||
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
|
||||
// 0,0,0 no channel active & interrupted by Ch1
|
||||
// 0,0,1 cannot occur
|
||||
// 0,1,0 Ch2 was active and interrupted by Ch1
|
||||
// 0,1,1 Ch3 was active and interrupted by Ch1
|
||||
// 1,0,0 Ch4 was active and interrupted by Ch1
|
||||
// 1,0,1 Ch5 was active and interrupted by Ch1
|
||||
// 1,1,0 Ch6 was active and interrupted by Ch1
|
||||
Uint16 rsvd2:9; // 15:7 (R=0:0)
|
||||
};
|
||||
|
||||
union PRIORITYSTAT_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYSTAT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Burst Size
|
||||
//
|
||||
struct BURST_SIZE_BITS { // bits description
|
||||
Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union BURST_SIZE_REG {
|
||||
Uint16 all;
|
||||
struct BURST_SIZE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Burst Count
|
||||
//
|
||||
struct BURST_COUNT_BITS { // bits description
|
||||
Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union BURST_COUNT_REG {
|
||||
Uint16 all;
|
||||
struct BURST_COUNT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DMA Channel Registers:
|
||||
//
|
||||
struct CH_REGS {
|
||||
union MODE_REG MODE; // Mode Register
|
||||
union CONTROL_REG CONTROL; // Control Register
|
||||
|
||||
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
|
||||
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
|
||||
|
||||
//
|
||||
// Source Burst Step Register
|
||||
//
|
||||
int16 SRC_BURST_STEP;
|
||||
|
||||
//
|
||||
// Destination Burst Step Register
|
||||
//
|
||||
int16 DST_BURST_STEP;
|
||||
|
||||
Uint16 TRANSFER_SIZE; // Transfer Size Register
|
||||
Uint16 TRANSFER_COUNT; // Transfer Count Register
|
||||
|
||||
//
|
||||
// Source Transfer Step Register
|
||||
//
|
||||
int16 SRC_TRANSFER_STEP;
|
||||
|
||||
//
|
||||
// Destination Transfer Step Register
|
||||
//
|
||||
int16 DST_TRANSFER_STEP;
|
||||
|
||||
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
|
||||
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
|
||||
int16 SRC_WRAP_STEP; // Source Wrap Step Register
|
||||
|
||||
//
|
||||
// Destination Wrap Size Register
|
||||
//
|
||||
Uint16 DST_WRAP_SIZE;
|
||||
|
||||
//
|
||||
// Destination Wrap Count Register
|
||||
//
|
||||
Uint16 DST_WRAP_COUNT;
|
||||
|
||||
//
|
||||
// Destination Wrap Step Register
|
||||
//
|
||||
int16 DST_WRAP_STEP;
|
||||
|
||||
//
|
||||
// Source Begin Address Shadow Register
|
||||
//
|
||||
Uint32 SRC_BEG_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Source Address Shadow Register
|
||||
//
|
||||
Uint32 SRC_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Source Begin Address Active Register
|
||||
//
|
||||
Uint32 SRC_BEG_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Source Address Active Register
|
||||
//
|
||||
Uint32 SRC_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Destination Begin Address Shadow Register
|
||||
//
|
||||
Uint32 DST_BEG_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Destination Address Shadow Register
|
||||
//
|
||||
Uint32 DST_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Destination Begin Address Active Register
|
||||
//
|
||||
Uint32 DST_BEG_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Destination Address Active Register
|
||||
//
|
||||
Uint32 DST_ADDR_ACTIVE;
|
||||
};
|
||||
|
||||
//
|
||||
// DMA Registers
|
||||
//
|
||||
struct DMA_REGS {
|
||||
union DMACTRL_REG DMACTRL; // DMA Control Register
|
||||
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
|
||||
Uint16 rsvd0; // reserved
|
||||
Uint16 rsvd1; //
|
||||
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
|
||||
Uint16 rsvd2; //
|
||||
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
|
||||
Uint16 rsvd3[25]; //
|
||||
struct CH_REGS CH1; // DMA Channel 1 Registers
|
||||
struct CH_REGS CH2; // DMA Channel 2 Registers
|
||||
struct CH_REGS CH3; // DMA Channel 3 Registers
|
||||
struct CH_REGS CH4; // DMA Channel 4 Registers
|
||||
struct CH_REGS CH5; // DMA Channel 5 Registers
|
||||
struct CH_REGS CH6; // DMA Channel 6 Registers
|
||||
};
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct DMA_REGS DmaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DMA_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: April 22, 2008 14:35:56 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP28x_Project.h
|
||||
//
|
||||
// TITLE: DSP28x Project Headerfile and Examples Include File
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP28x_PROJECT_H
|
||||
#define DSP28x_PROJECT_H
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
#endif // end of DSP28x_PROJECT_H definition
|
||||
|
||||
@@ -0,0 +1,219 @@
|
||||
#ifndef SOURCE_STATE_H_
|
||||
#define SOURCE_STATE_H_
|
||||
|
||||
#define COMM_TIME_OUT_COUNT (3000U) // 3sec
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ADC_ENGINE_HEATER_V = 0U, // 0
|
||||
IDX_ADC_GLOW_PLUG_V, // 1
|
||||
IDX_ADC_SOLENOID_V, // 2
|
||||
IDX_ADC_FUEL_PUMP_V, // 3
|
||||
IDX_ADC_COOLANT_PUMP_V, // 4
|
||||
IDX_ADC_FAN1_V, // 5
|
||||
IDX_ADC_FAN2_V, // 6
|
||||
IDX_ADC_ENGINE_HEATER_I, // 7
|
||||
IDX_ADC_GLOW_PLUG_I, // 8
|
||||
IDX_ADC_SOLENOID_I, // 9
|
||||
IDX_ADC_FUEL_PUMP_I, // 10
|
||||
IDX_ADC_COOLANT_PUMP_I, // 11
|
||||
IDX_ADC_FAN1_I, // 12
|
||||
IDX_ADC_FAN2_I, // 13
|
||||
IDX_ADC_MAX
|
||||
} E_IDX_ADC;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_WARNING_GCU_PCB_OT = 0U,
|
||||
IDX_WARNING_GCU_FET_OT,
|
||||
IDX_WARNING_GCU_WINDING1_OH,
|
||||
IDX_WARNING_GCU_WINDING2_OH,
|
||||
IDX_WARNING_GCU_MAX
|
||||
} E_IDX_WARNING_GCU;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_WARNING_ECU_ENGINE_OH = 0U,
|
||||
IDX_WARNING_ECU_RESERVED,
|
||||
IDX_WARNING_ECU_LO_OIL_PRESS,
|
||||
IDX_WARNING_ECU_INTAKE_OH,
|
||||
IDX_WARNING_ECU_INTAKE_LO_PRESS,
|
||||
IDX_WARNING_ECU_ENGINE_LO_TEMP,
|
||||
IDX_WARNING_ECU_ENGINE_SENSOR,
|
||||
IDX_WARNING_ECU_DEFAULT_ACTIVE,
|
||||
IDX_WARNING_ECU_MAX
|
||||
} E_IDX_WARNING_ECU;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_DCU_CAR_COMM = 0U, // 0
|
||||
IDX_FAULT_DCU_GCU_COMM, // 1
|
||||
IDX_FAULT_DCU_ECU_COMM, // 2
|
||||
IDX_FAULT_DCU_RPM_ERR, // 3
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4
|
||||
IDX_FAULT_DCU_GLOW_PLUG_OC, // 5
|
||||
IDX_FAULT_DCU_SOLENOID_OC, // 6
|
||||
IDX_FAULT_DCU_FUEL_PUMP_OC, // 7
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8
|
||||
IDX_FAULT_DCU_FAN1_OC, // 9
|
||||
IDX_FAULT_DCU_FAN2_OC, // 10
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12
|
||||
IDX_FAULT_DCU_GLOW_PLUG_UV, // 13
|
||||
IDX_FAULT_DCU_GLOW_PLUG_OV, // 14
|
||||
IDX_FAULT_DCU_SOLENOID_UV, // 15
|
||||
IDX_FAULT_DCU_SOLENOID_OV, // 16
|
||||
IDX_FAULT_DCU_FUEL_PUMP_UV, // 17
|
||||
IDX_FAULT_DCU_FUEL_PUMP_OV, // 18
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20
|
||||
IDX_FAULT_DCU_FAN1_UV, // 21
|
||||
IDX_FAULT_DCU_FAN1_OV, // 22
|
||||
IDX_FAULT_DCU_FAN2_UV, // 23
|
||||
IDX_FAULT_DCU_FAN2_OV, // 24
|
||||
IDX_FAULT_DCU_CRANKING_FAIL, // 25
|
||||
IDX_FAULT_DCU_MAX
|
||||
} E_IDX_DCU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_GCU_HWTRIP = 0U, // 0
|
||||
IDX_FAULT_GCU_HWIGBT, // 1
|
||||
IDX_FAULT_GCU_HW_DC, // 2
|
||||
IDX_FAULT_GCU_GEN_OCU, // 3
|
||||
IDX_FAULT_GCU_GEN_OCV, // 4
|
||||
IDX_FAULT_GCU_GEN_OCW, // 5
|
||||
IDX_FAULT_GCU_DC_OV, // 6
|
||||
IDX_FAULT_GCU_DC_OC, // 7
|
||||
|
||||
IDX_FAULT_GCU_CRANK_OC, // 8
|
||||
IDX_FAULT_GCU_PCB_OT, // 9
|
||||
IDX_FAULT_GCU_FET_OT, // 10
|
||||
IDX_FAULT_GCU_WINDING1_OH, // 11
|
||||
IDX_FAULT_GCU_WINDING2_OH, // 12
|
||||
IDX_FAULT_GCU_GEN_OS, // 13
|
||||
IDX_FAULT_GCU_RES_IC, // 14
|
||||
IDX_FAULT_GCU_RES_PRTY, // 15
|
||||
IDX_FAULT_GCU_MAX
|
||||
} E_IDX_GCU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_ECU_OIL_MS = 0U, // 0
|
||||
IDX_FAULT_ECU_INT_OH, // 1
|
||||
IDX_FAULT_ECU_ENG_OH, // 2
|
||||
IDX_FAULT_ECU_ACTUATOR, // 3
|
||||
IDX_FAULT_ECU_RPM_SIG, // 4
|
||||
IDX_FAULT_ECU_ENG_SF, // 5
|
||||
IDX_FAULT_MAX
|
||||
} E_IDX_ECU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_KEY_MAIN_POWER = 0U, // 0
|
||||
IDX_KEY_ARR_UP, // 1
|
||||
IDX_KEY_ARR_DOWN, // 2
|
||||
IDX_KEY_ENTER, // 3
|
||||
IDX_KEY_MENU, // 4
|
||||
IDX_KEY_ENG_START_STOP, // 5
|
||||
IDX_KEY_EMERGENCY, // 6
|
||||
IDX_KEY_REMOTE_START, // 7
|
||||
IDX_KEY_REMOTE_STOP, // 8
|
||||
IDX_KEY_REMOTE_EMERGENCY, // 9
|
||||
IDX_KEY_BATTLE_MODE, // 10
|
||||
IDX_KEY_MAX // 11
|
||||
} E_IDX_KEY;
|
||||
|
||||
typedef struct ClassKeyHandler
|
||||
{
|
||||
E_IDX_KEY eKey;
|
||||
void (*pAction) (void);
|
||||
} CKeyHandler;
|
||||
|
||||
typedef struct ClassAdcOperValue
|
||||
{
|
||||
Uint16 uiAdcOffsetIndex;
|
||||
Uint16 uiOffsetAdjustStart;
|
||||
} CAdcOperValue;
|
||||
|
||||
typedef struct ClassAdcCalcValue
|
||||
{
|
||||
float32 fLpfValue;
|
||||
float32 fSampledValue;
|
||||
float32 fSampledSum;
|
||||
float32 fTempAdcOffset;
|
||||
float32 fGain;
|
||||
float32 fOffset;
|
||||
Uint16 uiSamplingCount;
|
||||
int16 iAdcValue;
|
||||
} CAdcCalcValue;
|
||||
|
||||
typedef struct ClassWarningOperValue
|
||||
{
|
||||
float32 fCheckLimit; // 경고 한계 값
|
||||
Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중
|
||||
Uint16 uiDetectCount; // 경고 검출 카운터
|
||||
Uint16 uiReleaseCount; // 경고 해제 카운터
|
||||
Uint16 uiCheckTime;
|
||||
} CWarningOperValue;
|
||||
|
||||
typedef struct ClassAlarmOperValue
|
||||
{
|
||||
float32 fCheckLimit;
|
||||
float32 fFaultValue;
|
||||
Uint16 uiCheck;
|
||||
Uint16 uiCheckCount;
|
||||
Uint16 uiCheckTime;
|
||||
} CAlarmOperValue;
|
||||
|
||||
typedef struct ClassKeyList
|
||||
{
|
||||
Uint16 MainPower;
|
||||
Uint16 ArrowUp;
|
||||
Uint16 ArrowDown;
|
||||
Uint16 Enter;
|
||||
Uint16 Menu;
|
||||
Uint16 EngineStartStop;
|
||||
Uint16 Emergency;
|
||||
Uint16 BattleMode;
|
||||
} CKeyList;
|
||||
|
||||
typedef struct ClassKeyOperValue
|
||||
{
|
||||
Uint16 uiKeyWaitCount;
|
||||
Uint16 uiPreviousKey;
|
||||
Uint16 uiKeyWait;
|
||||
CKeyList KeyList;
|
||||
} CKeyOperValue;
|
||||
|
||||
extern CAdcCalcValue Adc_EngineHeater_V;
|
||||
extern CAdcCalcValue Adc_GlowPlug_V;
|
||||
extern CAdcCalcValue Adc_Solenoid_V;
|
||||
extern CAdcCalcValue Adc_FuelPump_V;
|
||||
extern CAdcCalcValue Adc_CoolantPump_V;
|
||||
extern CAdcCalcValue Adc_Fan1_V;
|
||||
extern CAdcCalcValue Adc_Fan2_V;
|
||||
|
||||
extern CAdcCalcValue Adc_EngineHeater_I;
|
||||
extern CAdcCalcValue Adc_GlowPlug_I;
|
||||
extern CAdcCalcValue Adc_Solenoid_I;
|
||||
extern CAdcCalcValue Adc_FuelPump_I;
|
||||
extern CAdcCalcValue Adc_CoolantPump_I;
|
||||
extern CAdcCalcValue Adc_Fan1_I;
|
||||
extern CAdcCalcValue Adc_Fan2_I;
|
||||
|
||||
extern CAdcOperValue AdcOperValue;
|
||||
extern CKeyOperValue KeyOperValue;
|
||||
|
||||
extern Uint32 ulDcuTotalAlarm;
|
||||
extern Uint32 ulGcuTotalAlarm;
|
||||
extern Uint32 ulEcuTotalAlarm;
|
||||
|
||||
interrupt void CAdcInterrupt(void);
|
||||
void CAlarmProcedure(void);
|
||||
void CInitAdc(void);
|
||||
void CKeyCheckProcedure(void);
|
||||
void CKeyWaitCount(void);
|
||||
void CDisplayAlarmPopup(void);
|
||||
|
||||
#endif /* SOURCE_STATE_H_ */
|
||||
@@ -0,0 +1,282 @@
|
||||
{
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_PIECTRL.H": [
|
||||
"beb797cd9bcae5c0ce186c9071f47086_",
|
||||
false,
|
||||
true,
|
||||
"f56a0095",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_PieCtrl.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/DISPLAY.C": [
|
||||
"b4e66dfc4efeb665671c8b94be6ce283",
|
||||
false,
|
||||
false,
|
||||
"1cc639a7",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Display.c"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_EPWM_DEFINES.H": [
|
||||
"1784ef9f6544b15ca51cc304251630b3_",
|
||||
false,
|
||||
true,
|
||||
"f4f62f4b",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_EPwm_defines.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/MAIN.C": [
|
||||
"b5d424479a96c0e4f4fc5ca18a4ffdc3",
|
||||
false,
|
||||
false,
|
||||
"646f103c",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/main.c"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP28X_PROJECT.H": [
|
||||
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|
||||
false,
|
||||
true,
|
||||
"515ecf84",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP28x_Project.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_SPI.H": [
|
||||
"33009c837a13a198dda5c87e283a5091_",
|
||||
false,
|
||||
true,
|
||||
"d495d271",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Spi.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_XINTF.H": [
|
||||
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|
||||
false,
|
||||
true,
|
||||
"ebb2e298",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Xintf.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_ECAN.H": [
|
||||
"70868bbf531d9aa79c87c32e4788ee4e_",
|
||||
false,
|
||||
true,
|
||||
"3e22f84d",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_ECan.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_I2C.H": [
|
||||
"0677fd7e81d1e42d5d888dd0d275b1fe_",
|
||||
false,
|
||||
true,
|
||||
"1cfec90a",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_I2c.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/OPER.C": [
|
||||
"d4d10244d3cbba60805c13f0c6e2a0c2",
|
||||
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|
||||
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|
||||
"ed3e6820",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Oper.c"
|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/LINKAGE.H": [
|
||||
"_bb64ad2ba728094bd1eb236fd1301908",
|
||||
true,
|
||||
false,
|
||||
"d0b2ad68",
|
||||
"C:/ti/ccs1281/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/linkage.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_SYSCTRL.H": [
|
||||
"dd8d114f9d4090743a4f2678af8cc2dd_",
|
||||
false,
|
||||
true,
|
||||
"eab4c7f8",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_SysCtrl.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_EQEP.H": [
|
||||
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|
||||
false,
|
||||
true,
|
||||
"9172624f",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_EQep.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_DEFAULTISR.H": [
|
||||
"d75fd8a9a8f6a4d86ed87452f4b37e5e_",
|
||||
false,
|
||||
true,
|
||||
"2036dd9a",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_DefaultIsr.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/.STATICDATA/PREINCLUDE/RECENT_PREINCLUDE_C.H": [
|
||||
"306227024c018cd03aca28832762ed44_",
|
||||
false,
|
||||
true,
|
||||
"dae7ffb3",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/.staticdata/preinclude/recent_preinclude_c.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/OPER.H": [
|
||||
"04e43fb5be4196c8a44f0c60a3b1677e",
|
||||
false,
|
||||
false,
|
||||
"5cd0d37f",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Oper.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_I2C_DEFINES.H": [
|
||||
"3932151096406d1bbe5a24cc2d6f26ea_",
|
||||
false,
|
||||
true,
|
||||
"b4ba7982",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_I2c_defines.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_DMA_DEFINES.H": [
|
||||
"df9f62d7db349a76fb310a1817f88d02_",
|
||||
false,
|
||||
true,
|
||||
"261a77df",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_Dma_defines.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_CPUTIMERS.H": [
|
||||
"c3ce07430b9437ddee99bdc151b20aae_",
|
||||
false,
|
||||
true,
|
||||
"33c71996",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_CpuTimers.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_ECAP.H": [
|
||||
"75eb44d83379bf4f199984eafdfd4d93_",
|
||||
false,
|
||||
true,
|
||||
"37dd7e48",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_ECap.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_GPIO.H": [
|
||||
"7db20b7d65499aa92f223811bf4e2ee0_",
|
||||
false,
|
||||
true,
|
||||
"77654875",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Gpio.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DMA.H": [
|
||||
"fe4f1419c3c067e59d2698ac4835fd68_",
|
||||
false,
|
||||
true,
|
||||
"ab81ed1e",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_DMA.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/STATE.H": [
|
||||
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|
||||
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|
||||
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|
||||
"c4b929cf",
|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_ADC.H": [
|
||||
"f4c48238da22647d03d8d119102df0e8_",
|
||||
false,
|
||||
true,
|
||||
"1b54d9f4",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Adc.h"
|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/STRING.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DEVICE.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_EPWM.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DEVEMU.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_SCI.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_EXAMPLES.H": [
|
||||
"886250910e6bddafd7e95146e1f5f406_",
|
||||
false,
|
||||
true,
|
||||
"f93bad3c",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_Examples.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_GLOBALPROTOTYPES.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_MCBSP.H": [
|
||||
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|
||||
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|
||||
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|
||||
"87a1351b",
|
||||
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|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/MAIN.H": [
|
||||
"87db14bcf223072d659483224d9ba3a7",
|
||||
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|
||||
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|
||||
"44e5859",
|
||||
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|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/_TI_CONFIG.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/DISPLAY.H": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/STATE.C": [
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_XINTRUPT.H": [
|
||||
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|
||||
false,
|
||||
true,
|
||||
"4e30eafc",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_XIntrupt.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_PIEVECT.H": [
|
||||
"7d86d3df0c09119c711baf3e0fc3da7a_",
|
||||
false,
|
||||
true,
|
||||
"f09c16ca",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_PieVect.h"
|
||||
]
|
||||
}
|
||||
@@ -0,0 +1,63 @@
|
||||
#ifndef SOURCE_OPER_H_
|
||||
#define SOURCE_OPER_H_
|
||||
|
||||
typedef struct ClassLedPattern
|
||||
{
|
||||
Uint16 Fault;
|
||||
Uint16 Operation;
|
||||
Uint16 Stop;
|
||||
} CLedPattern;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_APU_OPER_BOOT = 0U, // 0 부팅
|
||||
IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화
|
||||
IDX_APU_OPER_POST, // 2 자체 진단
|
||||
IDX_APU_OPER_EMERGENCY, // 3 비상 정지
|
||||
IDX_APU_OPER_STANDBY, // 4 대기
|
||||
IDX_APU_OPER_READY, // 5 준비 상태
|
||||
IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열
|
||||
IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동
|
||||
IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도
|
||||
IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기
|
||||
IDX_APU_OPER_GENERATING, // 10 발전 시작
|
||||
IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시)
|
||||
IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단
|
||||
} E_IDX_APU_OPER;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ECU_STAT_STANDBY = 0U, // 0
|
||||
IDX_ECU_STAT_STARTING, // 1
|
||||
IDX_ECU_STAT_IDLE, // 2
|
||||
IDX_ECU_STAT_OPERATION, // 3
|
||||
IDX_ECU_STAT_DERATING, // 4
|
||||
IDX_ECU_STAT_COOLDOWN, // 5
|
||||
IDX_ECU_STAT_STOP // 6
|
||||
} E_IDX_ECU_STAT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_GCU_CMD_STOP = 0U, // 0
|
||||
IDX_GCU_CMD_CRANKING, // 1
|
||||
IDX_GCU_CMD_STOP_CRANKING, // 2
|
||||
IDX_GCU_CMD_GENERATING // 3
|
||||
} E_IDX_GCU_CMD;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ECU_CMD_STOP = 0U, // 0
|
||||
IDX_ECU_CMD_START, // 1
|
||||
IDX_ECU_CMD_EMERGENCY // 2
|
||||
} E_IDX_ECU_CMD;
|
||||
|
||||
void CApuOperProcedure(void);
|
||||
void CDebugModeProcedure(void);
|
||||
void CLedControlProcedure(void);
|
||||
int16 CGetEngCoolantTemperature(void);
|
||||
Uint16 CGetGeneratorRpm(void);
|
||||
Uint16 CGetEngineActualRpm(void);
|
||||
void CSetGcuCommand(Uint16 Command);
|
||||
void CSetEcuCommand(Uint16 Command);
|
||||
|
||||
#endif /* SOURCE_OPER_H_ */
|
||||
@@ -0,0 +1,233 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 22, 2007 10:40:22 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2c.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
|
||||
// Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_I2C_H
|
||||
#define DSP2833x_I2C_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// I2C interrupt vector register bit definitions
|
||||
//
|
||||
struct I2CISRC_BITS { // bits description
|
||||
Uint16 INTCODE:3; // 2:0 Interrupt code
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union I2CISRC_REG {
|
||||
Uint16 all;
|
||||
struct I2CISRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C interrupt mask register bit definitions
|
||||
//
|
||||
struct I2CIER_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration lost interrupt
|
||||
Uint16 NACK:1; // 1 No ack interrupt
|
||||
Uint16 ARDY:1; // 2 Register access ready interrupt
|
||||
Uint16 RRDY:1; // 3 Recieve data ready interrupt
|
||||
Uint16 XRDY:1; // 4 Transmit data ready interrupt
|
||||
Uint16 SCD:1; // 5 Stop condition detection
|
||||
Uint16 AAS:1; // 6 Address as slave
|
||||
Uint16 rsvd:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union I2CIER_REG {
|
||||
Uint16 all;
|
||||
struct I2CIER_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C status register bit definitions
|
||||
//
|
||||
struct I2CSTR_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration lost interrupt
|
||||
Uint16 NACK:1; // 1 No ack interrupt
|
||||
Uint16 ARDY:1; // 2 Register access ready interrupt
|
||||
Uint16 RRDY:1; // 3 Recieve data ready interrupt
|
||||
Uint16 XRDY:1; // 4 Transmit data ready interrupt
|
||||
Uint16 SCD:1; // 5 Stop condition detection
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 AD0:1; // 8 Address Zero
|
||||
Uint16 AAS:1; // 9 Address as slave
|
||||
Uint16 XSMT:1; // 10 XMIT shift empty
|
||||
Uint16 RSFULL:1; // 11 Recieve shift full
|
||||
Uint16 BB:1; // 12 Bus busy
|
||||
Uint16 NACKSNT:1; // 13 A no ack sent
|
||||
Uint16 SDIR:1; // 14 Slave direction
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CSTR_REG {
|
||||
Uint16 all;
|
||||
struct I2CSTR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C mode control register bit definitions
|
||||
//
|
||||
struct I2CMDR_BITS { // bits description
|
||||
Uint16 BC:3; // 2:0 Bit count
|
||||
Uint16 FDF:1; // 3 Free data format
|
||||
Uint16 STB:1; // 4 Start byte
|
||||
Uint16 IRS:1; // 5 I2C Reset not
|
||||
Uint16 DLB:1; // 6 Digital loopback
|
||||
Uint16 RM:1; // 7 Repeat mode
|
||||
Uint16 XA:1; // 8 Expand address
|
||||
Uint16 TRX:1; // 9 Transmitter/reciever
|
||||
Uint16 MST:1; // 10 Master/slave
|
||||
Uint16 STP:1; // 11 Stop condition
|
||||
Uint16 rsvd1:1; // 12 reserved
|
||||
Uint16 STT:1; // 13 Start condition
|
||||
Uint16 FREE:1; // 14 Emulation mode
|
||||
Uint16 NACKMOD:1; // 15 No Ack mode
|
||||
};
|
||||
|
||||
union I2CMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CMDR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C extended mode control register bit definitions
|
||||
//
|
||||
struct I2CEMDR_BITS { // bits description
|
||||
Uint16 BCM:1; // 0 Backward compatibility mode
|
||||
Uint16 rsvd:15; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CEMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CEMDR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// I2C pre-scaler register bit definitions
|
||||
//
|
||||
struct I2CPSC_BITS { // bits description
|
||||
Uint16 IPSC:8; // 7:0 pre-scaler
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union I2CPSC_REG {
|
||||
Uint16 all;
|
||||
struct I2CPSC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TX FIFO control register bit definitions
|
||||
//
|
||||
struct I2CFFTX_BITS { // bits description
|
||||
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
|
||||
Uint16 TXFFINTCLR:1; // 6 FIFO clear
|
||||
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO level status
|
||||
Uint16 TXFFRST:1; // 13 FIFO reset
|
||||
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
|
||||
Uint16 rsvd1:1; // 15 reserved
|
||||
};
|
||||
|
||||
union I2CFFTX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RX FIFO control register bit definitions
|
||||
//
|
||||
struct I2CFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
|
||||
Uint16 RXFFINTCLR:1; // 6 FIFO clear
|
||||
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO level
|
||||
Uint16 RXFFRST:1; // 13 FIFO reset
|
||||
Uint16 rsvd1:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union I2CFFRX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFRX_BITS bit;
|
||||
};
|
||||
|
||||
struct I2C_REGS {
|
||||
Uint16 I2COAR; // Own address register
|
||||
union I2CIER_REG I2CIER; // Interrupt enable
|
||||
union I2CSTR_REG I2CSTR; // Interrupt status
|
||||
Uint16 I2CCLKL; // Clock divider low
|
||||
Uint16 I2CCLKH; // Clock divider high
|
||||
Uint16 I2CCNT; // Data count
|
||||
Uint16 I2CDRR; // Data recieve
|
||||
Uint16 I2CSAR; // Slave address
|
||||
Uint16 I2CDXR; // Data transmit
|
||||
union I2CMDR_REG I2CMDR; // Mode
|
||||
union I2CISRC_REG I2CISRC; // Interrupt source
|
||||
union I2CEMDR_REG I2CEMDR; // Extended Mode
|
||||
union I2CPSC_REG I2CPSC; // Pre-scaler
|
||||
Uint16 rsvd2[19]; // reserved
|
||||
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
|
||||
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
|
||||
};
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct I2C_REGS I2caRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_I2C_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,243 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:45:39 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm_defines.h
|
||||
//
|
||||
// TITLE: #defines used in ePWM examples examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EPWM_DEFINES_H
|
||||
#define DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// TBCTL (Time-Base Control)
|
||||
//
|
||||
// CTRMODE bits
|
||||
//
|
||||
#define TB_COUNT_UP 0x0
|
||||
#define TB_COUNT_DOWN 0x1
|
||||
#define TB_COUNT_UPDOWN 0x2
|
||||
#define TB_FREEZE 0x3
|
||||
|
||||
//
|
||||
// PHSEN bit
|
||||
//
|
||||
#define TB_DISABLE 0x0
|
||||
#define TB_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PRDLD bit
|
||||
//
|
||||
#define TB_SHADOW 0x0
|
||||
#define TB_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// SYNCOSEL bits
|
||||
//
|
||||
#define TB_SYNC_IN 0x0
|
||||
#define TB_CTR_ZERO 0x1
|
||||
#define TB_CTR_CMPB 0x2
|
||||
#define TB_SYNC_DISABLE 0x3
|
||||
|
||||
//
|
||||
// HSPCLKDIV and CLKDIV bits
|
||||
//
|
||||
#define TB_DIV1 0x0
|
||||
#define TB_DIV2 0x1
|
||||
#define TB_DIV4 0x2
|
||||
|
||||
//
|
||||
// PHSDIR bit
|
||||
//
|
||||
#define TB_DOWN 0x0
|
||||
#define TB_UP 0x1
|
||||
|
||||
//
|
||||
// CMPCTL (Compare Control)
|
||||
//
|
||||
// LOADAMODE and LOADBMODE bits
|
||||
//
|
||||
#define CC_CTR_ZERO 0x0
|
||||
#define CC_CTR_PRD 0x1
|
||||
#define CC_CTR_ZERO_PRD 0x2
|
||||
#define CC_LD_DISABLE 0x3
|
||||
|
||||
//
|
||||
// SHDWAMODE and SHDWBMODE bits
|
||||
//
|
||||
#define CC_SHADOW 0x0
|
||||
#define CC_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// AQCTLA and AQCTLB (Action Qualifier Control)
|
||||
//
|
||||
// ZRO, PRD, CAU, CAD, CBU, CBD bits
|
||||
//
|
||||
#define AQ_NO_ACTION 0x0
|
||||
#define AQ_CLEAR 0x1
|
||||
#define AQ_SET 0x2
|
||||
#define AQ_TOGGLE 0x3
|
||||
|
||||
//
|
||||
// DBCTL (Dead-Band Control)
|
||||
//
|
||||
// OUT MODE bits
|
||||
//
|
||||
#define DB_DISABLE 0x0
|
||||
#define DBB_ENABLE 0x1
|
||||
#define DBA_ENABLE 0x2
|
||||
#define DB_FULL_ENABLE 0x3
|
||||
|
||||
//
|
||||
// POLSEL bits
|
||||
//
|
||||
#define DB_ACTV_HI 0x0
|
||||
#define DB_ACTV_LOC 0x1
|
||||
#define DB_ACTV_HIC 0x2
|
||||
#define DB_ACTV_LO 0x3
|
||||
|
||||
//
|
||||
// IN MODE
|
||||
//
|
||||
#define DBA_ALL 0x0
|
||||
#define DBB_RED_DBA_FED 0x1
|
||||
#define DBA_RED_DBB_FED 0x2
|
||||
#define DBB_ALL 0x3
|
||||
|
||||
//
|
||||
// CHPCTL (chopper control)
|
||||
//
|
||||
// CHPEN bit
|
||||
//
|
||||
#define CHP_DISABLE 0x0
|
||||
#define CHP_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHPFREQ bits
|
||||
//
|
||||
#define CHP_DIV1 0x0
|
||||
#define CHP_DIV2 0x1
|
||||
#define CHP_DIV3 0x2
|
||||
#define CHP_DIV4 0x3
|
||||
#define CHP_DIV5 0x4
|
||||
#define CHP_DIV6 0x5
|
||||
#define CHP_DIV7 0x6
|
||||
#define CHP_DIV8 0x7
|
||||
|
||||
//
|
||||
// CHPDUTY bits
|
||||
//
|
||||
#define CHP1_8TH 0x0
|
||||
#define CHP2_8TH 0x1
|
||||
#define CHP3_8TH 0x2
|
||||
#define CHP4_8TH 0x3
|
||||
#define CHP5_8TH 0x4
|
||||
#define CHP6_8TH 0x5
|
||||
#define CHP7_8TH 0x6
|
||||
|
||||
//
|
||||
// TZSEL (Trip Zone Select)
|
||||
//
|
||||
// CBCn and OSHTn bits
|
||||
//
|
||||
#define TZ_DISABLE 0x0
|
||||
#define TZ_ENABLE 0x1
|
||||
|
||||
//
|
||||
// TZCTL (Trip Zone Control)
|
||||
//
|
||||
// TZA and TZB bits
|
||||
//
|
||||
#define TZ_HIZ 0x0
|
||||
#define TZ_FORCE_HI 0x1
|
||||
#define TZ_FORCE_LO 0x2
|
||||
#define TZ_NO_CHANGE 0x3
|
||||
|
||||
//
|
||||
// ETSEL (Event Trigger Select)
|
||||
//
|
||||
#define ET_CTR_ZERO 0x1
|
||||
#define ET_CTR_PRD 0x2
|
||||
#define ET_CTRU_CMPA 0x4
|
||||
#define ET_CTRD_CMPA 0x5
|
||||
#define ET_CTRU_CMPB 0x6
|
||||
#define ET_CTRD_CMPB 0x7
|
||||
|
||||
//
|
||||
// ETPS (Event Trigger Pre-scale)
|
||||
//
|
||||
// INTPRD, SOCAPRD, SOCBPRD bits
|
||||
//
|
||||
#define ET_DISABLE 0x0
|
||||
#define ET_1ST 0x1
|
||||
#define ET_2ND 0x2
|
||||
#define ET_3RD 0x3
|
||||
|
||||
//
|
||||
// HRPWM (High Resolution PWM)
|
||||
//
|
||||
// HRCNFG
|
||||
//
|
||||
#define HR_Disable 0x0
|
||||
#define HR_REP 0x1
|
||||
#define HR_FEP 0x2
|
||||
#define HR_BEP 0x3
|
||||
|
||||
#define HR_CMP 0x0
|
||||
#define HR_PHS 0x1
|
||||
|
||||
#define HR_CTR_ZERO 0x0
|
||||
#define HR_CTR_PRD 0x1
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,156 @@
|
||||
#ifndef SOURCE_DISPLAY_H_
|
||||
#define SOURCE_DISPLAY_H_
|
||||
|
||||
#define ZONE6_DAT *(volatile Uint16*)0x00100001
|
||||
#define ZONE6_COM *(volatile Uint16*)0x00100000
|
||||
|
||||
#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127
|
||||
#define OLED_HEIGHT (64U)
|
||||
#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7
|
||||
|
||||
#define TXT_ENG_WIDTH (6U)
|
||||
#define TXT_ENG_HEIGHT (12U)
|
||||
|
||||
#define TXT_TYPE_ENG (0U)
|
||||
#define TXT_TYPE_ETC (1U)
|
||||
|
||||
#define TXT_MAX_LEN (22U)
|
||||
#define TXT_LINE_LEN (5U)
|
||||
|
||||
#define OLED_LOAD_PROGRESS_X (14U)
|
||||
#define OLED_LOAD_PROGRESS_Y (52U)
|
||||
#define OLED_LOAD_PROGRESS_W (114U)
|
||||
#define OLED_LOAD_PROGRESS_H (10U)
|
||||
|
||||
#define MODE_COMMAND (0U)
|
||||
#define MODE_DATA (1U)
|
||||
|
||||
#define DIR_UP (1U)
|
||||
#define DIR_DOWN (0U)
|
||||
|
||||
typedef signed char int8;
|
||||
typedef unsigned char Uint8;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_LINE_TITLE = 0U,
|
||||
IDX_OLED_LINE_1 = 14U,
|
||||
IDX_OLED_LINE_2 = 27U,
|
||||
IDX_OLED_LINE_3 = 40U,
|
||||
IDX_OLED_LINE_4 = 53U
|
||||
} E_IDX_OLED_LINE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_ROW_0 = 0U,
|
||||
IDX_OLED_ROW_1,
|
||||
IDX_OLED_ROW_2,
|
||||
IDX_OLED_ROW_3,
|
||||
IDX_OLED_ROW_4
|
||||
} E_IDX_OLED_ROW;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_PASS_DIGIT_1 = 0U,
|
||||
IDX_OLED_PASS_DIGIT_2,
|
||||
IDX_OLED_PASS_DIGIT_3,
|
||||
IDX_OLED_PASS_DIGIT_4
|
||||
} E_IDX_OLED_PASS;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_PAGE_APU1 = 0U, // 0
|
||||
IDX_OLED_PAGE_APU2, // 1
|
||||
IDX_OLED_PAGE_MENU1, // 2
|
||||
IDX_OLED_PAGE_MENU2, // 3
|
||||
IDX_OLED_PAGE_TEMP, // 4
|
||||
IDX_OLED_PAGE_SENSOR1, // 5
|
||||
IDX_OLED_PAGE_SENSOR2, // 6
|
||||
IDX_OLED_PAGE_SENSOR3, // 7
|
||||
IDX_OLED_PAGE_SENSOR4, // 8
|
||||
IDX_OLED_PAGE_WARNING1, // 9
|
||||
IDX_OLED_PAGE_WARNING2, // 10
|
||||
IDX_OLED_PAGE_FAULT1, // 11
|
||||
IDX_OLED_PAGE_FAULT2, // 12
|
||||
IDX_OLED_PAGE_FAULT3, // 13
|
||||
IDX_OLED_PAGE_FAULT4, // 14
|
||||
IDX_OLED_PAGE_FAULT5, // 15
|
||||
IDX_OLED_PAGE_FAULT6, // 16
|
||||
IDX_OLED_PAGE_FAULT7, // 17
|
||||
IDX_OLED_PAGE_RESET_ALARM, // 18
|
||||
IDX_OLED_PAGE_PASSWORD, // 19
|
||||
IDX_OLED_PAGE_MAINTENANCE, // 20
|
||||
IDX_OLED_PAGE_VERSION, // 21
|
||||
IDX_OLED_PAGE_KEY_TEST, // 21
|
||||
IDX_OLED_PAGE_SHUTDOWN, // 23
|
||||
IDX_OLED_PAGE_MAX
|
||||
} E_IDX_OLED_PAGE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_MENU_APU = 0U, // 0
|
||||
IDX_OLED_MENU_TEMP, // 1
|
||||
IDX_OLED_MENU_SENSOR, // 2
|
||||
IDX_OLED_MENU_WARNING, // 3
|
||||
} E_IDX_OLED_MENU1;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_MENU_FAULT = 0U, // 0
|
||||
IDX_OLED_MENU_RESET, // 1
|
||||
IDX_OLED_MENU_DEBUG // 2
|
||||
} E_IDX_OLED_MENU2;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_OLED_LINE_FOCUS_1 = 0U,
|
||||
IDX_OLED_LINE_FOCUS_2,
|
||||
IDX_OLED_LINE_FOCUS_3,
|
||||
IDX_OLED_LINE_FOCUS_4
|
||||
} E_IDX_OLED_LINE_FOCUS;
|
||||
|
||||
typedef struct ClassPageHandler
|
||||
{
|
||||
Uint16 uiPage;
|
||||
void (*pAction) (void); // PageTable 참조
|
||||
} CPageHandler;
|
||||
|
||||
typedef struct ClassOledOperValue
|
||||
{
|
||||
Uint16 uiBuff[OLED_WIDTH][OLED_PAGE];
|
||||
Uint16 uiPageNum;
|
||||
Uint16 uiOldPageNum;
|
||||
Uint16 uiFocusLine;
|
||||
Uint16 uiPrevFocusLine;
|
||||
Uint16 uiFocusDigit;
|
||||
Uint16 uiProgressValue;
|
||||
Uint16 uiProgressDone;
|
||||
Uint16 uiResetAlarmAnswer;
|
||||
Uint16 uiResetHourAnswer;
|
||||
int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN];
|
||||
int8 cAlignBuffer[TXT_MAX_LEN];
|
||||
struct
|
||||
{
|
||||
Uint16 TxtColor;
|
||||
Uint16 BgColor;
|
||||
} Color;
|
||||
struct
|
||||
{
|
||||
Uint16 X;
|
||||
Uint16 Y;
|
||||
} Point;
|
||||
} COledOperValue;
|
||||
|
||||
void CInitXintf(void);
|
||||
void CInitOled(void);
|
||||
void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height);
|
||||
void CDisplayPostFail(void);
|
||||
void CSetPage(Uint16 PageNum);
|
||||
void CInitKeyOperValue(void);
|
||||
void CInitializePage(void);
|
||||
void COledBufferReset(void);
|
||||
void CDisplayAntiNoiseRefresh(void);
|
||||
|
||||
extern COledOperValue OledOperValue;
|
||||
|
||||
#endif /* SOURCE_DISPLAY_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c;
|
||||
extern unsigned int codescroll_built_in_line_macro;
|
||||
@@ -0,0 +1,208 @@
|
||||
// TI File $Revision: /main/3 $
|
||||
// Checkin $Date: April 17, 2008 11:08:27 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Spi.h
|
||||
//
|
||||
// TITLE: DSP2833x Device SPI Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SPI_H
|
||||
#define DSP2833x_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// SPI Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// SPI FIFO Transmit register bit definitions
|
||||
//
|
||||
struct SPIFFTX_BITS { // bit description
|
||||
Uint16 TXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 TXFFINT:1; // 7 INT flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO status
|
||||
Uint16 TXFIFO:1; // 13 FIFO reset
|
||||
Uint16 SPIFFENA:1; // 14 Enhancement enable
|
||||
Uint16 SPIRST:1; // 15 Reset SPI
|
||||
};
|
||||
|
||||
union SPIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI FIFO recieve register bit definitions
|
||||
//
|
||||
struct SPIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 RXFFINT:1; // 7 INT flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO status
|
||||
Uint16 RXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
|
||||
Uint16 RXFFOVF:1; // 15 FIFO overflow
|
||||
};
|
||||
|
||||
union SPIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI FIFO control register bit definitions
|
||||
//
|
||||
struct SPIFFCT_BITS { // bits description
|
||||
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI configuration register bit definitions
|
||||
//
|
||||
struct SPICCR_BITS { // bits description
|
||||
Uint16 SPICHAR:4; // 3:0 Character length control
|
||||
Uint16 SPILBK:1; // 4 Loop-back enable/disable
|
||||
Uint16 rsvd1:1; // 5 reserved
|
||||
Uint16 CLKPOLARITY:1; // 6 Clock polarity
|
||||
Uint16 SPISWRESET:1; // 7 SPI SW Reset
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPICCR_REG {
|
||||
Uint16 all;
|
||||
struct SPICCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI operation control register bit definitions
|
||||
//
|
||||
struct SPICTL_BITS { // bits description
|
||||
Uint16 SPIINTENA:1; // 0 Interrupt enable
|
||||
Uint16 TALK:1; // 1 Master/Slave transmit enable
|
||||
Uint16 MASTER_SLAVE:1; // 2 Network control mode
|
||||
Uint16 CLK_PHASE:1; // 3 Clock phase select
|
||||
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
|
||||
Uint16 rsvd:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union SPICTL_REG {
|
||||
Uint16 all;
|
||||
struct SPICTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI status register bit definitions
|
||||
//
|
||||
struct SPISTS_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
|
||||
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
|
||||
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SPISTS_REG {
|
||||
Uint16 all;
|
||||
struct SPISTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI priority control register bit definitions
|
||||
//
|
||||
struct SPIPRI_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 FREE:1; // 4 Free emulation mode control
|
||||
Uint16 SOFT:1; // 5 Soft emulation mode control
|
||||
Uint16 rsvd2:1; // 6 reserved
|
||||
Uint16 rsvd3:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union SPIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SPIPRI_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPI Register File
|
||||
//
|
||||
struct SPI_REGS {
|
||||
union SPICCR_REG SPICCR; // Configuration register
|
||||
union SPICTL_REG SPICTL; // Operation control register
|
||||
union SPISTS_REG SPISTS; // Status register
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 SPIBRR; // Baud Rate
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 SPIRXEMU; // Emulation buffer
|
||||
Uint16 SPIRXBUF; // Serial input buffer
|
||||
Uint16 SPITXBUF; // Serial output buffer
|
||||
Uint16 SPIDAT; // Serial data
|
||||
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
|
||||
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
|
||||
union SPIFFCT_REG SPIFFCT; // FIFO control register
|
||||
Uint16 rsvd3[2]; // reserved
|
||||
union SPIPRI_REG SPIPRI; // FIFO Priority control
|
||||
};
|
||||
|
||||
//
|
||||
// SPI External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SPI_REGS SpiaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SPI_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,131 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: April 15, 2009 10:05:17 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DevEmu.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Emulation Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEV_EMU_H
|
||||
#define DSP2833x_DEV_EMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Device Emulation Register Bit Definitions:
|
||||
//
|
||||
|
||||
//
|
||||
// Device Configuration Register Bit Definitions
|
||||
//
|
||||
struct DEVICECNF_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 reserved
|
||||
Uint16 VMAPS:1; // 3 VMAP Status
|
||||
Uint16 rsvd2:1; // 4 reserved
|
||||
Uint16 XRSn:1; // 5 XRSn Signal Status
|
||||
Uint16 rsvd3:10; // 15:6
|
||||
Uint16 rsvd4:3; // 18:16
|
||||
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
|
||||
Uint16 rsvd5:7; // 26:20 reserved
|
||||
Uint16 TRSTN:1; // 27 Status of TRSTn signal
|
||||
Uint16 rsvd6:4; // 31:28 reserved
|
||||
};
|
||||
|
||||
union DEVICECNF_REG {
|
||||
Uint32 all;
|
||||
struct DEVICECNF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// CLASSID
|
||||
//
|
||||
struct CLASSID_BITS { // bits description
|
||||
Uint16 CLASSNO:8; // 7:0 Class Number
|
||||
Uint16 PARTTYPE:8; // 15:8 Part Type
|
||||
};
|
||||
|
||||
union CLASSID_REG {
|
||||
Uint16 all;
|
||||
struct CLASSID_BITS bit;
|
||||
};
|
||||
|
||||
struct DEV_EMU_REGS {
|
||||
union DEVICECNF_REG DEVICECNF; // device configuration
|
||||
union CLASSID_REG CLASSID; // Class ID
|
||||
Uint16 REVID; // Device ID
|
||||
Uint16 PROTSTART; // Write-Read protection start
|
||||
Uint16 PROTRANGE; // Write-Read protection range
|
||||
Uint16 rsvd2[202];
|
||||
};
|
||||
|
||||
//
|
||||
// PARTID
|
||||
//
|
||||
struct PARTID_BITS { // bits description
|
||||
Uint16 PARTNO:8; // 7:0 Part Number
|
||||
Uint16 PARTTYPE:8; // 15:8 Part Type
|
||||
};
|
||||
|
||||
union PARTID_REG {
|
||||
Uint16 all;
|
||||
struct PARTID_BITS bit;
|
||||
};
|
||||
|
||||
struct PARTID_REGS {
|
||||
union PARTID_REG PARTID; // Part ID
|
||||
};
|
||||
|
||||
//
|
||||
// Device Emulation Register References & Function Declarations
|
||||
//
|
||||
extern volatile struct DEV_EMU_REGS DevEmuRegs;
|
||||
extern volatile struct PARTID_REGS PartIdRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEV_EMU_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,179 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: April 16, 2008 17:16:47 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2cExample.h
|
||||
//
|
||||
// TITLE: 2833x I2C Example Code Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_I2C_DEFINES_H
|
||||
#define DSP2833x_I2C_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Error Messages
|
||||
//
|
||||
#define I2C_ERROR 0xFFFF
|
||||
#define I2C_ARB_LOST_ERROR 0x0001
|
||||
#define I2C_NACK_ERROR 0x0002
|
||||
#define I2C_BUS_BUSY_ERROR 0x1000
|
||||
#define I2C_STP_NOT_READY_ERROR 0x5555
|
||||
#define I2C_NO_FLAGS 0xAAAA
|
||||
#define I2C_SUCCESS 0x0000
|
||||
|
||||
//
|
||||
// Clear Status Flags
|
||||
//
|
||||
#define I2C_CLR_AL_BIT 0x0001
|
||||
#define I2C_CLR_NACK_BIT 0x0002
|
||||
#define I2C_CLR_ARDY_BIT 0x0004
|
||||
#define I2C_CLR_RRDY_BIT 0x0008
|
||||
#define I2C_CLR_SCD_BIT 0x0020
|
||||
|
||||
//
|
||||
// Interrupt Source Messages
|
||||
//
|
||||
#define I2C_NO_ISRC 0x0000
|
||||
#define I2C_ARB_ISRC 0x0001
|
||||
#define I2C_NACK_ISRC 0x0002
|
||||
#define I2C_ARDY_ISRC 0x0003
|
||||
#define I2C_RX_ISRC 0x0004
|
||||
#define I2C_TX_ISRC 0x0005
|
||||
#define I2C_SCD_ISRC 0x0006
|
||||
#define I2C_AAS_ISRC 0x0007
|
||||
|
||||
//
|
||||
// I2CMSG structure defines
|
||||
//
|
||||
#define I2C_NO_STOP 0
|
||||
#define I2C_YES_STOP 1
|
||||
#define I2C_RECEIVE 0
|
||||
#define I2C_TRANSMIT 1
|
||||
#define I2C_MAX_BUFFER_SIZE 16
|
||||
|
||||
//
|
||||
// I2C Slave State defines
|
||||
//
|
||||
#define I2C_NOTSLAVE 0
|
||||
#define I2C_ADDR_AS_SLAVE 1
|
||||
#define I2C_ST_MSG_READY 2
|
||||
|
||||
//
|
||||
// I2C Slave Receiver messages defines
|
||||
//
|
||||
#define I2C_SND_MSG1 1
|
||||
#define I2C_SND_MSG2 2
|
||||
|
||||
//
|
||||
// I2C State defines
|
||||
//
|
||||
#define I2C_IDLE 0
|
||||
#define I2C_SLAVE_RECEIVER 1
|
||||
#define I2C_SLAVE_TRANSMITTER 2
|
||||
#define I2C_MASTER_RECEIVER 3
|
||||
#define I2C_MASTER_TRANSMITTER 4
|
||||
|
||||
//
|
||||
// I2C Message Commands for I2CMSG struct
|
||||
//
|
||||
#define I2C_MSGSTAT_INACTIVE 0x0000
|
||||
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
|
||||
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
|
||||
#define I2C_MSGSTAT_RESTART 0x0022
|
||||
#define I2C_MSGSTAT_READ_BUSY 0x0023
|
||||
|
||||
//
|
||||
// Generic defines
|
||||
//
|
||||
#define I2C_TRUE 1
|
||||
#define I2C_FALSE 0
|
||||
#define I2C_YES 1
|
||||
#define I2C_NO 0
|
||||
#define I2C_DUMMY_BYTE 0
|
||||
|
||||
//
|
||||
// Structures
|
||||
//
|
||||
|
||||
//
|
||||
// I2C Message Structure
|
||||
//
|
||||
struct I2CMSG
|
||||
{
|
||||
Uint16 MsgStatus; // Word stating what state msg is in:
|
||||
// I2C_MSGCMD_INACTIVE = do not send msg
|
||||
// I2C_MSGCMD_BUSY = msg start has been sent,
|
||||
// awaiting stop
|
||||
// I2C_MSGCMD_SEND_WITHSTOP = command to send
|
||||
// master trans msg complete with a stop bit
|
||||
// I2C_MSGCMD_SEND_NOSTOP = command to send
|
||||
// master trans msg without the stop bit
|
||||
// I2C_MSGCMD_RESTART = command to send a restart
|
||||
// as a master receiver with a stop bit
|
||||
Uint16 SlaveAddress; // I2C address of slave msg is intended for
|
||||
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
|
||||
|
||||
//
|
||||
// EEPROM address of data associated with msg (high byte)
|
||||
//
|
||||
Uint16 MemoryHighAddr;
|
||||
|
||||
//
|
||||
// EEPROM address of data associated with msg (low byte)
|
||||
//
|
||||
Uint16 MemoryLowAddr;
|
||||
|
||||
//
|
||||
// Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to
|
||||
// the FIFO's
|
||||
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];
|
||||
};
|
||||
|
||||
|
||||
#endif // end of DSP2833x_I2C_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:39 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_XIntrupt.h
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interrupt Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_XINTRUPT_H
|
||||
#define DSP2833x_XINTRUPT_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct XINTCR_BITS {
|
||||
Uint16 ENABLE:1; // 0 enable/disable
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
|
||||
Uint16 rsvd2:12; //15:4 reserved
|
||||
};
|
||||
|
||||
union XINTCR_REG {
|
||||
Uint16 all;
|
||||
struct XINTCR_BITS bit;
|
||||
};
|
||||
|
||||
struct XNMICR_BITS {
|
||||
Uint16 ENABLE:1; // 0 enable/disable
|
||||
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
|
||||
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union XNMICR_REG {
|
||||
Uint16 all;
|
||||
struct XNMICR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// External Interrupt Register File
|
||||
//
|
||||
struct XINTRUPT_REGS {
|
||||
union XINTCR_REG XINT1CR;
|
||||
union XINTCR_REG XINT2CR;
|
||||
union XINTCR_REG XINT3CR;
|
||||
union XINTCR_REG XINT4CR;
|
||||
union XINTCR_REG XINT5CR;
|
||||
union XINTCR_REG XINT6CR;
|
||||
union XINTCR_REG XINT7CR;
|
||||
union XNMICR_REG XNMICR;
|
||||
Uint16 XINT1CTR;
|
||||
Uint16 XINT2CTR;
|
||||
Uint16 rsvd[5];
|
||||
Uint16 XNMICTR;
|
||||
};
|
||||
|
||||
//
|
||||
// External Interrupt References & Function Declarations
|
||||
//
|
||||
extern volatile struct XINTRUPT_REGS XIntruptRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_XINTF_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,291 @@
|
||||
// TI File $Revision: /main/11 $
|
||||
// Checkin $Date: May 12, 2008 14:30:08 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_GlobalPrototypes.h
|
||||
//
|
||||
// TITLE: Global prototypes for DSP2833x Examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_GLOBALPROTOTYPES_H
|
||||
#define DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// shared global function prototypes
|
||||
//
|
||||
extern void InitAdc(void);
|
||||
extern void DMAInitialize(void);
|
||||
|
||||
//
|
||||
// DMA Channel 1
|
||||
//
|
||||
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH1(void);
|
||||
|
||||
//
|
||||
// DMA Channel 2
|
||||
//
|
||||
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH2(void);
|
||||
|
||||
//
|
||||
// DMA Channel 3
|
||||
//
|
||||
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH3(void);
|
||||
|
||||
//
|
||||
// DMA Channel 4
|
||||
//
|
||||
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH4(void);
|
||||
|
||||
//
|
||||
// DMA Channel 5
|
||||
//
|
||||
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH5(void);
|
||||
|
||||
//
|
||||
// DMA Channel 6
|
||||
//
|
||||
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH6(void);
|
||||
|
||||
extern void InitPeripherals(void);
|
||||
#if DSP28_ECANA
|
||||
extern void InitECan(void);
|
||||
extern void InitECana(void);
|
||||
extern void InitECanGpio(void);
|
||||
extern void InitECanaGpio(void);
|
||||
#endif // endif DSP28_ECANA
|
||||
#if DSP28_ECANB
|
||||
extern void InitECanb(void);
|
||||
extern void InitECanbGpio(void);
|
||||
#endif // endif DSP28_ECANB
|
||||
extern void InitECap(void);
|
||||
extern void InitECapGpio(void);
|
||||
extern void InitECap1Gpio(void);
|
||||
extern void InitECap2Gpio(void);
|
||||
#if DSP28_ECAP3
|
||||
extern void InitECap3Gpio(void);
|
||||
#endif // endif DSP28_ECAP3
|
||||
#if DSP28_ECAP4
|
||||
extern void InitECap4Gpio(void);
|
||||
#endif // endif DSP28_ECAP4
|
||||
#if DSP28_ECAP5
|
||||
extern void InitECap5Gpio(void);
|
||||
#endif // endif DSP28_ECAP5
|
||||
#if DSP28_ECAP6
|
||||
extern void InitECap6Gpio(void);
|
||||
#endif // endif DSP28_ECAP6
|
||||
extern void InitEPwm(void);
|
||||
extern void InitEPwmGpio(void);
|
||||
extern void InitEPwm1Gpio(void);
|
||||
extern void InitEPwm2Gpio(void);
|
||||
extern void InitEPwm3Gpio(void);
|
||||
#if DSP28_EPWM4
|
||||
extern void InitEPwm4Gpio(void);
|
||||
#endif // endif DSP28_EPWM4
|
||||
#if DSP28_EPWM5
|
||||
extern void InitEPwm5Gpio(void);
|
||||
#endif // endif DSP28_EPWM5
|
||||
#if DSP28_EPWM6
|
||||
extern void InitEPwm6Gpio(void);
|
||||
#endif // endif DSP28_EPWM6
|
||||
#if DSP28_EQEP1
|
||||
extern void InitEQep(void);
|
||||
extern void InitEQepGpio(void);
|
||||
extern void InitEQep1Gpio(void);
|
||||
#endif // if DSP28_EQEP1
|
||||
#if DSP28_EQEP2
|
||||
extern void InitEQep2Gpio(void);
|
||||
#endif // endif DSP28_EQEP2
|
||||
extern void InitGpio(void);
|
||||
extern void InitI2CGpio(void);
|
||||
|
||||
extern void InitMcbsp(void);
|
||||
extern void InitMcbspa(void);
|
||||
extern void delay_loop(void);
|
||||
extern void InitMcbspaGpio(void);
|
||||
extern void InitMcbspa8bit(void);
|
||||
extern void InitMcbspa12bit(void);
|
||||
extern void InitMcbspa16bit(void);
|
||||
extern void InitMcbspa20bit(void);
|
||||
extern void InitMcbspa24bit(void);
|
||||
extern void InitMcbspa32bit(void);
|
||||
#if DSP28_MCBSPB
|
||||
extern void InitMcbspb(void);
|
||||
extern void InitMcbspbGpio(void);
|
||||
extern void InitMcbspb8bit(void);
|
||||
extern void InitMcbspb12bit(void);
|
||||
extern void InitMcbspb16bit(void);
|
||||
extern void InitMcbspb20bit(void);
|
||||
extern void InitMcbspb24bit(void);
|
||||
extern void InitMcbspb32bit(void);
|
||||
#endif // endif DSP28_MCBSPB
|
||||
|
||||
extern void InitPieCtrl(void);
|
||||
extern void InitPieVectTable(void);
|
||||
|
||||
extern void InitSci(void);
|
||||
extern void InitSciGpio(void);
|
||||
extern void InitSciaGpio(void);
|
||||
#if DSP28_SCIB
|
||||
extern void InitScibGpio(void);
|
||||
#endif // endif DSP28_SCIB
|
||||
#if DSP28_SCIC
|
||||
extern void InitScicGpio(void);
|
||||
#endif
|
||||
extern void InitSpi(void);
|
||||
extern void InitSpiGpio(void);
|
||||
extern void InitSpiaGpio(void);
|
||||
extern void InitSysCtrl(void);
|
||||
extern void InitTzGpio(void);
|
||||
extern void InitXIntrupt(void);
|
||||
extern void XintfInit(void);
|
||||
extern void InitXintf16Gpio();
|
||||
extern void InitXintf32Gpio();
|
||||
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
|
||||
extern void InitPeripheralClocks(void);
|
||||
extern void EnableInterrupts(void);
|
||||
extern void DSP28x_usDelay(Uint32 Count);
|
||||
extern void ADC_cal (void);
|
||||
#define KickDog ServiceDog // For compatiblity with previous versions
|
||||
extern void ServiceDog(void);
|
||||
extern void DisableDog(void);
|
||||
extern Uint16 CsmUnlock(void);
|
||||
|
||||
//
|
||||
// DSP28_DBGIER.asm
|
||||
//
|
||||
extern void SetDBGIER(Uint16 dbgier);
|
||||
|
||||
//
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
//
|
||||
extern void InitFlash(void);
|
||||
|
||||
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
|
||||
|
||||
//
|
||||
// External symbols created by the linker cmd file
|
||||
// DSP28 examples will use these to relocate code from one LOAD location
|
||||
// in either Flash or XINTF to a different RUN location in internal
|
||||
// RAM
|
||||
//
|
||||
extern Uint16 RamfuncsLoadStart;
|
||||
extern Uint16 RamfuncsLoadEnd;
|
||||
extern Uint16 RamfuncsRunStart;
|
||||
extern Uint16 RamfuncsLoadSize;
|
||||
|
||||
extern Uint16 XintffuncsLoadStart;
|
||||
extern Uint16 XintffuncsLoadEnd;
|
||||
extern Uint16 XintffuncsRunStart;
|
||||
extern Uint16 XintffuncsLoadSize;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,239 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: January 22, 2008 16:55:35 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Device.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEVICE_H
|
||||
#define DSP2833x_DEVICE_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define TARGET 1
|
||||
|
||||
//
|
||||
// User To Select Target Device
|
||||
//
|
||||
#define DSP28_28335 TARGET // Selects '28335/'28235
|
||||
#define DSP28_28334 0 // Selects '28334/'28234
|
||||
#define DSP28_28333 0 // Selects '28333/'
|
||||
#define DSP28_28332 0 // Selects '28332/'28232
|
||||
|
||||
//
|
||||
// Common CPU Definitions
|
||||
//
|
||||
extern cregister volatile unsigned int IFR;
|
||||
extern cregister volatile unsigned int IER;
|
||||
|
||||
#define EINT asm(" clrc INTM")
|
||||
#define DINT asm(" setc INTM")
|
||||
#define ERTM asm(" clrc DBGM")
|
||||
#define DRTM asm(" setc DBGM")
|
||||
#define EALLOW asm(" EALLOW")
|
||||
#define EDIS asm(" EDIS")
|
||||
#define ESTOP0 asm(" ESTOP0")
|
||||
|
||||
#define M_INT1 0x0001
|
||||
#define M_INT2 0x0002
|
||||
#define M_INT3 0x0004
|
||||
#define M_INT4 0x0008
|
||||
#define M_INT5 0x0010
|
||||
#define M_INT6 0x0020
|
||||
#define M_INT7 0x0040
|
||||
#define M_INT8 0x0080
|
||||
#define M_INT9 0x0100
|
||||
#define M_INT10 0x0200
|
||||
#define M_INT11 0x0400
|
||||
#define M_INT12 0x0800
|
||||
#define M_INT13 0x1000
|
||||
#define M_INT14 0x2000
|
||||
#define M_DLOG 0x4000
|
||||
#define M_RTOS 0x8000
|
||||
|
||||
#define BIT0 0x0001
|
||||
#define BIT1 0x0002
|
||||
#define BIT2 0x0004
|
||||
#define BIT3 0x0008
|
||||
#define BIT4 0x0010
|
||||
#define BIT5 0x0020
|
||||
#define BIT6 0x0040
|
||||
#define BIT7 0x0080
|
||||
#define BIT8 0x0100
|
||||
#define BIT9 0x0200
|
||||
#define BIT10 0x0400
|
||||
#define BIT11 0x0800
|
||||
#define BIT12 0x1000
|
||||
#define BIT13 0x2000
|
||||
#define BIT14 0x4000
|
||||
#define BIT15 0x8000
|
||||
|
||||
//
|
||||
// For Portability, User Is Recommended To Use Following Data Type Size
|
||||
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
|
||||
//
|
||||
#ifndef DSP28_DATA_TYPES
|
||||
#define DSP28_DATA_TYPES
|
||||
typedef int int16;
|
||||
typedef long int32;
|
||||
typedef long long int64;
|
||||
typedef unsigned int Uint16;
|
||||
typedef unsigned long Uint32;
|
||||
typedef unsigned long long Uint64;
|
||||
typedef float float32;
|
||||
typedef long double float64;
|
||||
#endif
|
||||
|
||||
//
|
||||
// Included Peripheral Header Files
|
||||
//
|
||||
#include "DSP2833x_Adc.h" // ADC Registers
|
||||
#include "DSP2833x_DevEmu.h" // Device Emulation Registers
|
||||
#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers
|
||||
#include "DSP2833x_ECan.h" // Enhanced eCAN Registers
|
||||
#include "DSP2833x_ECap.h" // Enhanced Capture
|
||||
#include "DSP2833x_DMA.h" // DMA Registers
|
||||
#include "DSP2833x_EPwm.h" // Enhanced PWM
|
||||
#include "DSP2833x_EQep.h" // Enhanced QEP
|
||||
#include "DSP2833x_Gpio.h" // General Purpose I/O Registers
|
||||
#include "DSP2833x_I2c.h" // I2C Registers
|
||||
#include "DSP2833x_Mcbsp.h" // McBSP
|
||||
#include "DSP2833x_PieCtrl.h" // PIE Control Registers
|
||||
#include "DSP2833x_PieVect.h" // PIE Vector Table
|
||||
#include "DSP2833x_Spi.h" // SPI Registers
|
||||
#include "DSP2833x_Sci.h" // SCI Registers
|
||||
#include "DSP2833x_SysCtrl.h" // System Control/Power Modes
|
||||
#include "DSP2833x_XIntrupt.h" // External Interrupts
|
||||
#include "DSP2833x_Xintf.h" // XINTF External Interface
|
||||
|
||||
#if DSP28_28335 || DSP28_28333
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 1
|
||||
#define DSP28_ECAP6 1
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 1
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 1
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28335 || DSP28_28333
|
||||
|
||||
#if DSP28_28334
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 0
|
||||
#define DSP28_ECAP6 0
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 1
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 1
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28334
|
||||
|
||||
#if DSP28_28332
|
||||
#define DSP28_EPWM1 1
|
||||
#define DSP28_EPWM2 1
|
||||
#define DSP28_EPWM3 1
|
||||
#define DSP28_EPWM4 1
|
||||
#define DSP28_EPWM5 1
|
||||
#define DSP28_EPWM6 1
|
||||
#define DSP28_ECAP1 1
|
||||
#define DSP28_ECAP2 1
|
||||
#define DSP28_ECAP3 1
|
||||
#define DSP28_ECAP4 1
|
||||
#define DSP28_ECAP5 0
|
||||
#define DSP28_ECAP6 0
|
||||
#define DSP28_EQEP1 1
|
||||
#define DSP28_EQEP2 1
|
||||
#define DSP28_ECANA 1
|
||||
#define DSP28_ECANB 1
|
||||
#define DSP28_MCBSPA 1
|
||||
#define DSP28_MCBSPB 0
|
||||
#define DSP28_SPIA 1
|
||||
#define DSP28_SCIA 1
|
||||
#define DSP28_SCIB 1
|
||||
#define DSP28_SCIC 0
|
||||
#define DSP28_I2CA 1
|
||||
#endif // end DSP28_28332
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEVICE_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,179 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:07 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_ECap.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_ECAP_H
|
||||
#define DSP2833x_ECAP_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Capture control register 1 bit definitions
|
||||
//
|
||||
struct ECCTL1_BITS { // bits description
|
||||
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
|
||||
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
|
||||
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
|
||||
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
|
||||
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
|
||||
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
|
||||
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
|
||||
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
|
||||
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap
|
||||
// Event
|
||||
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union ECCTL1_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// In V1.1 the STOPVALUE bit field was changed to
|
||||
// STOP_WRAP. This correlated to a silicon change from
|
||||
// F2833x Rev 0 to Rev A.
|
||||
//
|
||||
|
||||
//
|
||||
// Capture control register 2 bit definitions
|
||||
//
|
||||
struct ECCTL2_BITS { // bits description
|
||||
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
|
||||
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
|
||||
Uint16 REARM:1; // 3 One-shot re-arm
|
||||
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
|
||||
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
|
||||
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
|
||||
Uint16 SWSYNC:1; // 8 SW forced counter sync
|
||||
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
|
||||
Uint16 APWMPOL:1; // 10 APWM output polarity select
|
||||
Uint16 rsvd1:5; // 15:11
|
||||
};
|
||||
|
||||
union ECCTL2_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// ECAP interrupt enable register bit definitions
|
||||
//
|
||||
struct ECEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
|
||||
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
|
||||
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ECEINT_REG {
|
||||
Uint16 all;
|
||||
struct ECEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// ECAP interrupt flag register bit definitions
|
||||
//
|
||||
struct ECFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global Flag
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
|
||||
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
|
||||
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
|
||||
Uint16 rsvd2:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ECFLG_REG {
|
||||
Uint16 all;
|
||||
struct ECFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct ECAP_REGS {
|
||||
Uint32 TSCTR; // Time stamp counter
|
||||
Uint32 CTRPHS; // Counter phase
|
||||
Uint32 CAP1; // Capture 1
|
||||
Uint32 CAP2; // Capture 2
|
||||
Uint32 CAP3; // Capture 3
|
||||
Uint32 CAP4; // Capture 4
|
||||
Uint16 rsvd1[8]; // reserved
|
||||
union ECCTL1_REG ECCTL1; // Capture Control Reg 1
|
||||
union ECCTL2_REG ECCTL2; // Capture Control Reg 2
|
||||
union ECEINT_REG ECEINT; // ECAP interrupt enable
|
||||
union ECFLG_REG ECFLG; // ECAP interrupt flags
|
||||
union ECFLG_REG ECCLR; // ECAP interrupt clear
|
||||
union ECEINT_REG ECFRC; // ECAP interrupt force
|
||||
Uint16 rsvd2[6]; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct ECAP_REGS ECap1Regs;
|
||||
extern volatile struct ECAP_REGS ECap2Regs;
|
||||
extern volatile struct ECAP_REGS ECap3Regs;
|
||||
extern volatile struct ECAP_REGS ECap4Regs;
|
||||
extern volatile struct ECAP_REGS ECap5Regs;
|
||||
extern volatile struct ECAP_REGS ECap6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_ECAP_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,265 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 16, 2007 09:00:21 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieVect.h
|
||||
//
|
||||
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_PIE_VECT_H
|
||||
#define DSP2833x_PIE_VECT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// PIE Interrupt Vector Table Definition
|
||||
//
|
||||
|
||||
//
|
||||
// Typedef used to create a user type called PINT (pointer to interrupt)
|
||||
//
|
||||
typedef interrupt void(*PINT)(void);
|
||||
|
||||
//
|
||||
// Vector Table Define
|
||||
//
|
||||
struct PIE_VECT_TABLE {
|
||||
//
|
||||
// Reset is never fetched from this table. It will always be fetched from
|
||||
// 0x3FFFC0 in boot ROM
|
||||
//
|
||||
PINT PIE1_RESERVED;
|
||||
PINT PIE2_RESERVED;
|
||||
PINT PIE3_RESERVED;
|
||||
PINT PIE4_RESERVED;
|
||||
PINT PIE5_RESERVED;
|
||||
PINT PIE6_RESERVED;
|
||||
PINT PIE7_RESERVED;
|
||||
PINT PIE8_RESERVED;
|
||||
PINT PIE9_RESERVED;
|
||||
PINT PIE10_RESERVED;
|
||||
PINT PIE11_RESERVED;
|
||||
PINT PIE12_RESERVED;
|
||||
PINT PIE13_RESERVED;
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts
|
||||
//
|
||||
PINT XINT13; // XINT13 / CPU-Timer1
|
||||
PINT TINT2; // CPU-Timer2
|
||||
PINT DATALOG; // Datalogging interrupt
|
||||
PINT RTOSINT; // RTOS interrupt
|
||||
PINT EMUINT; // Emulation interrupt
|
||||
PINT XNMI; // Non-maskable interrupt
|
||||
PINT ILLEGAL; // Illegal operation TRAP
|
||||
PINT USER1; // User Defined trap 1
|
||||
PINT USER2; // User Defined trap 2
|
||||
PINT USER3; // User Defined trap 3
|
||||
PINT USER4; // User Defined trap 4
|
||||
PINT USER5; // User Defined trap 5
|
||||
PINT USER6; // User Defined trap 6
|
||||
PINT USER7; // User Defined trap 7
|
||||
PINT USER8; // User Defined trap 8
|
||||
PINT USER9; // User Defined trap 9
|
||||
PINT USER10; // User Defined trap 10
|
||||
PINT USER11; // User Defined trap 11
|
||||
PINT USER12; // User Defined trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SEQ1INT;
|
||||
PINT SEQ2INT;
|
||||
PINT rsvd1_3;
|
||||
PINT XINT1;
|
||||
PINT XINT2;
|
||||
PINT ADCINT; // ADC
|
||||
PINT TINT0; // Timer 0
|
||||
PINT WAKEINT; // WD
|
||||
|
||||
//
|
||||
// Group 2 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EPWM1_TZINT; // EPWM-1
|
||||
PINT EPWM2_TZINT; // EPWM-2
|
||||
PINT EPWM3_TZINT; // EPWM-3
|
||||
PINT EPWM4_TZINT; // EPWM-4
|
||||
PINT EPWM5_TZINT; // EPWM-5
|
||||
PINT EPWM6_TZINT; // EPWM-6
|
||||
PINT rsvd2_7;
|
||||
PINT rsvd2_8;
|
||||
|
||||
//
|
||||
// Group 3 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EPWM1_INT; // EPWM-1
|
||||
PINT EPWM2_INT; // EPWM-2
|
||||
PINT EPWM3_INT; // EPWM-3
|
||||
PINT EPWM4_INT; // EPWM-4
|
||||
PINT EPWM5_INT; // EPWM-5
|
||||
PINT EPWM6_INT; // EPWM-6
|
||||
PINT rsvd3_7;
|
||||
PINT rsvd3_8;
|
||||
|
||||
//
|
||||
// Group 4 PIE Peripheral Vectors
|
||||
//
|
||||
PINT ECAP1_INT; // ECAP-1
|
||||
PINT ECAP2_INT; // ECAP-2
|
||||
PINT ECAP3_INT; // ECAP-3
|
||||
PINT ECAP4_INT; // ECAP-4
|
||||
PINT ECAP5_INT; // ECAP-5
|
||||
PINT ECAP6_INT; // ECAP-6
|
||||
PINT rsvd4_7;
|
||||
PINT rsvd4_8;
|
||||
|
||||
//
|
||||
// Group 5 PIE Peripheral Vectors
|
||||
//
|
||||
PINT EQEP1_INT; // EQEP-1
|
||||
PINT EQEP2_INT; // EQEP-2
|
||||
PINT rsvd5_3;
|
||||
PINT rsvd5_4;
|
||||
PINT rsvd5_5;
|
||||
PINT rsvd5_6;
|
||||
PINT rsvd5_7;
|
||||
PINT rsvd5_8;
|
||||
|
||||
//
|
||||
// Group 6 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SPIRXINTA; // SPI-A
|
||||
PINT SPITXINTA; // SPI-A
|
||||
PINT MRINTB; // McBSP-B
|
||||
PINT MXINTB; // McBSP-B
|
||||
PINT MRINTA; // McBSP-A
|
||||
PINT MXINTA; // McBSP-A
|
||||
PINT rsvd6_7;
|
||||
PINT rsvd6_8;
|
||||
|
||||
//
|
||||
// Group 7 PIE Peripheral Vectors
|
||||
//
|
||||
PINT DINTCH1; // DMA
|
||||
PINT DINTCH2; // DMA
|
||||
PINT DINTCH3; // DMA
|
||||
PINT DINTCH4; // DMA
|
||||
PINT DINTCH5; // DMA
|
||||
PINT DINTCH6; // DMA
|
||||
PINT rsvd7_7;
|
||||
PINT rsvd7_8;
|
||||
|
||||
//
|
||||
// Group 8 PIE Peripheral Vectors
|
||||
//
|
||||
PINT I2CINT1A; // I2C-A
|
||||
PINT I2CINT2A; // I2C-A
|
||||
PINT rsvd8_3;
|
||||
PINT rsvd8_4;
|
||||
PINT SCIRXINTC; // SCI-C
|
||||
PINT SCITXINTC; // SCI-C
|
||||
PINT rsvd8_7;
|
||||
PINT rsvd8_8;
|
||||
|
||||
//
|
||||
// Group 9 PIE Peripheral Vectors
|
||||
//
|
||||
PINT SCIRXINTA; // SCI-A
|
||||
PINT SCITXINTA; // SCI-A
|
||||
PINT SCIRXINTB; // SCI-B
|
||||
PINT SCITXINTB; // SCI-B
|
||||
PINT ECAN0INTA; // eCAN-A
|
||||
PINT ECAN1INTA; // eCAN-A
|
||||
PINT ECAN0INTB; // eCAN-B
|
||||
PINT ECAN1INTB; // eCAN-B
|
||||
|
||||
//
|
||||
// Group 10 PIE Peripheral Vectors
|
||||
//
|
||||
PINT rsvd10_1;
|
||||
PINT rsvd10_2;
|
||||
PINT rsvd10_3;
|
||||
PINT rsvd10_4;
|
||||
PINT rsvd10_5;
|
||||
PINT rsvd10_6;
|
||||
PINT rsvd10_7;
|
||||
PINT rsvd10_8;
|
||||
|
||||
//
|
||||
// Group 11 PIE Peripheral Vectors
|
||||
//
|
||||
PINT rsvd11_1;
|
||||
PINT rsvd11_2;
|
||||
PINT rsvd11_3;
|
||||
PINT rsvd11_4;
|
||||
PINT rsvd11_5;
|
||||
PINT rsvd11_6;
|
||||
PINT rsvd11_7;
|
||||
PINT rsvd11_8;
|
||||
|
||||
//
|
||||
// Group 12 PIE Peripheral Vectors
|
||||
//
|
||||
PINT XINT3; // External interrupt
|
||||
PINT XINT4;
|
||||
PINT XINT5;
|
||||
PINT XINT6;
|
||||
PINT XINT7;
|
||||
PINT rsvd12_6;
|
||||
PINT LVF; // Latched overflow
|
||||
PINT LUF; // Latched underflow
|
||||
};
|
||||
|
||||
//
|
||||
// PIE Interrupt Vector Table External References & Function Declarations
|
||||
//
|
||||
extern volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_PIE_VECT_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,493 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: November 15, 2007 09:58:53 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Gpio.h
|
||||
//
|
||||
// TITLE: DSP2833x General Purpose I/O Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_GPIO_H
|
||||
#define DSP2833x_GPIO_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// GPIO A control register bit definitions
|
||||
//
|
||||
struct GPACTRL_BITS { // bits description
|
||||
Uint16 QUALPRD0:8; // 7:0 Qual period
|
||||
Uint16 QUALPRD1:8; // 15:8 Qual period
|
||||
Uint16 QUALPRD2:8; // 23:16 Qual period
|
||||
Uint16 QUALPRD3:8; // 31:24 Qual period
|
||||
};
|
||||
|
||||
union GPACTRL_REG {
|
||||
Uint32 all;
|
||||
struct GPACTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO B control register bit definitions
|
||||
//
|
||||
struct GPBCTRL_BITS { // bits description
|
||||
Uint16 QUALPRD0:8; // 7:0 Qual period
|
||||
Uint16 QUALPRD1:8; // 15:8 Qual period
|
||||
Uint16 QUALPRD2:8; // 23:16 Qual period
|
||||
Uint16 QUALPRD3:8; // 31:24
|
||||
};
|
||||
|
||||
union GPBCTRL_REG {
|
||||
Uint32 all;
|
||||
struct GPBCTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO A Qual/MUX select register bit definitions
|
||||
//
|
||||
struct GPA1_BITS { // bits description
|
||||
Uint16 GPIO0:2; // 1:0 GPIO0
|
||||
Uint16 GPIO1:2; // 3:2 GPIO1
|
||||
Uint16 GPIO2:2; // 5:4 GPIO2
|
||||
Uint16 GPIO3:2; // 7:6 GPIO3
|
||||
Uint16 GPIO4:2; // 9:8 GPIO4
|
||||
Uint16 GPIO5:2; // 11:10 GPIO5
|
||||
Uint16 GPIO6:2; // 13:12 GPIO6
|
||||
Uint16 GPIO7:2; // 15:14 GPIO7
|
||||
Uint16 GPIO8:2; // 17:16 GPIO8
|
||||
Uint16 GPIO9:2; // 19:18 GPIO9
|
||||
Uint16 GPIO10:2; // 21:20 GPIO10
|
||||
Uint16 GPIO11:2; // 23:22 GPIO11
|
||||
Uint16 GPIO12:2; // 25:24 GPIO12
|
||||
Uint16 GPIO13:2; // 27:26 GPIO13
|
||||
Uint16 GPIO14:2; // 29:28 GPIO14
|
||||
Uint16 GPIO15:2; // 31:30 GPIO15
|
||||
};
|
||||
|
||||
struct GPA2_BITS { // bits description
|
||||
Uint16 GPIO16:2; // 1:0 GPIO16
|
||||
Uint16 GPIO17:2; // 3:2 GPIO17
|
||||
Uint16 GPIO18:2; // 5:4 GPIO18
|
||||
Uint16 GPIO19:2; // 7:6 GPIO19
|
||||
Uint16 GPIO20:2; // 9:8 GPIO20
|
||||
Uint16 GPIO21:2; // 11:10 GPIO21
|
||||
Uint16 GPIO22:2; // 13:12 GPIO22
|
||||
Uint16 GPIO23:2; // 15:14 GPIO23
|
||||
Uint16 GPIO24:2; // 17:16 GPIO24
|
||||
Uint16 GPIO25:2; // 19:18 GPIO25
|
||||
Uint16 GPIO26:2; // 21:20 GPIO26
|
||||
Uint16 GPIO27:2; // 23:22 GPIO27
|
||||
Uint16 GPIO28:2; // 25:24 GPIO28
|
||||
Uint16 GPIO29:2; // 27:26 GPIO29
|
||||
Uint16 GPIO30:2; // 29:28 GPIO30
|
||||
Uint16 GPIO31:2; // 31:30 GPIO31
|
||||
};
|
||||
|
||||
struct GPB1_BITS { // bits description
|
||||
Uint16 GPIO32:2; // 1:0 GPIO32
|
||||
Uint16 GPIO33:2; // 3:2 GPIO33
|
||||
Uint16 GPIO34:2; // 5:4 GPIO34
|
||||
Uint16 GPIO35:2; // 7:6 GPIO35
|
||||
Uint16 GPIO36:2; // 9:8 GPIO36
|
||||
Uint16 GPIO37:2; // 11:10 GPIO37
|
||||
Uint16 GPIO38:2; // 13:12 GPIO38
|
||||
Uint16 GPIO39:2; // 15:14 GPIO39
|
||||
Uint16 GPIO40:2; // 17:16 GPIO40
|
||||
Uint16 GPIO41:2; // 19:16 GPIO41
|
||||
Uint16 GPIO42:2; // 21:20 GPIO42
|
||||
Uint16 GPIO43:2; // 23:22 GPIO43
|
||||
Uint16 GPIO44:2; // 25:24 GPIO44
|
||||
Uint16 GPIO45:2; // 27:26 GPIO45
|
||||
Uint16 GPIO46:2; // 29:28 GPIO46
|
||||
Uint16 GPIO47:2; // 31:30 GPIO47
|
||||
};
|
||||
|
||||
struct GPB2_BITS { // bits description
|
||||
Uint16 GPIO48:2; // 1:0 GPIO48
|
||||
Uint16 GPIO49:2; // 3:2 GPIO49
|
||||
Uint16 GPIO50:2; // 5:4 GPIO50
|
||||
Uint16 GPIO51:2; // 7:6 GPIO51
|
||||
Uint16 GPIO52:2; // 9:8 GPIO52
|
||||
Uint16 GPIO53:2; // 11:10 GPIO53
|
||||
Uint16 GPIO54:2; // 13:12 GPIO54
|
||||
Uint16 GPIO55:2; // 15:14 GPIO55
|
||||
Uint16 GPIO56:2; // 17:16 GPIO56
|
||||
Uint16 GPIO57:2; // 19:18 GPIO57
|
||||
Uint16 GPIO58:2; // 21:20 GPIO58
|
||||
Uint16 GPIO59:2; // 23:22 GPIO59
|
||||
Uint16 GPIO60:2; // 25:24 GPIO60
|
||||
Uint16 GPIO61:2; // 27:26 GPIO61
|
||||
Uint16 GPIO62:2; // 29:28 GPIO62
|
||||
Uint16 GPIO63:2; // 31:30 GPIO63
|
||||
};
|
||||
|
||||
struct GPC1_BITS { // bits description
|
||||
Uint16 GPIO64:2; // 1:0 GPIO64
|
||||
Uint16 GPIO65:2; // 3:2 GPIO65
|
||||
Uint16 GPIO66:2; // 5:4 GPIO66
|
||||
Uint16 GPIO67:2; // 7:6 GPIO67
|
||||
Uint16 GPIO68:2; // 9:8 GPIO68
|
||||
Uint16 GPIO69:2; // 11:10 GPIO69
|
||||
Uint16 GPIO70:2; // 13:12 GPIO70
|
||||
Uint16 GPIO71:2; // 15:14 GPIO71
|
||||
Uint16 GPIO72:2; // 17:16 GPIO72
|
||||
Uint16 GPIO73:2; // 19:18 GPIO73
|
||||
Uint16 GPIO74:2; // 21:20 GPIO74
|
||||
Uint16 GPIO75:2; // 23:22 GPIO75
|
||||
Uint16 GPIO76:2; // 25:24 GPIO76
|
||||
Uint16 GPIO77:2; // 27:26 GPIO77
|
||||
Uint16 GPIO78:2; // 29:28 GPIO78
|
||||
Uint16 GPIO79:2; // 31:30 GPIO79
|
||||
};
|
||||
|
||||
struct GPC2_BITS { // bits description
|
||||
Uint16 GPIO80:2; // 1:0 GPIO80
|
||||
Uint16 GPIO81:2; // 3:2 GPIO81
|
||||
Uint16 GPIO82:2; // 5:4 GPIO82
|
||||
Uint16 GPIO83:2; // 7:6 GPIO83
|
||||
Uint16 GPIO84:2; // 9:8 GPIO84
|
||||
Uint16 GPIO85:2; // 11:10 GPIO85
|
||||
Uint16 GPIO86:2; // 13:12 GPIO86
|
||||
Uint16 GPIO87:2; // 15:14 GPIO87
|
||||
Uint16 rsvd:16; // 31:16 reserved
|
||||
};
|
||||
|
||||
union GPA1_REG {
|
||||
Uint32 all;
|
||||
struct GPA1_BITS bit;
|
||||
};
|
||||
|
||||
union GPA2_REG {
|
||||
Uint32 all;
|
||||
struct GPA2_BITS bit;
|
||||
};
|
||||
|
||||
union GPB1_REG {
|
||||
Uint32 all;
|
||||
struct GPB1_BITS bit;
|
||||
};
|
||||
|
||||
union GPB2_REG {
|
||||
Uint32 all;
|
||||
struct GPB2_BITS bit;
|
||||
};
|
||||
|
||||
union GPC1_REG {
|
||||
Uint32 all;
|
||||
struct GPC1_BITS bit;
|
||||
};
|
||||
|
||||
union GPC2_REG {
|
||||
Uint32 all;
|
||||
struct GPC2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions
|
||||
//
|
||||
struct GPADAT_BITS { // bits description
|
||||
Uint16 GPIO0:1; // 0 GPIO0
|
||||
Uint16 GPIO1:1; // 1 GPIO1
|
||||
Uint16 GPIO2:1; // 2 GPIO2
|
||||
Uint16 GPIO3:1; // 3 GPIO3
|
||||
Uint16 GPIO4:1; // 4 GPIO4
|
||||
Uint16 GPIO5:1; // 5 GPIO5
|
||||
Uint16 GPIO6:1; // 6 GPIO6
|
||||
Uint16 GPIO7:1; // 7 GPIO7
|
||||
Uint16 GPIO8:1; // 8 GPIO8
|
||||
Uint16 GPIO9:1; // 9 GPIO9
|
||||
Uint16 GPIO10:1; // 10 GPIO10
|
||||
Uint16 GPIO11:1; // 11 GPIO11
|
||||
Uint16 GPIO12:1; // 12 GPIO12
|
||||
Uint16 GPIO13:1; // 13 GPIO13
|
||||
Uint16 GPIO14:1; // 14 GPIO14
|
||||
Uint16 GPIO15:1; // 15 GPIO15
|
||||
Uint16 GPIO16:1; // 16 GPIO16
|
||||
Uint16 GPIO17:1; // 17 GPIO17
|
||||
Uint16 GPIO18:1; // 18 GPIO18
|
||||
Uint16 GPIO19:1; // 19 GPIO19
|
||||
Uint16 GPIO20:1; // 20 GPIO20
|
||||
Uint16 GPIO21:1; // 21 GPIO21
|
||||
Uint16 GPIO22:1; // 22 GPIO22
|
||||
Uint16 GPIO23:1; // 23 GPIO23
|
||||
Uint16 GPIO24:1; // 24 GPIO24
|
||||
Uint16 GPIO25:1; // 25 GPIO25
|
||||
Uint16 GPIO26:1; // 26 GPIO26
|
||||
Uint16 GPIO27:1; // 27 GPIO27
|
||||
Uint16 GPIO28:1; // 28 GPIO28
|
||||
Uint16 GPIO29:1; // 29 GPIO29
|
||||
Uint16 GPIO30:1; // 30 GPIO30
|
||||
Uint16 GPIO31:1; // 31 GPIO31
|
||||
};
|
||||
|
||||
struct GPBDAT_BITS { // bits description
|
||||
Uint16 GPIO32:1; // 0 GPIO32
|
||||
Uint16 GPIO33:1; // 1 GPIO33
|
||||
Uint16 GPIO34:1; // 2 GPIO34
|
||||
Uint16 GPIO35:1; // 3 GPIO35
|
||||
Uint16 GPIO36:1; // 4 GPIO36
|
||||
Uint16 GPIO37:1; // 5 GPIO37
|
||||
Uint16 GPIO38:1; // 6 GPIO38
|
||||
Uint16 GPIO39:1; // 7 GPIO39
|
||||
Uint16 GPIO40:1; // 8 GPIO40
|
||||
Uint16 GPIO41:1; // 9 GPIO41
|
||||
Uint16 GPIO42:1; // 10 GPIO42
|
||||
Uint16 GPIO43:1; // 11 GPIO43
|
||||
Uint16 GPIO44:1; // 12 GPIO44
|
||||
Uint16 GPIO45:1; // 13 GPIO45
|
||||
Uint16 GPIO46:1; // 14 GPIO46
|
||||
Uint16 GPIO47:1; // 15 GPIO47
|
||||
Uint16 GPIO48:1; // 16 GPIO48
|
||||
Uint16 GPIO49:1; // 17 GPIO49
|
||||
Uint16 GPIO50:1; // 18 GPIO50
|
||||
Uint16 GPIO51:1; // 19 GPIO51
|
||||
Uint16 GPIO52:1; // 20 GPIO52
|
||||
Uint16 GPIO53:1; // 21 GPIO53
|
||||
Uint16 GPIO54:1; // 22 GPIO54
|
||||
Uint16 GPIO55:1; // 23 GPIO55
|
||||
Uint16 GPIO56:1; // 24 GPIO56
|
||||
Uint16 GPIO57:1; // 25 GPIO57
|
||||
Uint16 GPIO58:1; // 26 GPIO58
|
||||
Uint16 GPIO59:1; // 27 GPIO59
|
||||
Uint16 GPIO60:1; // 28 GPIO60
|
||||
Uint16 GPIO61:1; // 29 GPIO61
|
||||
Uint16 GPIO62:1; // 30 GPIO62
|
||||
Uint16 GPIO63:1; // 31 GPIO63
|
||||
};
|
||||
|
||||
struct GPCDAT_BITS { // bits description
|
||||
Uint16 GPIO64:1; // 0 GPIO64
|
||||
Uint16 GPIO65:1; // 1 GPIO65
|
||||
Uint16 GPIO66:1; // 2 GPIO66
|
||||
Uint16 GPIO67:1; // 3 GPIO67
|
||||
Uint16 GPIO68:1; // 4 GPIO68
|
||||
Uint16 GPIO69:1; // 5 GPIO69
|
||||
Uint16 GPIO70:1; // 6 GPIO70
|
||||
Uint16 GPIO71:1; // 7 GPIO71
|
||||
Uint16 GPIO72:1; // 8 GPIO72
|
||||
Uint16 GPIO73:1; // 9 GPIO73
|
||||
Uint16 GPIO74:1; // 10 GPIO74
|
||||
Uint16 GPIO75:1; // 11 GPIO75
|
||||
Uint16 GPIO76:1; // 12 GPIO76
|
||||
Uint16 GPIO77:1; // 13 GPIO77
|
||||
Uint16 GPIO78:1; // 14 GPIO78
|
||||
Uint16 GPIO79:1; // 15 GPIO79
|
||||
Uint16 GPIO80:1; // 16 GPIO80
|
||||
Uint16 GPIO81:1; // 17 GPIO81
|
||||
Uint16 GPIO82:1; // 18 GPIO82
|
||||
Uint16 GPIO83:1; // 19 GPIO83
|
||||
Uint16 GPIO84:1; // 20 GPIO84
|
||||
Uint16 GPIO85:1; // 21 GPIO85
|
||||
Uint16 GPIO86:1; // 22 GPIO86
|
||||
Uint16 GPIO87:1; // 23 GPIO87
|
||||
Uint16 rsvd1:8; // 31:24 reserved
|
||||
};
|
||||
|
||||
union GPADAT_REG {
|
||||
Uint32 all;
|
||||
struct GPADAT_BITS bit;
|
||||
};
|
||||
|
||||
union GPBDAT_REG {
|
||||
Uint32 all;
|
||||
struct GPBDAT_BITS bit;
|
||||
};
|
||||
|
||||
union GPCDAT_REG {
|
||||
Uint32 all;
|
||||
struct GPCDAT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// GPIO Xint1/XINT2/XNMI select register bit definitions
|
||||
//
|
||||
struct GPIOXINT_BITS { // bits description
|
||||
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union GPIOXINT_REG {
|
||||
Uint16 all;
|
||||
struct GPIOXINT_BITS bit;
|
||||
};
|
||||
|
||||
struct GPIO_CTRL_REGS {
|
||||
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO A Qualifier Select 1 Register (GPIO0 to 15)
|
||||
//
|
||||
union GPA1_REG GPAQSEL1;
|
||||
|
||||
//
|
||||
// GPIO A Qualifier Select 2 Register (GPIO16 to 31)
|
||||
//
|
||||
union GPA2_REG GPAQSEL2;
|
||||
|
||||
//
|
||||
// GPIO A Mux 1 Register (GPIO0 to 15)
|
||||
//
|
||||
union GPA1_REG GPAMUX1;
|
||||
|
||||
//
|
||||
// GPIO A Mux 2 Register (GPIO16 to 31)
|
||||
//
|
||||
union GPA2_REG GPAMUX2;
|
||||
|
||||
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO A Pull Up Disable Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPAPUD;
|
||||
|
||||
Uint32 rsvd1;
|
||||
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO B Qualifier Select 1 Register (GPIO32 to 47)
|
||||
//
|
||||
union GPB1_REG GPBQSEL1;
|
||||
|
||||
//
|
||||
// GPIO B Qualifier Select 2 Register (GPIO48 to 63)
|
||||
//
|
||||
union GPB2_REG GPBQSEL2;
|
||||
|
||||
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
|
||||
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
|
||||
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO B Pull Up Disable Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBPUD;
|
||||
|
||||
Uint16 rsvd2[8];
|
||||
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
|
||||
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
|
||||
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
|
||||
|
||||
//
|
||||
// GPIO C Pull Up Disable Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCPUD;
|
||||
};
|
||||
|
||||
struct GPIO_DATA_REGS {
|
||||
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
|
||||
|
||||
//
|
||||
// GPIO Data Set Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPASET;
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPACLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO0 to 31)
|
||||
//
|
||||
union GPADAT_REG GPATOGGLE;
|
||||
|
||||
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
|
||||
|
||||
//
|
||||
// GPIO Data Set Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBSET;
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBCLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO32 to 63)
|
||||
//
|
||||
union GPBDAT_REG GPBTOGGLE;
|
||||
|
||||
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
|
||||
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
|
||||
|
||||
//
|
||||
// GPIO Data Clear Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCCLEAR;
|
||||
|
||||
//
|
||||
// GPIO Data Toggle Register (GPIO64 to 95)
|
||||
//
|
||||
union GPCDAT_REG GPCTOGGLE;
|
||||
Uint16 rsvd1[8];
|
||||
};
|
||||
|
||||
struct GPIO_INT_REGS {
|
||||
union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection
|
||||
union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection
|
||||
union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
|
||||
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
|
||||
extern volatile struct GPIO_INT_REGS GpioIntRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_GPIO_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,252 @@
|
||||
#ifndef SOURCE_MAIN_H_
|
||||
#define SOURCE_MAIN_H_
|
||||
|
||||
#include <String.h>
|
||||
#include "DSP28x_Project.h"
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "State.h"
|
||||
#include "Oper.h"
|
||||
#include "Display.h"
|
||||
#include "Comm.h"
|
||||
|
||||
#define AUX_TEST
|
||||
|
||||
#define true (1U)
|
||||
#define false (0U)
|
||||
|
||||
// Key Input Port (Lo Active)
|
||||
#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active
|
||||
#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active
|
||||
#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active
|
||||
#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active
|
||||
#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active
|
||||
#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active
|
||||
#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active
|
||||
#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active
|
||||
|
||||
// Read ChipSelect State
|
||||
#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active
|
||||
#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active
|
||||
#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active
|
||||
#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active
|
||||
#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active
|
||||
#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active
|
||||
#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active
|
||||
|
||||
// Active Read From ECU
|
||||
#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active
|
||||
#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active
|
||||
#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active
|
||||
#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active
|
||||
|
||||
// Fail-Safe Enable(ECU HW Emergency)
|
||||
#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active
|
||||
|
||||
// Auxiliary Read all
|
||||
#define STATUS_BIT_HEATER (0)
|
||||
#define STATUS_BIT_GLOW (1)
|
||||
#define STATUS_BIT_SOLENOID (2)
|
||||
#define STATUS_BIT_FUEL (3)
|
||||
#define STATUS_BIT_COOLANT (4)
|
||||
#define STATUS_BIT_FAN1 (5)
|
||||
#define STATUS_BIT_FAN2 (6)
|
||||
|
||||
#define GET_ALL_AUX_STATUS() \
|
||||
( \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \
|
||||
(GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \
|
||||
(GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \
|
||||
(GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \
|
||||
)
|
||||
|
||||
/* Comment Description
|
||||
* [!] : 변경시 주의
|
||||
* [?] : 결정이 필요
|
||||
* [*] : 주의보다 더 엄중
|
||||
*/
|
||||
|
||||
/* Firmware 버전 (Semantic Versioning) */
|
||||
#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때
|
||||
#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때
|
||||
#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때
|
||||
|
||||
/* Version History
|
||||
* [0.0.1] : DCU 프로젝트 생성
|
||||
* [0.0.2] : DCU 펌웨어 탑재 성공
|
||||
* [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현
|
||||
* [0.0.4] : OLED 표시 화면 구현
|
||||
* [0.0.5] : CAN-B 확인 및 맵핑
|
||||
* [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정
|
||||
* [0.1.6] : Suter 보조엔진 시동 완료 시점
|
||||
* [0.1.7] : 발전상태 전환 조건 추가 26-02-23
|
||||
* [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제>
|
||||
* [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26
|
||||
*/
|
||||
|
||||
#define MAINTENECE_PASSKEY {0,0,0,0}
|
||||
|
||||
#define ENABLED (1)
|
||||
#define DISABLED (!ENABLED)
|
||||
|
||||
/*
|
||||
* Bit mask
|
||||
*/
|
||||
#define MASK_LOW_NIBBLE (0x0FU)
|
||||
#define MASK_HIGH_NIBBLE (0xF0U)
|
||||
#define MASK_BYTE (0xFFU)
|
||||
#define MASK_WORD (0xFFFFU)
|
||||
#define MASK_6BIT (0x3FU)
|
||||
#define MASK_26BIT (0x3FFFFFFUL)
|
||||
|
||||
/*
|
||||
Timer Clock Per 100us
|
||||
*/
|
||||
#define SYSTEM_10MIN_TIME (6000000UL)
|
||||
#define TIME_01MS (10UL)
|
||||
#define TIME_10MS (100UL)
|
||||
#define TIME_20MS (200UL)
|
||||
#define TIME_50MS (500UL)
|
||||
#define TIME_100MS (1000UL)
|
||||
#define TIME_500MS (5000UL)
|
||||
#define TIME_1SEC (10000UL)
|
||||
#define TIME_5SEC (50000UL)
|
||||
#define TIME_10SEC (100000UL)
|
||||
#define TIME_60SEC (600000UL)
|
||||
|
||||
// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250
|
||||
#define SENSOR_LOW_LIMIT (2000) // 단선
|
||||
#define SENSOR_HIGH_LIMIT (4000) // 단락
|
||||
|
||||
#define TIME_OVER (1U)
|
||||
|
||||
enum
|
||||
{
|
||||
TIMER_01MS = 0U,
|
||||
TIMER_10MS,
|
||||
TIMER_20MS,
|
||||
TIMER_50MS,
|
||||
TIMER_100MS,
|
||||
TIMER_500MS,
|
||||
TIMER_1SEC,
|
||||
TIMER_MAX
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
SOFTTIMER_TIME_OVER = 0U,
|
||||
SOFTTIMER_RUNNING,
|
||||
SOFTTIMER_PAUSE,
|
||||
SOFTTIMER_DONT_EXIST
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
SOFTTIMER_WAIT_INIT = 0U,
|
||||
SOFTTIMER_WAIT_ALARM_RESET,
|
||||
SOFTTIMER_WAIT_ENG_COOLDOWN,
|
||||
SOFTTIMER_WAIT_PREHEAT,
|
||||
SOFTTIMER_WAIT_CRANKING,
|
||||
SOFTTIMER_WAIT_RETRY_CRANKING,
|
||||
SOFTTIMER_WAIT_OPERATION,
|
||||
SOFTTIMER_WAIT_SHUTDOWN,
|
||||
SOFTTIMER_WAIT_AFTER_COOLDOWN,
|
||||
SOFTTIMER_WAIT_MAX
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_CS_ENG_HEATER = 0,
|
||||
IDX_CS_GLOW_PLUG,
|
||||
IDX_CS_SOLENOID,
|
||||
IDX_CS_FUEL_PUMP,
|
||||
IDX_CS_COOLANT_PUMP,
|
||||
IDX_CS_FAN1,
|
||||
IDX_CS_FAN2,
|
||||
IDX_CS_MAX
|
||||
} E_AUX_CS_IDX;
|
||||
|
||||
typedef struct ClassSoftTimer
|
||||
{
|
||||
Uint32 ulSetValue;
|
||||
Uint32 ulDecreaseValue;
|
||||
int16 iTimer;
|
||||
int16 iStart;
|
||||
} CSoftTimer;
|
||||
|
||||
typedef struct ClassWaitTimer
|
||||
{
|
||||
Uint32 ulCountSoftClock;
|
||||
Uint16 uiSoftCountTarget;
|
||||
} CWaitTimer;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_SENSOR_ENGINE_HEATER = 0U, // 0
|
||||
IDX_SENSOR_GLOW_PLUG, // 1
|
||||
IDX_SENSOR_SOLENOID, // 2
|
||||
IDX_SENSOR_FUEL_PUMP, // 3
|
||||
IDX_SENSOR_COOLANT_PUMP, // 4
|
||||
IDX_SENSOR_FAN1, // 5
|
||||
IDX_SENSOR_FAN2, // 6
|
||||
IDX_SENSOR_MAX // 7
|
||||
} E_IDX_SENSOR;
|
||||
|
||||
typedef struct ClassGeneralOperValue
|
||||
{
|
||||
Uint16 uiFaultOccured;
|
||||
Uint16 uiDynamicRPM;
|
||||
Uint16 uiPassword[4];
|
||||
Uint16 uiSelfTestCheck;
|
||||
Uint16 uiSelfTestPass;
|
||||
Uint16 uiEmergency;
|
||||
Uint16 uiApuStart;
|
||||
Uint16 uiApuState;
|
||||
Uint16 uiAlarmReset;
|
||||
Uint16 uiMaintenance;
|
||||
Uint16 uiRetryCrankingCount;
|
||||
Uint16 uiWriteEepromDataStart;
|
||||
Uint32 ulTotalOperationHour;
|
||||
struct
|
||||
{
|
||||
Uint16 PlayCmd;
|
||||
} GcuCommand;
|
||||
struct
|
||||
{
|
||||
Uint16 EngineStart;
|
||||
Uint16 EngineStop;
|
||||
Uint16 RpmSetPoint;
|
||||
Uint16 ActiveOverride;
|
||||
Uint16 EmergencyStop;
|
||||
} EcuCommand;
|
||||
struct
|
||||
{
|
||||
Uint16 CarComputer;
|
||||
Uint16 Gcu;
|
||||
Uint16 Ecu;
|
||||
} Conection;
|
||||
struct
|
||||
{
|
||||
Uint16 ManualCranking;
|
||||
Uint16 LampTest;
|
||||
Uint16 KeyTest;
|
||||
} Maintenance;
|
||||
} CGeneralOperValue;
|
||||
|
||||
extern CGeneralOperValue GeneralOperValue;
|
||||
extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX];
|
||||
|
||||
Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime);
|
||||
void COffChipSelect(void);
|
||||
void CSoftWaitCountClear(Uint16 Index);
|
||||
Uint32 CGetSoftClock(void);
|
||||
void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond);
|
||||
void DELAY_USEC(Uint32 ulMicroSeconds);
|
||||
Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx);
|
||||
void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState);
|
||||
|
||||
#endif /* SOURCE_MAIN_H_ */
|
||||
@@ -0,0 +1,167 @@
|
||||
// TI File $Revision: /main/9 $
|
||||
// Checkin $Date: July 2, 2008 14:31:12 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Examples.h
|
||||
//
|
||||
// TITLE: DSP2833x Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EXAMPLES_H
|
||||
#define DSP2833x_EXAMPLES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
|
||||
//
|
||||
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
|
||||
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
|
||||
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
|
||||
|
||||
#define DSP28_PLLCR 10
|
||||
//#define DSP28_PLLCR 9
|
||||
//#define DSP28_PLLCR 8
|
||||
//#define DSP28_PLLCR 7
|
||||
//#define DSP28_PLLCR 6
|
||||
//#define DSP28_PLLCR 5
|
||||
//#define DSP28_PLLCR 4
|
||||
//#define DSP28_PLLCR 3
|
||||
//#define DSP28_PLLCR 2
|
||||
//#define DSP28_PLLCR 1
|
||||
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
|
||||
|
||||
//
|
||||
// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
|
||||
//
|
||||
// Take into account the input clock frequency and the PLL multiplier
|
||||
// selected in step 1.
|
||||
//
|
||||
// Use one of the values provided, or define your own.
|
||||
// The trailing L is required tells the compiler to treat
|
||||
// the number as a 64-bit value.
|
||||
//
|
||||
// Only one statement should be uncommented.
|
||||
//
|
||||
// Example 1:150 MHz devices:
|
||||
// CLKIN is a 30MHz crystal.
|
||||
//
|
||||
// In step 1 the user specified PLLCR = 0xA for a
|
||||
// 150Mhz CPU clock (SYSCLKOUT = 150MHz).
|
||||
//
|
||||
// In this case, the CPU_RATE will be 6.667L
|
||||
// Uncomment the line: #define CPU_RATE 6.667L
|
||||
//
|
||||
// Example 2: 100 MHz devices:
|
||||
// CLKIN is a 20MHz crystal.
|
||||
//
|
||||
// In step 1 the user specified PLLCR = 0xA for a
|
||||
// 100Mhz CPU clock (SYSCLKOUT = 100MHz).
|
||||
//
|
||||
// In this case, the CPU_RATE will be 10.000L
|
||||
// Uncomment the line: #define CPU_RATE 10.000L
|
||||
//
|
||||
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
|
||||
|
||||
//
|
||||
// Target device (in DSP2833x_Device.h) determines CPU frequency
|
||||
// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
|
||||
// (for 28332 and 28333). User does not have to change anything here.
|
||||
//
|
||||
#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only
|
||||
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
|
||||
#define CPU_FRQ_150MHZ 0
|
||||
#else
|
||||
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
|
||||
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
|
||||
#endif
|
||||
|
||||
//
|
||||
// Include Example Header Files
|
||||
//
|
||||
|
||||
//
|
||||
// Prototypes for global functions within the .c files.
|
||||
//
|
||||
#include "DSP2833x_GlobalPrototypes.h"
|
||||
#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples.
|
||||
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
|
||||
#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples.
|
||||
|
||||
#define PARTNO_28335 0xEF
|
||||
#define PARTNO_28334 0xEE
|
||||
#define PARTNO_28333 0xEA
|
||||
#define PARTNO_28332 0xED
|
||||
|
||||
//
|
||||
// Include files not used with DSP/BIOS
|
||||
//
|
||||
#ifndef DSP28_BIOS
|
||||
#include "DSP2833x_DefaultIsr.h"
|
||||
#endif
|
||||
|
||||
//
|
||||
// DO NOT MODIFY THIS LINE.
|
||||
//
|
||||
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \
|
||||
(long double)CPU_RATE) - 9.0L) / 5.0L)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EXAMPLES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: July 27, 2009 13:57:25 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Xintf.h
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interface Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_XINTF_H
|
||||
#define DSP2833x_XINTF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// XINTF timing register bit definitions
|
||||
//
|
||||
struct XTIMING_BITS { // bits description
|
||||
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
|
||||
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
|
||||
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
|
||||
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
|
||||
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
|
||||
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
|
||||
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
|
||||
Uint16 READYMODE:1; // 15 Ready mode
|
||||
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
|
||||
Uint16 rsvd1:4; // 21:18 reserved
|
||||
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
|
||||
Uint16 rsvd3:9; // 31:23 reserved
|
||||
};
|
||||
|
||||
union XTIMING_REG {
|
||||
Uint32 all;
|
||||
struct XTIMING_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF control register bit definitions
|
||||
//
|
||||
struct XINTCNF2_BITS { // bits description
|
||||
Uint16 WRBUFF:2; // 1:0 Write buffer depth
|
||||
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
|
||||
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
|
||||
Uint16 rsvd1:2; // 5:4 reserved
|
||||
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
|
||||
Uint16 rsvd2:1; // 8 reserved
|
||||
Uint16 HOLD:1; // 9 Hold enable/disable
|
||||
Uint16 HOLDS:1; // 10 Current state of HOLDn input
|
||||
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
|
||||
Uint16 rsvd3:4; // 15:12 reserved
|
||||
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
|
||||
Uint16 rsvd4:13; // 31:19 reserved
|
||||
};
|
||||
|
||||
union XINTCNF2_REG {
|
||||
Uint32 all;
|
||||
struct XINTCNF2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF bank switching register bit definitions
|
||||
//
|
||||
struct XBANK_BITS { // bits description
|
||||
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
|
||||
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
|
||||
Uint16 rsvd:10; // 15:6 reserved
|
||||
};
|
||||
|
||||
union XBANK_REG {
|
||||
Uint16 all;
|
||||
struct XBANK_BITS bit;
|
||||
};
|
||||
|
||||
struct XRESET_BITS {
|
||||
Uint16 XHARDRESET:1;
|
||||
Uint16 rsvd1:15;
|
||||
};
|
||||
|
||||
union XRESET_REG {
|
||||
Uint16 all;
|
||||
struct XRESET_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF Register File
|
||||
//
|
||||
struct XINTF_REGS {
|
||||
union XTIMING_REG XTIMING0;
|
||||
Uint32 rsvd1[5];
|
||||
union XTIMING_REG XTIMING6;
|
||||
union XTIMING_REG XTIMING7;
|
||||
Uint32 rsvd2[2];
|
||||
union XINTCNF2_REG XINTCNF2;
|
||||
Uint32 rsvd3;
|
||||
union XBANK_REG XBANK;
|
||||
Uint16 rsvd4;
|
||||
Uint16 XREVISION;
|
||||
Uint16 rsvd5[2];
|
||||
union XRESET_REG XRESET;
|
||||
};
|
||||
|
||||
//
|
||||
// XINTF External References & Function Declarations
|
||||
//
|
||||
extern volatile struct XINTF_REGS XintfRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_XINTF_H definition
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
|
||||
@@ -0,0 +1,454 @@
|
||||
/*****************************************************************************/
|
||||
/* string.h */
|
||||
/* */
|
||||
/* Copyright (c) 1993 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef _STRING_H_
|
||||
#define _STRING_H_
|
||||
|
||||
#include <_ti_config.h>
|
||||
|
||||
#if defined(__TMS320C2000__)
|
||||
#if defined(__TMS320C28XX_CLA__)
|
||||
#error "Header file <string.h> not supported by CLA compiler"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef _SIZE_T_DECLARED
|
||||
#define _SIZE_T_DECLARED
|
||||
#ifdef __clang__
|
||||
typedef __SIZE_TYPE__ size_t;
|
||||
#else
|
||||
typedef __SIZE_T_TYPE__ size_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
|
||||
|
||||
#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__))
|
||||
#define _OPT_IDECL
|
||||
#else
|
||||
#define _OPT_IDECL _IDECL
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_OPT_IDECL size_t strlen(const char *string);
|
||||
|
||||
_OPT_IDECL char *strcpy(char * __restrict dest,
|
||||
const char * __restrict src);
|
||||
_OPT_IDECL char *strncpy(char * __restrict dest,
|
||||
const char * __restrict src, size_t n);
|
||||
_OPT_IDECL char *strcat(char * __restrict string1,
|
||||
const char * __restrict string2);
|
||||
_OPT_IDECL char *strncat(char * __restrict dest,
|
||||
const char * __restrict src, size_t n);
|
||||
_OPT_IDECL char *strchr(const char *string, int c);
|
||||
_OPT_IDECL char *strrchr(const char *string, int c);
|
||||
|
||||
_OPT_IDECL int strcmp(const char *string1, const char *string2);
|
||||
_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n);
|
||||
|
||||
_CODE_ACCESS int strcoll(const char *string1, const char *_string2);
|
||||
_CODE_ACCESS size_t strxfrm(char * __restrict to,
|
||||
const char * __restrict from, size_t n);
|
||||
_CODE_ACCESS char *strpbrk(const char *string, const char *chs);
|
||||
_CODE_ACCESS size_t strspn(const char *string, const char *chs);
|
||||
_CODE_ACCESS size_t strcspn(const char *string, const char *chs);
|
||||
_CODE_ACCESS char *strstr(const char *string1, const char *string2);
|
||||
_CODE_ACCESS char *strtok(char * __restrict str1,
|
||||
const char * __restrict str2);
|
||||
_CODE_ACCESS char *strerror(int _errno);
|
||||
_CODE_ACCESS char *strdup(const char *string);
|
||||
|
||||
|
||||
_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n);
|
||||
|
||||
_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count);
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */
|
||||
_CODE_ACCESS void *memcpy(void * __restrict s1,
|
||||
const void * __restrict s2, size_t n);
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n);
|
||||
_OPT_IDECL void *memchr(const void *cs, int c, size_t n);
|
||||
|
||||
#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \
|
||||
defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__)
|
||||
_CODE_ACCESS void *memset(void *mem, int ch, size_t length);
|
||||
#else
|
||||
_OPT_IDECL void *memset(void *mem, int ch, size_t length);
|
||||
#endif
|
||||
|
||||
#if defined(__TMS320C2000__) && !defined(__TI_EABI__)
|
||||
|
||||
#ifndef __cplusplus
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
|
||||
/* keep macros as direct #defines and not function-like macros or function
|
||||
names surrounded by parentheses to support all original supported use cases
|
||||
including taking their address through the macros and prefixing with
|
||||
namespace macros */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
|
||||
#define far_memcpy __memcpy_ff
|
||||
#define far_strcpy strcpy_ff
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
size_t far_strlen(const char *s);
|
||||
char *strcpy_nf(char *s1, const char *s2);
|
||||
char *strcpy_fn(char *s1, const char *s2);
|
||||
char *strcpy_ff(char *s1, const char *s2);
|
||||
char *far_strncpy(char *s1, const char *s2, size_t n);
|
||||
char *far_strcat(char *s1, const char *s2);
|
||||
char *far_strncat(char *s1, const char *s2, size_t n);
|
||||
char *far_strchr(const char *s, int c);
|
||||
char *far_strrchr(const char *s, int c);
|
||||
int far_strcmp(const char *s1, const char *s2);
|
||||
int far_strncmp(const char *s1, const char *s2, size_t n);
|
||||
int far_strcoll(const char *s1, const char *s2);
|
||||
size_t far_strxfrm(char *s1, const char *s2, size_t n);
|
||||
char *far_strpbrk(const char *s1, const char *s2);
|
||||
size_t far_strspn(const char *s1, const char *s2);
|
||||
size_t far_strcspn(const char *s1, const char *s2);
|
||||
char *far_strstr(const char *s1, const char *s2);
|
||||
char *far_strtok(char *s1, const char *s2);
|
||||
char *far_strerror(int _errno);
|
||||
void *far_memmove(void *s1, const void *s2, size_t n);
|
||||
void *__memcpy_nf (void *_s1, const void *_s2, size_t _n);
|
||||
void *__memcpy_fn (void *_s1, const void *_s2, size_t _n);
|
||||
void *__memcpy_ff (void *_s1, const void *_s2, size_t _n);
|
||||
int far_memcmp(const void *s1, const void *s2, size_t n);
|
||||
void *far_memchr(const void *s, int c, size_t n);
|
||||
void *far_memset(void *s, int c, size_t n);
|
||||
void *far_memlcpy(void *to, const void *from,
|
||||
unsigned long n);
|
||||
void *far_memlmove(void *to, const void *from,
|
||||
unsigned long n);
|
||||
#else /* __cplusplus */
|
||||
long far_memlcpy(long to, long from, unsigned long n);
|
||||
long far_memlmove(long to, long from, unsigned long n);
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern "C" */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION)
|
||||
|
||||
#if (defined(_STRING_IMPLEMENTATION) || \
|
||||
!(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__))))
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
|
||||
|
||||
#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
|
||||
defined(__TMS320C2000__) || \
|
||||
defined(__MSP430__)))
|
||||
#define _OPT_IDEFN
|
||||
#else
|
||||
#define _OPT_IDEFN _IDEFN
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */
|
||||
|
||||
/* MISRA exceptions to avoid changing inline versions of the functions that
|
||||
would be linked in instead of included inline at different mf levels */
|
||||
/* these functions are very well-tested, stable, and efficient; it would
|
||||
introduce a high risk to implement new, separate MISRA versions just for the
|
||||
inline headers */
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRLEN)
|
||||
_OPT_IDEFN size_t strlen(const char *string)
|
||||
{
|
||||
size_t n = (size_t)-1;
|
||||
const char *s = string;
|
||||
|
||||
do n++; while (*s++);
|
||||
return n;
|
||||
}
|
||||
#endif /* _INLINE || _STRLEN */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCPY)
|
||||
_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
|
||||
while ((*d++ = *s++));
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRCPY */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCPY)
|
||||
_OPT_IDEFN char *strncpy(char * __restrict dest,
|
||||
const char * __restrict src,
|
||||
size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
while ((*d++ = *s++) && --n); /* COPY STRING */
|
||||
if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCPY */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCAT)
|
||||
_OPT_IDEFN char *strcat(char * __restrict string1,
|
||||
const char * __restrict string2)
|
||||
{
|
||||
char *s1 = string1;
|
||||
const char *s2 = string2;
|
||||
|
||||
while (*s1) s1++; /* FIND END OF STRING */
|
||||
while ((*s1++ = *s2++)); /* APPEND SECOND STRING */
|
||||
return string1;
|
||||
}
|
||||
#endif /* _INLINE || _STRCAT */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCAT)
|
||||
_OPT_IDEFN char *strncat(char * __restrict dest,
|
||||
const char * __restrict src, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
char *d = dest;
|
||||
const char *s = src;
|
||||
|
||||
while (*d) d++; /* FIND END OF STRING */
|
||||
|
||||
while (n--)
|
||||
if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */
|
||||
*d = 0;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCAT */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCHR)
|
||||
_OPT_IDEFN char *strchr(const char *string, int c)
|
||||
{
|
||||
char tch, ch = c;
|
||||
const char *s = string;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
if ((tch = *s) == ch) return (char *) s;
|
||||
if (!tch) return (char *) 0;
|
||||
s++;
|
||||
}
|
||||
}
|
||||
#endif /* _INLINE || _STRCHR */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRRCHR)
|
||||
_OPT_IDEFN char *strrchr(const char *string, int c)
|
||||
{
|
||||
char tch, ch = c;
|
||||
char *result = 0;
|
||||
const char *s = string;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
if ((tch = *s) == ch) result = (char *) s;
|
||||
if (!tch) break;
|
||||
s++;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif /* _INLINE || _STRRCHR */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRCMP)
|
||||
_OPT_IDEFN int strcmp(const char *string1, const char *string2)
|
||||
{
|
||||
int c1, res;
|
||||
|
||||
for (;;)
|
||||
{
|
||||
c1 = (unsigned char)*string1++;
|
||||
res = c1 - (unsigned char)*string2++;
|
||||
|
||||
if (c1 == 0 || res != 0) break;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
#endif /* _INLINE || _STRCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_STRNCMP)
|
||||
_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const char *s1 = string1;
|
||||
const char *s2 = string2;
|
||||
unsigned char cp;
|
||||
int result;
|
||||
|
||||
do
|
||||
if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++)))
|
||||
return result;
|
||||
while (cp && --n);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* _INLINE || _STRNCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_MEMCMP)
|
||||
_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const unsigned char *mem1 = (unsigned char *)cs;
|
||||
const unsigned char *mem2 = (unsigned char *)ct;
|
||||
int cp1, cp2;
|
||||
|
||||
while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n);
|
||||
return cp1 - cp2;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* _INLINE || _MEMCMP */
|
||||
|
||||
#if defined(_INLINE) || defined(_MEMCHR)
|
||||
_OPT_IDEFN void *memchr(const void *cs, int c, size_t n)
|
||||
{
|
||||
if (n)
|
||||
{
|
||||
const unsigned char *mem = (unsigned char *)cs;
|
||||
unsigned char ch = c;
|
||||
|
||||
do
|
||||
if ( *mem == ch ) return (void *)mem;
|
||||
else mem++;
|
||||
while (--n);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
#endif /* _INLINE || _MEMCHR */
|
||||
|
||||
#if (((defined(_INLINE) || defined(_MEMSET)) && \
|
||||
!(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \
|
||||
!defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__))
|
||||
_OPT_IDEFN void *memset(void *mem, int ch, size_t length)
|
||||
{
|
||||
char *m = (char *)mem;
|
||||
|
||||
while (length--) *m++ = ch;
|
||||
return mem;
|
||||
}
|
||||
#endif /* _INLINE || _MEMSET */
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */
|
||||
|
||||
#endif /* (_INLINE || _STRING_IMPLEMENTATION) */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */
|
||||
/* this file will have already included sys/cdefs.h. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#if __has_include(<sys/cdefs.h>)
|
||||
#include <sys/cdefs.h>
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Include xlocale/_string.h if POSIX is enabled. This will expose the */
|
||||
/* xlocale string interface. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
|
||||
__BEGIN_DECLS
|
||||
#include <xlocale/_string.h>
|
||||
__END_DECLS
|
||||
#endif
|
||||
|
||||
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
|
||||
_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict);
|
||||
_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t);
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* ! _STRING_H_ */
|
||||
@@ -0,0 +1,74 @@
|
||||
/*****************************************************************************/
|
||||
/* linkage.h */
|
||||
/* */
|
||||
/* Copyright (c) 1998 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef _LINKAGE
|
||||
#define _LINKAGE
|
||||
|
||||
#pragma diag_push
|
||||
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */
|
||||
|
||||
/* No modifiers needed to access code */
|
||||
|
||||
#define _CODE_ACCESS
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _DATA_ACCESS ==> how to access RTS global or static data */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#define _DATA_ACCESS
|
||||
#define _DATA_ACCESS_NEAR
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#ifndef _OPTIMIZE_FOR_SPACE
|
||||
#define _OPTIMIZE_FOR_SPACE 1
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Define _IDECL ==> how inline functions are declared */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#ifdef _INLINE
|
||||
#define _IDECL static __inline
|
||||
#define _IDEFN static __inline
|
||||
#else
|
||||
#define _IDECL extern _CODE_ACCESS
|
||||
#define _IDEFN _CODE_ACCESS
|
||||
#endif
|
||||
|
||||
#pragma diag_pop
|
||||
|
||||
#endif /* _LINKAGE */
|
||||
@@ -0,0 +1,145 @@
|
||||
/*****************************************************************************/
|
||||
/* _ti_config.h */
|
||||
/* */
|
||||
/* Copyright (c) 2017 Texas Instruments Incorporated */
|
||||
/* http://www.ti.com/ */
|
||||
/* */
|
||||
/* Redistribution and use in source and binary forms, with or without */
|
||||
/* modification, are permitted provided that the following conditions */
|
||||
/* are met: */
|
||||
/* */
|
||||
/* Redistributions of source code must retain the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer. */
|
||||
/* */
|
||||
/* Redistributions in binary form must reproduce the above copyright */
|
||||
/* notice, this list of conditions and the following disclaimer in */
|
||||
/* the documentation and/or other materials provided with the */
|
||||
/* distribution. */
|
||||
/* */
|
||||
/* Neither the name of Texas Instruments Incorporated nor the names */
|
||||
/* of its contributors may be used to endorse or promote products */
|
||||
/* derived from this software without specific prior written */
|
||||
/* permission. */
|
||||
/* */
|
||||
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
|
||||
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
|
||||
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
|
||||
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
|
||||
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
|
||||
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
|
||||
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
|
||||
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
|
||||
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
|
||||
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
/* */
|
||||
/*****************************************************************************/
|
||||
|
||||
#ifndef __TI_CONFIG_H
|
||||
#define __TI_CONFIG_H
|
||||
|
||||
/*Unsupported pragmas are omitted */
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
# pragma diag_push
|
||||
# pragma CHECK_MISRA("-19.7")
|
||||
# pragma CHECK_MISRA("-19.4")
|
||||
# pragma CHECK_MISRA("-19.1")
|
||||
# pragma CHECK_MISRA("-19.15")
|
||||
# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg)
|
||||
# pragma diag_pop
|
||||
#else
|
||||
# define _TI_PROPRIETARY_PRAGMA(arg)
|
||||
#endif
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_push")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")")
|
||||
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")")
|
||||
|
||||
/* Hide uses of the TI proprietary macros behind other macros.
|
||||
Implementations that don't implement these features should leave
|
||||
these macros undefined. */
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
# ifdef __TI_STRICT_ANSI_MODE__
|
||||
# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
|
||||
# endif
|
||||
|
||||
# ifdef __TI_STRICT_FP_MODE__
|
||||
# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
|
||||
# endif
|
||||
|
||||
# ifdef __unsigned_chars__
|
||||
# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__
|
||||
# else
|
||||
# undef __TI_PROPRIETARY_UNSIGNED_CHARS__
|
||||
# endif
|
||||
#else
|
||||
# undef __TI_PROPRIETARY_UNSIGNED_CHARS__
|
||||
# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
|
||||
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
|
||||
#endif
|
||||
|
||||
/* Common definitions */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
/* C++ */
|
||||
# if (__cplusplus >= 201103L)
|
||||
/* C++11 */
|
||||
# define _TI_NORETURN [[noreturn]]
|
||||
# define _TI_NOEXCEPT noexcept
|
||||
# else
|
||||
/* C++98/03 */
|
||||
# define _TI_NORETURN __attribute__((noreturn))
|
||||
# define _TI_NOEXCEPT throw()
|
||||
# endif
|
||||
#else
|
||||
/* C */
|
||||
# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
|
||||
/* C11 */
|
||||
# define _TI_NORETURN _Noreturn
|
||||
# else
|
||||
/* C89/C99 */
|
||||
# define _TI_NORETURN __attribute__((noreturn))
|
||||
# endif
|
||||
# define _TI_NOEXCEPT
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus) && (__cplusplus >= 201103L)
|
||||
# define _TI_CPP11LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus) && (__cplusplus >= 201402L)
|
||||
# define _TI_CPP14LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \
|
||||
defined(_TI_CPP11LIB)
|
||||
# define _TI_C99LIB 1
|
||||
#endif
|
||||
|
||||
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \
|
||||
defined(_TI_CPP14LIB)
|
||||
# define _TI_C11LIB 1
|
||||
#endif
|
||||
|
||||
/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It
|
||||
is intended to be used for functions like abort and atexit that are supposed
|
||||
to be declared noexcept only in C++14 mode. */
|
||||
#ifdef _TI_CPP14LIB
|
||||
# define _TI_NOEXCEPT_CPP14 noexcept
|
||||
#else
|
||||
# define _TI_NOEXCEPT_CPP14
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Target-specific definitions */
|
||||
#include <linkage.h>
|
||||
|
||||
_TI_PROPRIETARY_PRAGMA("diag_pop")
|
||||
|
||||
#endif /* ifndef __TI_CONFIG_H */
|
||||
@@ -0,0 +1,270 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:13 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EQep.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
|
||||
// Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EQEP_H
|
||||
#define DSP2833x_EQEP_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Capture decoder control register bit definitions
|
||||
//
|
||||
struct QDECCTL_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 QSP:1; // 5 QEPS input polarity
|
||||
Uint16 QIP:1; // 6 QEPI input polarity
|
||||
Uint16 QBP:1; // 7 QEPB input polarity
|
||||
Uint16 QAP:1; // 8 QEPA input polarity
|
||||
Uint16 IGATE:1; // 9 Index pulse gating option
|
||||
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
|
||||
Uint16 XCR:1; // 11 External clock rate
|
||||
Uint16 SPSEL:1; // 12 Sync output pin select
|
||||
Uint16 SOEN:1; // 13 Enable position compare sync
|
||||
Uint16 QSRC:2; // 15:14 Position counter source
|
||||
};
|
||||
|
||||
union QDECCTL_REG {
|
||||
Uint16 all;
|
||||
struct QDECCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP control register bit definitions
|
||||
//
|
||||
struct QEPCTL_BITS { // bits description
|
||||
Uint16 WDE:1; // 0 QEP watchdog enable
|
||||
Uint16 UTE:1; // 1 QEP unit timer enable
|
||||
Uint16 QCLM:1; // 2 QEP capture latch mode
|
||||
Uint16 QPEN:1; // 3 Quadrature position counter enable
|
||||
Uint16 IEL:2; // 5:4 Index event latch
|
||||
Uint16 SEL:1; // 6 Strobe event latch
|
||||
Uint16 SWI:1; // 7 Software init position counter
|
||||
Uint16 IEI:2; // 9:8 Index event init of position count
|
||||
Uint16 SEI:2; // 11:10 Strobe event init
|
||||
Uint16 PCRM:2; // 13:12 Position counter reset
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union QEPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QEPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Quadrature capture control register bit definitions
|
||||
//
|
||||
struct QCAPCTL_BITS { // bits description
|
||||
Uint16 UPPS:4; // 3:0 Unit position pre-scale
|
||||
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
|
||||
Uint16 rsvd1:8; // 14:7 reserved
|
||||
Uint16 CEN:1; // 15 Enable QEP capture
|
||||
};
|
||||
|
||||
union QCAPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QCAPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Position compare control register bit definitions
|
||||
//
|
||||
struct QPOSCTL_BITS { // bits description
|
||||
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
|
||||
Uint16 PCE:1; // 12 Position compare enable/disable
|
||||
Uint16 PCPOL:1; // 13 Polarity of sync output
|
||||
Uint16 PCLOAD:1; // 14 Position compare of shadow load
|
||||
Uint16 PCSHDW:1; // 15 Position compare shadow enable
|
||||
};
|
||||
|
||||
union QPOSCTL_REG {
|
||||
Uint16 all;
|
||||
struct QPOSCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt control register bit definitions
|
||||
//
|
||||
struct QEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 QPE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union QEINT_REG {
|
||||
Uint16 all;
|
||||
struct QEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt status register bit definitions
|
||||
//
|
||||
struct QFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global interrupt
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 PHE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union QFLG_REG {
|
||||
Uint16 all;
|
||||
struct QFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// QEP interrupt force register bit definitions
|
||||
//
|
||||
struct QFRC_BITS { // bits description
|
||||
Uint16 reserved:1; // 0 Reserved
|
||||
Uint16 PCE:1; // 1 Position counter error
|
||||
Uint16 PHE:1; // 2 Quadrature phase error
|
||||
Uint16 QDC:1; // 3 Quadrature dir change
|
||||
Uint16 WTO:1; // 4 Watchdog timeout
|
||||
Uint16 PCU:1; // 5 Position counter underflow
|
||||
Uint16 PCO:1; // 6 Position counter overflow
|
||||
Uint16 PCR:1; // 7 Position compare ready
|
||||
Uint16 PCM:1; // 8 Position compare match
|
||||
Uint16 SEL:1; // 9 Strobe event latch
|
||||
Uint16 IEL:1; // 10 Event latch
|
||||
Uint16 UTO:1; // 11 Unit timeout
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
|
||||
union QFRC_REG {
|
||||
Uint16 all;
|
||||
struct QFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// V1.1 Added UPEVNT (bit 7) This reflects changes
|
||||
// made as of F2833x Rev A devices
|
||||
//
|
||||
|
||||
//
|
||||
// QEP status register bit definitions
|
||||
//
|
||||
struct QEPSTS_BITS { // bits description
|
||||
Uint16 PCEF:1; // 0 Position counter error
|
||||
Uint16 FIMF:1; // 1 First index marker
|
||||
Uint16 CDEF:1; // 2 Capture direction error
|
||||
Uint16 COEF:1; // 3 Capture overflow error
|
||||
Uint16 QDLF:1; // 4 QEP direction latch
|
||||
Uint16 QDF:1; // 5 Quadrature direction
|
||||
Uint16 FIDF:1; // 6 Direction on first index marker
|
||||
Uint16 UPEVNT:1; // 7 Unit position event flag
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union QEPSTS_REG {
|
||||
Uint16 all;
|
||||
struct QEPSTS_BITS bit;
|
||||
};
|
||||
|
||||
struct EQEP_REGS {
|
||||
Uint32 QPOSCNT; // Position counter
|
||||
Uint32 QPOSINIT; // Position counter init
|
||||
Uint32 QPOSMAX; // Maximum position count
|
||||
Uint32 QPOSCMP; // Position compare
|
||||
Uint32 QPOSILAT; // Index position latch
|
||||
Uint32 QPOSSLAT; // Strobe position latch
|
||||
Uint32 QPOSLAT; // Position latch
|
||||
Uint32 QUTMR; // Unit timer
|
||||
Uint32 QUPRD; // Unit period
|
||||
Uint16 QWDTMR; // QEP watchdog timer
|
||||
Uint16 QWDPRD; // QEP watchdog period
|
||||
union QDECCTL_REG QDECCTL; // Quadrature decoder control
|
||||
union QEPCTL_REG QEPCTL; // QEP control
|
||||
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
|
||||
union QPOSCTL_REG QPOSCTL; // Position compare control
|
||||
union QEINT_REG QEINT; // QEP interrupt control
|
||||
union QFLG_REG QFLG; // QEP interrupt flag
|
||||
union QFLG_REG QCLR; // QEP interrupt clear
|
||||
union QFRC_REG QFRC; // QEP interrupt force
|
||||
union QEPSTS_REG QEPSTS; // QEP status
|
||||
Uint16 QCTMR; // QEP capture timer
|
||||
Uint16 QCPRD; // QEP capture period
|
||||
Uint16 QCTMRLAT; // QEP capture latch
|
||||
Uint16 QCPRDLAT; // QEP capture period latch
|
||||
Uint16 rsvd1[30]; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// GPI/O External References & Function Declarations
|
||||
//
|
||||
extern volatile struct EQEP_REGS EQep1Regs;
|
||||
extern volatile struct EQEP_REGS EQep2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EQEP_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,465 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:10 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm.h
|
||||
//
|
||||
// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_EPWM_H
|
||||
#define DSP2833x_EPWM_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Time base control register bit definitions
|
||||
//
|
||||
struct TBCTL_BITS { // bits description
|
||||
Uint16 CTRMODE:2; // 1:0 Counter Mode
|
||||
Uint16 PHSEN:1; // 2 Phase load enable
|
||||
Uint16 PRDLD:1; // 3 Active period load
|
||||
Uint16 SYNCOSEL:2; // 5:4 Sync output select
|
||||
Uint16 SWFSYNC:1; // 6 Software force sync pulse
|
||||
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
|
||||
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
|
||||
Uint16 PHSDIR:1; // 13 Phase Direction
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union TBCTL_REG {
|
||||
Uint16 all;
|
||||
struct TBCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Time base status register bit definitions
|
||||
//
|
||||
struct TBSTS_BITS { // bits description
|
||||
Uint16 CTRDIR:1; // 0 Counter direction status
|
||||
Uint16 SYNCI:1; // 1 External input sync status
|
||||
Uint16 CTRMAX:1; // 2 Counter max latched status
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TBSTS_REG {
|
||||
Uint16 all;
|
||||
struct TBSTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Compare control register bit definitions
|
||||
//
|
||||
struct CMPCTL_BITS { // bits description
|
||||
Uint16 LOADAMODE:2; // 0:1 Active compare A
|
||||
Uint16 LOADBMODE:2; // 3:2 Active compare B
|
||||
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
|
||||
Uint16 rsvd1:1; // 5 reserved
|
||||
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
|
||||
Uint16 rsvd2:1; // 7 reserved
|
||||
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
|
||||
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
|
||||
Uint16 rsvd3:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union CMPCTL_REG {
|
||||
Uint16 all;
|
||||
struct CMPCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier register bit definitions
|
||||
//
|
||||
struct AQCTL_BITS { // bits description
|
||||
Uint16 ZRO:2; // 1:0 Action Counter = Zero
|
||||
Uint16 PRD:2; // 3:2 Action Counter = Period
|
||||
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
|
||||
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
|
||||
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
|
||||
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
|
||||
Uint16 rsvd:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union AQCTL_REG {
|
||||
Uint16 all;
|
||||
struct AQCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier SW force register bit definitions
|
||||
//
|
||||
struct AQSFRC_BITS { // bits description
|
||||
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
|
||||
Uint16 OTSFA:1; // 2 One-time SW Force A output
|
||||
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
|
||||
Uint16 OTSFB:1; // 5 One-time SW Force A output
|
||||
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union AQSFRC_REG {
|
||||
Uint16 all;
|
||||
struct AQSFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Action qualifier continuous SW force register bit definitions
|
||||
//
|
||||
struct AQCSFRC_BITS { // bits description
|
||||
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
|
||||
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union AQCSFRC_REG {
|
||||
Uint16 all;
|
||||
struct AQCSFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// As of version 1.1
|
||||
// Changed the MODE bit-field to OUT_MODE
|
||||
// Added the bit-field IN_MODE
|
||||
// This corresponds to changes in silicon as of F2833x devices
|
||||
// Rev A silicon.
|
||||
//
|
||||
|
||||
//
|
||||
// Dead-band generator control register bit definitions
|
||||
//
|
||||
struct DBCTL_BITS { // bits description
|
||||
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
|
||||
Uint16 POLSEL:2; // 3:2 Polarity Select Control
|
||||
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
|
||||
Uint16 rsvd1:10; // 15:4 reserved
|
||||
};
|
||||
|
||||
union DBCTL_REG {
|
||||
Uint16 all;
|
||||
struct DBCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone select register bit definitions
|
||||
//
|
||||
struct TZSEL_BITS { // bits description
|
||||
Uint16 CBC1:1; // 0 TZ1 CBC select
|
||||
Uint16 CBC2:1; // 1 TZ2 CBC select
|
||||
Uint16 CBC3:1; // 2 TZ3 CBC select
|
||||
Uint16 CBC4:1; // 3 TZ4 CBC select
|
||||
Uint16 CBC5:1; // 4 TZ5 CBC select
|
||||
Uint16 CBC6:1; // 5 TZ6 CBC select
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 OSHT1:1; // 8 One-shot TZ1 select
|
||||
Uint16 OSHT2:1; // 9 One-shot TZ2 select
|
||||
Uint16 OSHT3:1; // 10 One-shot TZ3 select
|
||||
Uint16 OSHT4:1; // 11 One-shot TZ4 select
|
||||
Uint16 OSHT5:1; // 12 One-shot TZ5 select
|
||||
Uint16 OSHT6:1; // 13 One-shot TZ6 select
|
||||
Uint16 rsvd2:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union TZSEL_REG {
|
||||
Uint16 all;
|
||||
struct TZSEL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone control register bit definitions
|
||||
//
|
||||
struct TZCTL_BITS { // bits description
|
||||
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
|
||||
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
|
||||
Uint16 rsvd:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union TZCTL_REG {
|
||||
Uint16 all;
|
||||
struct TZCTL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone control register bit definitions
|
||||
//
|
||||
struct TZEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZEINT_REG {
|
||||
Uint16 all;
|
||||
struct TZEINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag register bit definitions
|
||||
//
|
||||
struct TZFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global status
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZFLG_REG {
|
||||
Uint16 all;
|
||||
struct TZFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag clear register bit definitions
|
||||
//
|
||||
struct TZCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global status
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZCLR_REG {
|
||||
Uint16 all;
|
||||
struct TZCLR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Trip zone flag force register bit definitions
|
||||
//
|
||||
struct TZFRC_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 reserved
|
||||
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
|
||||
Uint16 OST:1; // 2 Trip Zones One Shot Int
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union TZFRC_REG {
|
||||
Uint16 all;
|
||||
struct TZFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger select register bit definitions
|
||||
//
|
||||
struct ETSEL_BITS { // bits description
|
||||
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
|
||||
Uint16 INTEN:1; // 3 EPWMxINTn Enable
|
||||
Uint16 rsvd1:4; // 7:4 reserved
|
||||
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
|
||||
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
|
||||
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
|
||||
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
|
||||
};
|
||||
|
||||
union ETSEL_REG {
|
||||
Uint16 all;
|
||||
struct ETSEL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger pre-scale register bit definitions
|
||||
//
|
||||
struct ETPS_BITS { // bits description
|
||||
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
|
||||
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
|
||||
Uint16 rsvd1:4; // 7:4 reserved
|
||||
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
|
||||
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
|
||||
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
|
||||
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
|
||||
};
|
||||
|
||||
union ETPS_REG {
|
||||
Uint16 all;
|
||||
struct ETPS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Flag register bit definitions
|
||||
//
|
||||
struct ETFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Flag
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETFLG_REG {
|
||||
Uint16 all;
|
||||
struct ETFLG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Clear register bit definitions
|
||||
//
|
||||
struct ETCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Clear
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETCLR_REG {
|
||||
Uint16 all;
|
||||
struct ETCLR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Event trigger Force register bit definitions
|
||||
//
|
||||
struct ETFRC_BITS { // bits description
|
||||
Uint16 INT:1; // 0 EPWMxINTn Force
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 SOCA:1; // 2 EPWMxSOCA Force
|
||||
Uint16 SOCB:1; // 3 EPWMxSOCB Force
|
||||
Uint16 rsvd2:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union ETFRC_REG {
|
||||
Uint16 all;
|
||||
struct ETFRC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PWM chopper control register bit definitions
|
||||
//
|
||||
struct PCCTL_BITS { // bits description
|
||||
Uint16 CHPEN:1; // 0 PWM chopping enable
|
||||
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
|
||||
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
|
||||
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
|
||||
Uint16 rsvd1:5; // 15:11 reserved
|
||||
};
|
||||
|
||||
union PCCTL_REG {
|
||||
Uint16 all;
|
||||
struct PCCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct HRCNFG_BITS { // bits description
|
||||
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
|
||||
Uint16 CTLMODE:1; // 2 Control mode Select Bit
|
||||
Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union HRCNFG_REG {
|
||||
Uint16 all;
|
||||
struct HRCNFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TBPHS_HRPWM_REG { //bits description
|
||||
Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits)
|
||||
Uint16 TBPHS; //31:16 Phase offset register
|
||||
};
|
||||
|
||||
union TBPHS_HRPWM_GROUP {
|
||||
Uint32 all;
|
||||
struct TBPHS_HRPWM_REG half;
|
||||
};
|
||||
|
||||
struct CMPA_HRPWM_REG { // bits description
|
||||
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
|
||||
Uint16 CMPA; // 31:16 Compare A reg
|
||||
};
|
||||
|
||||
union CMPA_HRPWM_GROUP {
|
||||
Uint32 all;
|
||||
struct CMPA_HRPWM_REG half;
|
||||
};
|
||||
|
||||
struct EPWM_REGS {
|
||||
union TBCTL_REG TBCTL; //
|
||||
union TBSTS_REG TBSTS; //
|
||||
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
|
||||
Uint16 TBCTR; // Counter
|
||||
Uint16 TBPRD; // Period register set
|
||||
Uint16 rsvd1; //
|
||||
union CMPCTL_REG CMPCTL; // Compare control
|
||||
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
|
||||
Uint16 CMPB; // Compare B reg
|
||||
union AQCTL_REG AQCTLA; // Action qual output A
|
||||
union AQCTL_REG AQCTLB; // Action qual output B
|
||||
union AQSFRC_REG AQSFRC; // Action qual SW force
|
||||
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
|
||||
union DBCTL_REG DBCTL; // Dead-band control
|
||||
Uint16 DBRED; // Dead-band rising edge delay
|
||||
Uint16 DBFED; // Dead-band falling edge delay
|
||||
union TZSEL_REG TZSEL; // Trip zone select
|
||||
Uint16 rsvd2;
|
||||
union TZCTL_REG TZCTL; // Trip zone control
|
||||
union TZEINT_REG TZEINT; // Trip zone interrupt enable
|
||||
union TZFLG_REG TZFLG; // Trip zone interrupt flags
|
||||
union TZCLR_REG TZCLR; // Trip zone clear
|
||||
union TZFRC_REG TZFRC; // Trip zone force interrupt
|
||||
union ETSEL_REG ETSEL; // Event trigger selection
|
||||
union ETPS_REG ETPS; // Event trigger pre-scaler
|
||||
union ETFLG_REG ETFLG; // Event trigger flags
|
||||
union ETCLR_REG ETCLR; // Event trigger clear
|
||||
union ETFRC_REG ETFRC; // Event trigger force
|
||||
union PCCTL_REG PCCTL; // PWM chopper control
|
||||
Uint16 rsvd3; //
|
||||
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct EPWM_REGS EPwm1Regs;
|
||||
extern volatile struct EPWM_REGS EPwm2Regs;
|
||||
extern volatile struct EPWM_REGS EPwm3Regs;
|
||||
extern volatile struct EPWM_REGS EPwm4Regs;
|
||||
extern volatile struct EPWM_REGS EPwm5Regs;
|
||||
extern volatile struct EPWM_REGS EPwm6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_EPWM_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,730 @@
|
||||
/* ========================================================================= */
|
||||
/* 1. Includes */
|
||||
/* ========================================================================= */
|
||||
#include "main.h"
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */
|
||||
/* ========================================================================= */
|
||||
static void CInitSystem(void);
|
||||
static void COledDisplay(void);
|
||||
static void CInitGeneralOperValue(void);
|
||||
static void CInitGpio(void);
|
||||
static void CSystemConfigure(void);
|
||||
static void CMappingInterrupt(void);
|
||||
static void CProcessSoftTimer(void);
|
||||
static void CShutdownProcedure(void);
|
||||
static Uint16 CPowerOnCheck(void);
|
||||
static void CSoftTimerWorkProcess(void);
|
||||
static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex);
|
||||
static void CReloadSoftTimer(Uint16 uiTimerIndex);
|
||||
static void CInitSoftTimers(void);
|
||||
static void CInitSoftTimer(void);
|
||||
static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay);
|
||||
static void CStartSoftTimer(Uint16 uiTimerIndex);
|
||||
static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock);
|
||||
static void CInitI2C(void);
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */
|
||||
/* ========================================================================= */
|
||||
Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U };
|
||||
|
||||
CGeneralOperValue GeneralOperValue;
|
||||
|
||||
static CSoftTimer SoftTimer[TIMER_MAX];
|
||||
static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX];
|
||||
static Uint32 ulSoftClock;
|
||||
|
||||
/* ========================================================================= */
|
||||
/* Function Definitions */
|
||||
/* ========================================================================= */
|
||||
int main(void)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT;
|
||||
|
||||
CInitSystem();
|
||||
|
||||
CInitOled();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL;
|
||||
|
||||
AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작
|
||||
|
||||
for ( ; ; )
|
||||
{
|
||||
CShutdownProcedure();
|
||||
|
||||
CSoftTimerWorkProcess();
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL)
|
||||
{
|
||||
if (OledOperValue.uiProgressDone == 1U)
|
||||
{
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
COledBufferReset();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST)
|
||||
{
|
||||
if (GeneralOperValue.uiSelfTestCheck == 0U)
|
||||
{
|
||||
GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함
|
||||
|
||||
GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상
|
||||
{
|
||||
COledBufferReset();
|
||||
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef AUX_TEST
|
||||
if (Rx400.AuxControl.AuxTestStart == 1U)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U);
|
||||
}
|
||||
// 정비 모드가 꺼져있어야 시퀀스 동작.
|
||||
else if (GeneralOperValue.uiMaintenance == 0U)
|
||||
#else
|
||||
if (GeneralOperValue.uiMaintenance == 0U)
|
||||
#endif
|
||||
{
|
||||
if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF
|
||||
{
|
||||
CApuOperProcedure(); // 엔진 운영 프로시저
|
||||
|
||||
CLedControlProcedure(); // LED 제어 프로시저
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CDebugModeProcedure();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CSoftTimerWorkProcess(void)
|
||||
{
|
||||
Uint16 ui01msExcute;
|
||||
Uint16 ui10msExcute;
|
||||
Uint16 ui100msExcute;
|
||||
|
||||
ui01msExcute = CIsStatusSoftTimer(TIMER_01MS);
|
||||
ui10msExcute = CIsStatusSoftTimer(TIMER_10MS);
|
||||
ui100msExcute = CIsStatusSoftTimer(TIMER_100MS);
|
||||
|
||||
if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_01MS);
|
||||
|
||||
if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지
|
||||
{
|
||||
CAlarmProcedure();
|
||||
CDisplayAlarmPopup();
|
||||
}
|
||||
|
||||
// (정비모드:키테스트)가 아니면 키 입력 처리 시작 함.
|
||||
if (GeneralOperValue.Maintenance.KeyTest == 0U)
|
||||
{
|
||||
CKeyCheckProcedure();
|
||||
CKeyWaitCount();
|
||||
}
|
||||
}
|
||||
|
||||
if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_10MS);
|
||||
|
||||
CSendECanDataB();
|
||||
COledDisplay();
|
||||
}
|
||||
|
||||
if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
CReloadSoftTimer(TIMER_100MS);
|
||||
CSendECanDataA();
|
||||
CDisplayAntiNoiseRefresh();
|
||||
}
|
||||
}
|
||||
|
||||
static void COledDisplay(void)
|
||||
{
|
||||
static Uint16 RefeshDelay = 0U;
|
||||
|
||||
// 부트 상태 이 후 프로그래스바 화면 표시용
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL)
|
||||
{
|
||||
CInitializePage();
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RefeshDelay == 0U) // 10ms 주기를 위함
|
||||
{
|
||||
// POST 상태 표시 용
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST)
|
||||
{
|
||||
CDisplayPostFail();
|
||||
}
|
||||
else
|
||||
{
|
||||
// POST 이 후 화면 표시용
|
||||
CSetPage(OledOperValue.uiPageNum);
|
||||
}
|
||||
}
|
||||
RefeshDelay = (RefeshDelay + 1U) % 10U;
|
||||
}
|
||||
|
||||
COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT);
|
||||
}
|
||||
|
||||
void CSoftWaitCountClear(Uint16 Index)
|
||||
{
|
||||
WaitTimer[Index].ulCountSoftClock = 0U;
|
||||
WaitTimer[Index].uiSoftCountTarget = 0U;
|
||||
}
|
||||
|
||||
static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
Uint16 isRunning = 1U;
|
||||
|
||||
if (SoftTimer[uiTimerIndex].iStart != -1)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iStart == 1)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U)
|
||||
{
|
||||
isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success
|
||||
}
|
||||
else
|
||||
{
|
||||
isRunning = (Uint16)SOFTTIMER_RUNNING;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return isRunning;
|
||||
}
|
||||
|
||||
static void CReloadSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iTimer != -1)
|
||||
{
|
||||
SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue;
|
||||
}
|
||||
}
|
||||
|
||||
Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime)
|
||||
{
|
||||
Uint16 isCountOver = 0U;
|
||||
|
||||
switch (WaitTimer[uiIndex].uiSoftCountTarget)
|
||||
{
|
||||
case 0U:
|
||||
{
|
||||
WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock();
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 1U;
|
||||
break;
|
||||
}
|
||||
case 1U:
|
||||
{
|
||||
if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER)
|
||||
{
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 2U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
WaitTimer[uiIndex].ulCountSoftClock = 0U;
|
||||
WaitTimer[uiIndex].uiSoftCountTarget = 0U;
|
||||
isCountOver = 1U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return isCountOver;
|
||||
}
|
||||
|
||||
static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock)
|
||||
{
|
||||
Uint16 isRunning = 1U;
|
||||
Uint32 ulCpuClock = CGetSoftClock();
|
||||
|
||||
if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock)
|
||||
{
|
||||
isRunning = 0U;
|
||||
}
|
||||
|
||||
return isRunning;
|
||||
}
|
||||
|
||||
Uint32 CGetSoftClock(void)
|
||||
{
|
||||
return ulSoftClock;
|
||||
}
|
||||
|
||||
static void CInitSystem(void)
|
||||
{
|
||||
DINT;
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitSysCtrl();
|
||||
|
||||
CInitGpio(); // GPIO Direction and mux
|
||||
|
||||
InitPieCtrl();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitPieVectTable();
|
||||
|
||||
InitCpuTimers();
|
||||
|
||||
ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec
|
||||
|
||||
CSystemConfigure();
|
||||
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
|
||||
CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0
|
||||
}
|
||||
|
||||
static void CInitGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// GPIO MUX Setting
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA
|
||||
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA)
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA)
|
||||
|
||||
// GPIO Direction Setting '1' Output, '0' Input
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR
|
||||
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA
|
||||
|
||||
// GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous
|
||||
GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling
|
||||
|
||||
// Gpio Default Value Initial
|
||||
GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
|
||||
GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N
|
||||
GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N
|
||||
GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
void COffChipSelect(void)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, 0U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, 0U);
|
||||
}
|
||||
|
||||
static interrupt void CMainTimer0Interrupt(void)
|
||||
{
|
||||
// Per 100uSec
|
||||
|
||||
DINT;
|
||||
|
||||
ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME;
|
||||
|
||||
CProcessSoftTimer();
|
||||
// Do Something
|
||||
|
||||
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
|
||||
EINT;
|
||||
}
|
||||
|
||||
static void CSystemConfigure(void)
|
||||
{
|
||||
CMappingInterrupt();
|
||||
|
||||
CInitGeneralOperValue();
|
||||
|
||||
CInitAdc();
|
||||
CInitEcan();
|
||||
|
||||
CInitI2C();
|
||||
|
||||
CInitXintf();
|
||||
|
||||
CInitSoftTimers();
|
||||
|
||||
CInitKeyOperValue();
|
||||
}
|
||||
|
||||
static void CInitGeneralOperValue(void)
|
||||
{
|
||||
(void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue));
|
||||
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0;
|
||||
GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0;
|
||||
|
||||
GeneralOperValue.EcuCommand.EngineStop = 1U;
|
||||
}
|
||||
|
||||
static void CMappingInterrupt(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
// Interrupt Vector Remapping
|
||||
PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0
|
||||
PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC
|
||||
PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA
|
||||
PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB
|
||||
|
||||
PieVectTable.TINT0 = &CMainTimer0Interrupt;
|
||||
PieVectTable.ECAN0INTA = &CECanInterruptA;
|
||||
PieVectTable.ECAN0INTB = &CECanInterruptB;
|
||||
PieVectTable.ADCINT = &CAdcInterrupt;
|
||||
|
||||
IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9);
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
static void CProcessSoftTimer(void)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
for (i = 0U; i < (Uint16)TIMER_MAX; i++)
|
||||
{
|
||||
if (SoftTimer[i].iTimer != -1)
|
||||
{
|
||||
if (SoftTimer[i].iStart == 1)
|
||||
{
|
||||
if (SoftTimer[i].ulDecreaseValue > 0UL)
|
||||
{
|
||||
SoftTimer[i].ulDecreaseValue--;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CInitSoftTimers(void)
|
||||
{
|
||||
CInitSoftTimer();
|
||||
CConfigSoftTimer(TIMER_01MS, TIME_01MS);
|
||||
CConfigSoftTimer(TIMER_10MS, TIME_10MS);
|
||||
CConfigSoftTimer(TIMER_20MS, TIME_20MS);
|
||||
CConfigSoftTimer(TIMER_50MS, TIME_50MS);
|
||||
CConfigSoftTimer(TIMER_100MS, TIME_100MS);
|
||||
CConfigSoftTimer(TIMER_500MS, TIME_500MS);
|
||||
|
||||
CStartSoftTimer(TIMER_01MS);
|
||||
CStartSoftTimer(TIMER_10MS);
|
||||
CStartSoftTimer(TIMER_20MS);
|
||||
CStartSoftTimer(TIMER_50MS);
|
||||
CStartSoftTimer(TIMER_100MS);
|
||||
CStartSoftTimer(TIMER_500MS);
|
||||
}
|
||||
|
||||
static void CStartSoftTimer(Uint16 uiTimerIndex)
|
||||
{
|
||||
if (SoftTimer[uiTimerIndex].iTimer != -1)
|
||||
{
|
||||
SoftTimer[uiTimerIndex].iStart = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void CInitSoftTimer(void)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
(void)memset(&SoftTimer, 0, sizeof(SoftTimer));
|
||||
(void)memset(&WaitTimer, 0, sizeof(WaitTimer));
|
||||
|
||||
for (i = 0; i < (Uint16)TIMER_MAX; i++)
|
||||
{
|
||||
SoftTimer[i].iTimer = -1;
|
||||
}
|
||||
}
|
||||
|
||||
static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay)
|
||||
{
|
||||
SoftTimer[TimerIndex].iTimer = (int16) TimerIndex;
|
||||
SoftTimer[TimerIndex].ulSetValue = Delay;
|
||||
SoftTimer[TimerIndex].ulDecreaseValue = Delay;
|
||||
SoftTimer[TimerIndex].iStart = 0;
|
||||
}
|
||||
|
||||
static Uint16 CPowerOnCheck(void)
|
||||
{
|
||||
Uint16 result = 1U;
|
||||
Uint16 uiTemp = 0U;
|
||||
Uint16 i;
|
||||
|
||||
// Check EngineHeater V/I Sensor
|
||||
uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp;
|
||||
|
||||
// Check GlowPlug V/I Sensor
|
||||
uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp;
|
||||
|
||||
// Check Solenoid V/I Sensor
|
||||
uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp;
|
||||
|
||||
// Check FuelPump V/I Sensor
|
||||
uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp;
|
||||
|
||||
// Check CoolantPump V/I Sensor
|
||||
uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp;
|
||||
|
||||
// Check Fan1 V/I Sensor
|
||||
uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp;
|
||||
|
||||
// Check Fan2 V/I Sensor
|
||||
uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U;
|
||||
PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp;
|
||||
|
||||
for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++)
|
||||
{
|
||||
if (PowerOnCheckSensor[i] > 0U)
|
||||
{
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return result; // '0' 정상
|
||||
}
|
||||
|
||||
static void CInitI2C(void)
|
||||
{
|
||||
/* I2C 모듈 리셋 */
|
||||
I2caRegs.I2CMDR.bit.IRS = 0U;
|
||||
|
||||
/*
|
||||
* 1. I2C 프리스케일러 (I2CPSC) 설정
|
||||
* SYSCLKOUT = 150MHz 기준
|
||||
* 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14
|
||||
*/
|
||||
I2caRegs.I2CPSC.all = 14U;
|
||||
|
||||
/*
|
||||
* 2. I2C 마스터 클럭 (SCL) 설정
|
||||
* 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25
|
||||
*/
|
||||
//I2caRegs.I2CCLKL = 45U; // 100kHz
|
||||
//I2caRegs.I2CCLKH = 45U; // 100kHz
|
||||
I2caRegs.I2CCLKL = 8U; // 400kHz
|
||||
I2caRegs.I2CCLKH = 7U; // 400kHz
|
||||
|
||||
/*
|
||||
* 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA)
|
||||
*/
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */
|
||||
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */
|
||||
EDIS;
|
||||
|
||||
/* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */
|
||||
I2caRegs.I2CMDR.all = 0x0020U;
|
||||
}
|
||||
|
||||
static void CShutdownProcedure(void)
|
||||
{
|
||||
if (KeyOperValue.KeyList.MainPower == 1U)
|
||||
{
|
||||
// 장치의 전원을 끄기 전 모든 제어상태를 정지 한다.
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY);
|
||||
COffChipSelect();
|
||||
|
||||
if (GeneralOperValue.uiWriteEepromDataStart == 0U)
|
||||
{
|
||||
GeneralOperValue.uiWriteEepromDataStart = 1U;
|
||||
}
|
||||
|
||||
// 최대 3초 경과 후 꺼짐
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond)
|
||||
{
|
||||
Uint32 ulMask;
|
||||
|
||||
if (pData != NULL)
|
||||
{
|
||||
ulMask = 1UL << (Uint32)uiIdx;
|
||||
*pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask);
|
||||
}
|
||||
}
|
||||
|
||||
Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx)
|
||||
{
|
||||
Uint32 ulMask;
|
||||
|
||||
ulMask = 1UL << (Uint32)uiIdx;
|
||||
|
||||
return (((ulData & ulMask) != 0UL) ? 1U : 0U);
|
||||
}
|
||||
|
||||
void DELAY_USEC(Uint32 ulMicroSeconds)
|
||||
{
|
||||
Uint32 ulDelayCount;
|
||||
|
||||
ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L));
|
||||
|
||||
DSP28x_usDelay(ulDelayCount);
|
||||
}
|
||||
|
||||
void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState)
|
||||
{
|
||||
switch (eIdx)
|
||||
{
|
||||
case IDX_CS_ENG_HEATER:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_GLOW_PLUG:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; }
|
||||
else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_SOLENOID:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_FUEL_PUMP:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; }
|
||||
else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_COOLANT_PUMP:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; }
|
||||
break;
|
||||
}
|
||||
case IDX_CS_FAN1:
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; }
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
if (eIdx == IDX_CS_FAN2)
|
||||
{
|
||||
if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; }
|
||||
else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; }
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,696 @@
|
||||
#ifndef SOURCE_COMM_H_
|
||||
#define SOURCE_COMM_H_
|
||||
|
||||
typedef struct ClassCommCheck
|
||||
{
|
||||
Uint16 CarComputer;
|
||||
Uint16 Gcu;
|
||||
Uint16 Ecu;
|
||||
} CCommCheck;
|
||||
|
||||
typedef struct ClassTx100
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Heartbit;
|
||||
|
||||
/* BYTE 2~4 Reserved */
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 VersionPatch;
|
||||
} CTx100;
|
||||
|
||||
typedef struct ClassTx101
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PlayState; // 0~3 bit
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe
|
||||
|
||||
/* BYTE 2~7 Reserved */
|
||||
|
||||
} CTx101;
|
||||
|
||||
typedef struct ClassTx102
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency
|
||||
|
||||
/* BYTE 1~7 Reserved */
|
||||
|
||||
} CTx102;
|
||||
|
||||
|
||||
typedef struct ClassTx103
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 EngineStart;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 EngineStop;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 FaultReset;
|
||||
|
||||
/* BYTE 3 Reserved */
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 RpmSetpoint;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 ActiveOverride;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 EmergencyStop;
|
||||
|
||||
} CTx103;
|
||||
|
||||
typedef struct ClassTx110
|
||||
{
|
||||
/* BYTE 0~3 */
|
||||
Uint16 DcuFaultB0;
|
||||
Uint16 DcuFaultB1;
|
||||
Uint16 DcuFaultB2;
|
||||
Uint16 DcuFaultB3;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx110;
|
||||
|
||||
typedef struct ClassTx120
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CTx120;
|
||||
|
||||
typedef struct ClassTx121
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 EngHeatVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 EngHeatCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 GlowPlugVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 GlowPlugCurrent;
|
||||
} CTx121;
|
||||
|
||||
typedef struct ClassTx122
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 SolenoidVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SolenoidCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 FuelPumpVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 FuelPumpCurrent;
|
||||
} CTx122;
|
||||
|
||||
typedef struct ClassTx123
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 CoolantPumpVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 CoolantPumpCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Fan1Voltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Fan1Current;
|
||||
} CTx123;
|
||||
|
||||
typedef struct ClassTx124
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Fan2Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Fan2Current;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx124;
|
||||
|
||||
typedef struct ClassRx200
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 HeartBit;
|
||||
|
||||
/* BYTE 2~4 - Reserved */
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 VersionPatch;
|
||||
} CRx200;
|
||||
|
||||
typedef struct ClassRx201
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PlayState; // 0:3 bit PlayState
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 State; // bit 0:AlarmOccured, 1:Shutdown
|
||||
|
||||
/* BYTE 2~7 - Reserved */
|
||||
|
||||
} CRx201;
|
||||
|
||||
typedef struct ClassRx210
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:PcbOverHeat
|
||||
* 1:FetOverHeat
|
||||
* 2:GenOverHeat1
|
||||
* 3:GenOverHeat2
|
||||
*/
|
||||
Uint16 GcuWarning;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:HwTrip
|
||||
* 1:HwIgbt
|
||||
* 2:HwDc
|
||||
* 3:GenOverCurrentU
|
||||
* 4:GenOverCurrentV
|
||||
* 5:GenOverCurrentW
|
||||
* 6:DcOverVoltage
|
||||
* 7:DcOverCurrent
|
||||
*
|
||||
* 8:CrankningOverCurrent
|
||||
* 9:PcbOverHeat
|
||||
* 10:FetOverHeat
|
||||
* 11:GenTempOverHeat1
|
||||
* 12:GenTempOverHeat2
|
||||
* 13:GenOverSpeed
|
||||
* 14:ResolverIC
|
||||
* 15:ResolverParity
|
||||
*/
|
||||
Uint16 GcuFault;
|
||||
|
||||
/* BYTE 4~7 - Reserved*/
|
||||
|
||||
} CRx210;
|
||||
|
||||
typedef struct ClassRx220
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 DcVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 DcCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Rpm;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Power;
|
||||
} CRx220;
|
||||
|
||||
typedef struct ClassRx221
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PcbTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 FetTemperature;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 GenTemperature1;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 GenTemperature2;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CRx221;
|
||||
|
||||
typedef struct ClassRx300
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 VersionMajor;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 VersionMinor;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 VersionPatch;
|
||||
|
||||
/* BYTE 3~7 - Reserved */
|
||||
|
||||
} CRx300;
|
||||
|
||||
typedef struct ClassRx301
|
||||
{
|
||||
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:AlarmOccured
|
||||
* 1~3:PlayState
|
||||
* 4:OverrideActive
|
||||
* 5:GlowPlugActive
|
||||
* 6:HeaterActive
|
||||
* 7:OilPressureMissing
|
||||
*/
|
||||
Uint16 State;
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CRx301;
|
||||
|
||||
typedef struct ClassRx310
|
||||
{
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineOverHeat
|
||||
* 1:Reserved
|
||||
* 2:LoOilPressure
|
||||
* 3:IntakeOverHeat
|
||||
* 4:IntakeLoPressure
|
||||
* 5:EngineLoTemperature
|
||||
* 6:EngineSensor
|
||||
* 7:DefaltValueActive
|
||||
*/
|
||||
Uint16 EcuWarning;
|
||||
|
||||
/* BYTE 1 - Reserved */
|
||||
|
||||
/* BYTE 2 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:OilPressureMissing
|
||||
* 1:IntakeOverHeat
|
||||
* 2:EngineOverHeat
|
||||
* 3:Actuator
|
||||
* 4:RpmSignal
|
||||
* 5:EngineStartFail
|
||||
* 6:Reserved
|
||||
* 7:Reserved
|
||||
*/
|
||||
Uint16 EcuFault;
|
||||
|
||||
/* BYTE 3~7 - Reserved */
|
||||
|
||||
} CRx310;
|
||||
|
||||
typedef struct ClassRx320
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 ActualRpm;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SetRpm;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 ActualTorque;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 SetTorque;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 SystemVoltage;
|
||||
} CRx320;
|
||||
|
||||
typedef struct ClassRx321
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 CoolantTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 Fan1Speed;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Fan2Speed;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 CoolantPumpSpeed;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 BarometricPressure;
|
||||
|
||||
/* BYTE 6~7 - Reserved */
|
||||
|
||||
} CRx321;
|
||||
|
||||
typedef struct ClassRx322
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 TotalOperTimeL : 16;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 TotalOperTimeH : 16;
|
||||
|
||||
/* BYTE 4~7 - Reserved*/
|
||||
|
||||
} CRx322;
|
||||
|
||||
typedef struct ClassTx700
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 HeartBit;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 DCUversionMajor;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 DCUversionMinor;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 GCUversionMajor;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 GCUversionMinor;
|
||||
|
||||
/* BYTE 6 */
|
||||
Uint16 ECUversionMajor;
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 ECUversionMinor;
|
||||
} CTx700;
|
||||
|
||||
typedef struct ClassTx701
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 DcuPlayState; // bit 0~3:PlayState
|
||||
|
||||
/* BYTE 1 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:DcuAlarmOccured
|
||||
* 1:DcuEmergencyStop
|
||||
* 2:PowerSwitchPush
|
||||
* 3:EcuFailSafe
|
||||
*/
|
||||
Uint16 DcuState;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 GcuPlayState; // bit 0~2:GcuPlayState
|
||||
|
||||
/* BYTE 3 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:GcuAlarmOccured
|
||||
* 1:GcuShutdown
|
||||
*/
|
||||
Uint16 GcuState;
|
||||
|
||||
/* BYTE 4 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EcuAlarmOccured
|
||||
* 1~3:EcuPlayState
|
||||
* 4:ActiveOverride
|
||||
* 5:ActiveGlowPlug
|
||||
* 6:ActiveEngHeater
|
||||
* 7:OilPressureMissing
|
||||
*/
|
||||
Uint16 EcuState;
|
||||
|
||||
/* BYTE 5~7 - Reserved */
|
||||
|
||||
} CTx701;
|
||||
|
||||
typedef struct ClassTx710
|
||||
{
|
||||
/* BYTE 0 - GCU Warning */
|
||||
/*
|
||||
* bit description
|
||||
* 0:PcbOverHeat
|
||||
* 1:FetOverHeat
|
||||
* 2:Winding1OverHeat
|
||||
* 3:Winding2OverHeat
|
||||
*/
|
||||
Uint16 GcuWarning;
|
||||
|
||||
/* BYTE 1 - ECU Warning */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineOverHeat
|
||||
* 1:Reserved
|
||||
* 2:LoOilPressure
|
||||
* 3:IntakeOverHeat
|
||||
* 4:IntakeLoPressure
|
||||
* 5:EngineLoTemperature
|
||||
* 6:EngineSensorFault
|
||||
* 7:DefaultValueActive
|
||||
*/
|
||||
Uint16 EcuWarning;
|
||||
|
||||
/* BYTE 2~7 - Reserved */
|
||||
|
||||
} CTx710;
|
||||
|
||||
typedef struct ClassTx720
|
||||
{
|
||||
/* BYTE 0~3 - DCU Fault */
|
||||
Uint16 DcuFault0;
|
||||
Uint16 DcuFault1;
|
||||
Uint16 DcuFault2;
|
||||
Uint16 DcuFault3;
|
||||
|
||||
/* BYTE 4~5 - GCU Fault */
|
||||
Uint16 GcuFault0;
|
||||
Uint16 GcuFault1;
|
||||
|
||||
/* BYTE 6 - Reserved */
|
||||
|
||||
/* BYTE 7 */
|
||||
Uint16 EcuFault;
|
||||
} CTx720;
|
||||
|
||||
typedef struct ClassTx730
|
||||
{
|
||||
/* BYTE 0 */
|
||||
/*
|
||||
* bit description
|
||||
* 0:EngineHeater
|
||||
* 1:GlowPlug
|
||||
* 2:Solenoid
|
||||
* 3:FuelPump
|
||||
* 4:CoolantPump
|
||||
* 5:Fan1
|
||||
* 6:Fan2
|
||||
* 7:Reserved
|
||||
*/
|
||||
Uint16 AuxState;
|
||||
|
||||
/* BYTE 1~7 - Reserved */
|
||||
|
||||
} CTx730;
|
||||
|
||||
typedef struct ClassTx731
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 EngineHeaterVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 EngineHeaterCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 GlowPlugVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 GlowPlugCurrent;
|
||||
} CTx731;
|
||||
|
||||
typedef struct ClassTx732
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 SolenoidVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SolenoidCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 FuelPumpVoltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 FuelPumpCurrent;
|
||||
} CTx732;
|
||||
|
||||
typedef struct ClassTx733
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 CoolantPumpVoltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 CoolantPumpCurrent;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Fan1Voltage;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Fan1Current;
|
||||
} CTx733;
|
||||
|
||||
typedef struct ClassTx734
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Fan2Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Fan2Current;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx734;
|
||||
|
||||
typedef struct ClassTx740
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 Voltage;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 Current;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Rpm;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 Power;
|
||||
} CTx740;
|
||||
|
||||
typedef struct ClassTx741
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 PcbTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 FetTemperature;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Winding1Temperature;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 Winding2Temperature;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx741;
|
||||
|
||||
typedef struct ClassTx750
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 ActualRpm;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 SetRpm;
|
||||
|
||||
/* BYTE 4 */
|
||||
Uint16 ActualTorque;
|
||||
|
||||
/* BYTE 5 */
|
||||
Uint16 SetTorque;
|
||||
|
||||
/* BYTE 6~7 */
|
||||
Uint16 SystemVoltage;
|
||||
} CTx750;
|
||||
|
||||
typedef struct ClassTx751
|
||||
{
|
||||
/* BYTE 0 */
|
||||
Uint16 CoolantTemperature;
|
||||
|
||||
/* BYTE 1 */
|
||||
Uint16 Fan1Speed;
|
||||
|
||||
/* BYTE 2 */
|
||||
Uint16 Fan2Speed;
|
||||
|
||||
/* BYTE 3 */
|
||||
Uint16 CoolantPumpSpeed;
|
||||
|
||||
/* BYTE 4~5 */
|
||||
Uint16 Barometric;
|
||||
|
||||
/* BYTE 6~7 - Reserved */
|
||||
|
||||
} CTx751;
|
||||
|
||||
typedef struct ClassTx752
|
||||
{
|
||||
/* BYTE 0~1 */
|
||||
Uint16 OperationTimeL;
|
||||
|
||||
/* BYTE 2~3 */
|
||||
Uint16 OperationTimeH;
|
||||
|
||||
/* BYTE 4~7 - Reserved */
|
||||
|
||||
} CTx752;
|
||||
|
||||
interrupt void CECanInterruptA(void);
|
||||
interrupt void CECanInterruptB(void);
|
||||
void CSendECanDataA(void);
|
||||
void CSendECanDataB(void);
|
||||
void CInitEcan(void);
|
||||
|
||||
extern CCommCheck CommCheck;
|
||||
extern CRx200 Rx200;
|
||||
extern CRx210 Rx210;
|
||||
extern CRx220 Rx220;
|
||||
extern CRx221 Rx221;
|
||||
extern CRx300 Rx300;
|
||||
extern CRx301 Rx301;
|
||||
extern CRx310 Rx310;
|
||||
extern CRx320 Rx320;
|
||||
extern CRx321 Rx321;
|
||||
extern CRx322 Rx322;
|
||||
|
||||
typedef struct ClassRx400
|
||||
{
|
||||
struct
|
||||
{
|
||||
Uint16 BYTE0 : 8;
|
||||
Uint16 BYTE1 : 8;
|
||||
Uint16 BYTE2 : 8;
|
||||
Uint16 BYTE3 : 8;
|
||||
Uint16 BYTE4 : 8;
|
||||
Uint16 BYTE5 : 8;
|
||||
Uint16 BYTE6 : 8;
|
||||
Uint16 BYTE7 : 8;
|
||||
} Bytes;
|
||||
struct
|
||||
{
|
||||
Uint16 EngineHeater : 1;
|
||||
Uint16 GlowPlug : 1;
|
||||
Uint16 Solenoid : 1;
|
||||
Uint16 FuelPump : 1;
|
||||
Uint16 CoolantPump : 1;
|
||||
Uint16 Fan1 : 1;
|
||||
Uint16 Fan2 : 1;
|
||||
Uint16 AuxTestStart : 1;
|
||||
Uint16 rsvd_padding : 8;
|
||||
} AuxControl;
|
||||
} CRx400;
|
||||
|
||||
extern CRx400 Rx400;
|
||||
|
||||
#endif /* SOURCE_COMM_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,195 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:52:24 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieCtrl.h
|
||||
//
|
||||
// TITLE: DSP2833x Device PIE Control Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_PIE_CTRL_H
|
||||
#define DSP2833x_PIE_CTRL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// PIE Control Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// PIECTRL: Register bit definitions
|
||||
//
|
||||
struct PIECTRL_BITS { // bits description
|
||||
Uint16 ENPIE:1; // 0 Enable PIE block
|
||||
Uint16 PIEVECT:15; // 15:1 Fetched vector address
|
||||
};
|
||||
|
||||
union PIECTRL_REG {
|
||||
Uint16 all;
|
||||
struct PIECTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEIER: Register bit definitions
|
||||
//
|
||||
struct PIEIER_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 INTx.1
|
||||
Uint16 INTx2:1; // 1 INTx.2
|
||||
Uint16 INTx3:1; // 2 INTx.3
|
||||
Uint16 INTx4:1; // 3 INTx.4
|
||||
Uint16 INTx5:1; // 4 INTx.5
|
||||
Uint16 INTx6:1; // 5 INTx.6
|
||||
Uint16 INTx7:1; // 6 INTx.7
|
||||
Uint16 INTx8:1; // 7 INTx.8
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union PIEIER_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEIFR: Register bit definitions
|
||||
//
|
||||
struct PIEIFR_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 INTx.1
|
||||
Uint16 INTx2:1; // 1 INTx.2
|
||||
Uint16 INTx3:1; // 2 INTx.3
|
||||
Uint16 INTx4:1; // 3 INTx.4
|
||||
Uint16 INTx5:1; // 4 INTx.5
|
||||
Uint16 INTx6:1; // 5 INTx.6
|
||||
Uint16 INTx7:1; // 6 INTx.7
|
||||
Uint16 INTx8:1; // 7 INTx.8
|
||||
Uint16 rsvd:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union PIEIFR_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIEACK: Register bit definitions
|
||||
//
|
||||
struct PIEACK_BITS { // bits description
|
||||
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
|
||||
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
|
||||
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
|
||||
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
|
||||
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
|
||||
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
|
||||
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
|
||||
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
|
||||
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
|
||||
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
|
||||
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
|
||||
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
|
||||
Uint16 rsvd:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union PIEACK_REG {
|
||||
Uint16 all;
|
||||
struct PIEACK_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PIE Control Register File
|
||||
//
|
||||
struct PIE_CTRL_REGS {
|
||||
union PIECTRL_REG PIECTRL; // PIE control register
|
||||
union PIEACK_REG PIEACK; // PIE acknowledge
|
||||
union PIEIER_REG PIEIER1; // PIE int1 IER register
|
||||
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
|
||||
union PIEIER_REG PIEIER2; // PIE INT2 IER register
|
||||
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
|
||||
union PIEIER_REG PIEIER3; // PIE INT3 IER register
|
||||
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
|
||||
union PIEIER_REG PIEIER4; // PIE INT4 IER register
|
||||
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
|
||||
union PIEIER_REG PIEIER5; // PIE INT5 IER register
|
||||
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
|
||||
union PIEIER_REG PIEIER6; // PIE INT6 IER register
|
||||
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
|
||||
union PIEIER_REG PIEIER7; // PIE INT7 IER register
|
||||
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
|
||||
union PIEIER_REG PIEIER8; // PIE INT8 IER register
|
||||
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
|
||||
union PIEIER_REG PIEIER9; // PIE INT9 IER register
|
||||
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
|
||||
union PIEIER_REG PIEIER10; // PIE int10 IER register
|
||||
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
|
||||
union PIEIER_REG PIEIER11; // PIE int11 IER register
|
||||
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
|
||||
union PIEIER_REG PIEIER12; // PIE int12 IER register
|
||||
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
|
||||
};
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define PIEACK_GROUP1 0x0001
|
||||
#define PIEACK_GROUP2 0x0002
|
||||
#define PIEACK_GROUP3 0x0004
|
||||
#define PIEACK_GROUP4 0x0008
|
||||
#define PIEACK_GROUP5 0x0010
|
||||
#define PIEACK_GROUP6 0x0020
|
||||
#define PIEACK_GROUP7 0x0040
|
||||
#define PIEACK_GROUP8 0x0080
|
||||
#define PIEACK_GROUP9 0x0100
|
||||
#define PIEACK_GROUP10 0x0200
|
||||
#define PIEACK_GROUP11 0x0400
|
||||
#define PIEACK_GROUP12 0x0800
|
||||
|
||||
//
|
||||
// PIE Control Registers External References & Function Declarations
|
||||
//
|
||||
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_PIE_CTRL_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,255 @@
|
||||
// TI File $Revision: /main/4 $
|
||||
// Checkin $Date: March 20, 2007 15:33:42 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_CpuTimers.h
|
||||
//
|
||||
// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
|
||||
//
|
||||
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
|
||||
// other realtime operating systems.
|
||||
//
|
||||
// Do not use these two timers in your application if you ever plan
|
||||
// on integrating DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// For this reason, comment out the code to manipulate these two
|
||||
// timers if using DSP-BIOS or another realtime OS.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_CPU_TIMERS_H
|
||||
#define DSP2833x_CPU_TIMERS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// CPU Timer Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// TCR: Control register bit definitions
|
||||
//
|
||||
struct TCR_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 TSS:1; // 4 Timer Start/Stop
|
||||
Uint16 TRB:1; // 5 Timer reload
|
||||
Uint16 rsvd2:4; // 9:6 reserved
|
||||
Uint16 SOFT:1; // 10 Emulation modes
|
||||
Uint16 FREE:1; // 11
|
||||
Uint16 rsvd3:2; // 12:13 reserved
|
||||
Uint16 TIE:1; // 14 Output enable
|
||||
Uint16 TIF:1; // 15 Interrupt flag
|
||||
};
|
||||
|
||||
union TCR_REG {
|
||||
Uint16 all;
|
||||
struct TCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TPR: Pre-scale low bit definitions
|
||||
//
|
||||
struct TPR_BITS { // bits description
|
||||
Uint16 TDDR:8; // 7:0 Divide-down low
|
||||
Uint16 PSC:8; // 15:8 Prescale counter low
|
||||
};
|
||||
|
||||
union TPR_REG {
|
||||
Uint16 all;
|
||||
struct TPR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TPRH: Pre-scale high bit definitions
|
||||
//
|
||||
struct TPRH_BITS { // bits description
|
||||
Uint16 TDDRH:8; // 7:0 Divide-down high
|
||||
Uint16 PSCH:8; // 15:8 Prescale counter high
|
||||
};
|
||||
|
||||
union TPRH_REG {
|
||||
Uint16 all;
|
||||
struct TPRH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// TIM, TIMH: Timer register definitions
|
||||
//
|
||||
struct TIM_REG {
|
||||
Uint16 LSW;
|
||||
Uint16 MSW;
|
||||
};
|
||||
|
||||
union TIM_GROUP {
|
||||
Uint32 all;
|
||||
struct TIM_REG half;
|
||||
};
|
||||
|
||||
//
|
||||
// PRD, PRDH: Period register definitions
|
||||
//
|
||||
struct PRD_REG {
|
||||
Uint16 LSW;
|
||||
Uint16 MSW;
|
||||
};
|
||||
|
||||
union PRD_GROUP {
|
||||
Uint32 all;
|
||||
struct PRD_REG half;
|
||||
};
|
||||
|
||||
//
|
||||
// CPU Timer Register File
|
||||
//
|
||||
struct CPUTIMER_REGS {
|
||||
union TIM_GROUP TIM; // Timer counter register
|
||||
union PRD_GROUP PRD; // Period register
|
||||
union TCR_REG TCR; // Timer control register
|
||||
Uint16 rsvd1; // reserved
|
||||
union TPR_REG TPR; // Timer pre-scale low
|
||||
union TPRH_REG TPRH; // Timer pre-scale high
|
||||
};
|
||||
|
||||
//
|
||||
// CPU Timer Support Variables
|
||||
//
|
||||
struct CPUTIMER_VARS {
|
||||
volatile struct CPUTIMER_REGS *RegsAddr;
|
||||
Uint32 InterruptCount;
|
||||
float CPUFreqInMHz;
|
||||
float PeriodInUSec;
|
||||
};
|
||||
|
||||
//
|
||||
// Function prototypes and external definitions
|
||||
//
|
||||
void InitCpuTimers(void);
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
|
||||
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
extern struct CPUTIMER_VARS CpuTimer0;
|
||||
|
||||
//
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS.
|
||||
// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
|
||||
//
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
|
||||
extern struct CPUTIMER_VARS CpuTimer1;
|
||||
extern struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//
|
||||
// Defines for useful Timer Operations:
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer
|
||||
//
|
||||
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer
|
||||
//
|
||||
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value
|
||||
//
|
||||
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value
|
||||
//
|
||||
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value
|
||||
//
|
||||
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
|
||||
|
||||
//
|
||||
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
|
||||
// Do not use these two timers if you ever plan on integrating
|
||||
// DSP-BIOS or another realtime OS.
|
||||
//
|
||||
// For this reason, comment out the code to manipulate these two timers
|
||||
// if using DSP-BIOS or another realtime OS.
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer
|
||||
//
|
||||
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
|
||||
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer
|
||||
//
|
||||
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
|
||||
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value
|
||||
//
|
||||
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
|
||||
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value
|
||||
//
|
||||
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
|
||||
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value
|
||||
//
|
||||
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
|
||||
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_CPU_TIMERS_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,251 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: March 1, 2007 15:57:02 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Sci.h
|
||||
//
|
||||
// TITLE: DSP2833x Device SCI Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SCI_H
|
||||
#define DSP2833x_SCI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// SCI Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// SCICCR communication control register bit definitions
|
||||
//
|
||||
struct SCICCR_BITS { // bit description
|
||||
Uint16 SCICHAR:3; // 2:0 Character length control
|
||||
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
|
||||
Uint16 LOOPBKENA:1; // 4 Loop Back enable
|
||||
Uint16 PARITYENA:1; // 5 Parity enable
|
||||
Uint16 PARITY:1; // 6 Even or Odd Parity
|
||||
Uint16 STOPBITS:1; // 7 Number of Stop Bits
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SCICCR_REG {
|
||||
Uint16 all;
|
||||
struct SCICCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCICTL1 control register 1 bit definitions
|
||||
//
|
||||
struct SCICTL1_BITS { // bit description
|
||||
Uint16 RXENA:1; // 0 SCI receiver enable
|
||||
Uint16 TXENA:1; // 1 SCI transmitter enable
|
||||
Uint16 SLEEP:1; // 2 SCI sleep
|
||||
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
|
||||
Uint16 rsvd:1; // 4 reserved
|
||||
Uint16 SWRESET:1; // 5 Software reset
|
||||
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
|
||||
Uint16 rsvd1:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union SCICTL1_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCICTL2 control register 2 bit definitions
|
||||
//
|
||||
struct SCICTL2_BITS { // bit description
|
||||
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
|
||||
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
|
||||
Uint16 rsvd:4; // 5:2 reserved
|
||||
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
|
||||
Uint16 TXRDY:1; // 7 Transmitter ready flag
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union SCICTL2_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIRXST Receiver status register bit definitions
|
||||
//
|
||||
struct SCIRXST_BITS { // bit description
|
||||
Uint16 rsvd:1; // 0 reserved
|
||||
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
|
||||
Uint16 PE:1; // 2 Parity error flag
|
||||
Uint16 OE:1; // 3 Overrun error flag
|
||||
Uint16 FE:1; // 4 Framing error flag
|
||||
Uint16 BRKDT:1; // 5 Break-detect flag
|
||||
Uint16 RXRDY:1; // 6 Receiver ready flag
|
||||
Uint16 RXERROR:1; // 7 Receiver error flag
|
||||
};
|
||||
|
||||
union SCIRXST_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXST_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions
|
||||
//
|
||||
struct SCIRXBUF_BITS { // bits description
|
||||
Uint16 RXDT:8; // 7:0 Receive word
|
||||
Uint16 rsvd:6; // 13:8 reserved
|
||||
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
|
||||
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
|
||||
};
|
||||
|
||||
union SCIRXBUF_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXBUF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCIPRI Priority control register bit definitions
|
||||
//
|
||||
struct SCIPRI_BITS { // bit description
|
||||
Uint16 rsvd:3; // 2:0 reserved
|
||||
Uint16 FREE:1; // 3 Free emulation suspend mode
|
||||
Uint16 SOFT:1; // 4 Soft emulation suspend mode
|
||||
Uint16 rsvd1:3; // 7:5 reserved
|
||||
};
|
||||
|
||||
union SCIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SCIPRI_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO Transmit register bit definitions
|
||||
//
|
||||
struct SCIFFTX_BITS { // bit description
|
||||
Uint16 TXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 TXFFINT:1; // 7 INT flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO status
|
||||
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
|
||||
Uint16 SCIFFENA:1; // 14 Enhancement enable
|
||||
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
|
||||
};
|
||||
|
||||
union SCIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO recieve register bit definitions
|
||||
//
|
||||
struct SCIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 RXFFINT:1; // 7 INT flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO status
|
||||
Uint16 RXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
|
||||
Uint16 RXFFOVF:1; // 15 FIFO overflow
|
||||
};
|
||||
|
||||
union SCIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI FIFO control register bit definitions
|
||||
//
|
||||
struct SCIFFCT_BITS { // bits description
|
||||
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
|
||||
Uint16 rsvd:5; // 12:8 reserved
|
||||
Uint16 CDC:1; // 13 Auto baud mode enable
|
||||
Uint16 ABDCLR:1; // 14 Auto baud clear
|
||||
Uint16 ABD:1; // 15 Auto baud detect
|
||||
};
|
||||
|
||||
union SCIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SCI Register File
|
||||
//
|
||||
struct SCI_REGS {
|
||||
union SCICCR_REG SCICCR; // Communications control register
|
||||
union SCICTL1_REG SCICTL1; // Control register 1
|
||||
Uint16 SCIHBAUD; // Baud rate (high) register
|
||||
Uint16 SCILBAUD; // Baud rate (low) register
|
||||
union SCICTL2_REG SCICTL2; // Control register 2
|
||||
union SCIRXST_REG SCIRXST; // Recieve status register
|
||||
Uint16 SCIRXEMU; // Recieve emulation buffer register
|
||||
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 SCITXBUF; // Transmit data buffer
|
||||
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
|
||||
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
|
||||
union SCIFFCT_REG SCIFFCT; // FIFO control register
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 rsvd3; // reserved
|
||||
union SCIPRI_REG SCIPRI; // FIFO Priority control
|
||||
};
|
||||
|
||||
//
|
||||
// SCI External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SCI_REGS SciaRegs;
|
||||
extern volatile struct SCI_REGS ScibRegs;
|
||||
extern volatile struct SCI_REGS ScicRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SCI_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,586 @@
|
||||
/* ========================================================================= */
|
||||
/* 1. Includes */
|
||||
/* ========================================================================= */
|
||||
#include "main.h"
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */
|
||||
/* ========================================================================= */
|
||||
#define ENGINE_MAXIMUM_SPEED (2800U)
|
||||
#define ENGINE_OPERATION_SPEED (2400U)
|
||||
#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400
|
||||
|
||||
#define LED_OFF (0U)
|
||||
#define LED_ON (1U)
|
||||
#define LED_BLINK (2U)
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */
|
||||
/* ========================================================================= */
|
||||
static void CInitialStandby(void);
|
||||
static void CEmergencyStop(void);
|
||||
static void CProcessApuStateReady(void);
|
||||
static void CProcessApuStatePreheat(void);
|
||||
static void CProcessApuStateCranking(void);
|
||||
static void CProcessApuStateRetryCranking(void);
|
||||
static void CProcessApuStateEngineIdle(void);
|
||||
static void CProcessApuStateGenerating(void);
|
||||
static void CProcessApuStateCooldown(void);
|
||||
static void CProcessApuStateStopping(void);
|
||||
static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용
|
||||
static void CSetEngineActualRpm(Uint16 Rpm);
|
||||
static float32 CGetGcuLoadPower(void);
|
||||
static Uint16 CDynamicRpmControl(void);
|
||||
static void CLedControl(Uint16 idx, Uint16 state);
|
||||
|
||||
/* ========================================================================= */
|
||||
/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */
|
||||
/* ========================================================================= */
|
||||
// No Code
|
||||
|
||||
/* ========================================================================= */
|
||||
/* Function Definitions */
|
||||
/* ========================================================================= */
|
||||
static void CProcessApuStateReady(void)
|
||||
{
|
||||
// 냉각수 펌프 및 냉각팬 시작
|
||||
CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN1, 1U);
|
||||
CSetAuxCtrlPin(IDX_CS_FAN2, 1U);
|
||||
|
||||
// ECU 동작 명령 송신, 2400 RPM 설정
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_START);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT;
|
||||
}
|
||||
|
||||
static void CProcessApuStatePreheat(void)
|
||||
{
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING;
|
||||
}
|
||||
else
|
||||
{
|
||||
// PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
// 알람처리를 할지 무기한 대기 할 지 검토 필요
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateCranking(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING);
|
||||
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE;
|
||||
GeneralOperValue.uiRetryCrankingCount = 0U;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
}
|
||||
else
|
||||
{
|
||||
// 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING);
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateRetryCranking(void)
|
||||
{
|
||||
if (GeneralOperValue.uiRetryCrankingCount < 3U)
|
||||
{
|
||||
// 5초 대기 후 재시도
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GeneralOperValue.uiRetryCrankingCount++;
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING;
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL);
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateEngineIdle(void)
|
||||
{
|
||||
if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION)
|
||||
{
|
||||
// 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환
|
||||
if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM
|
||||
{
|
||||
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateGenerating(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신
|
||||
GeneralOperValue.uiDynamicRPM = CDynamicRpmControl();
|
||||
CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작
|
||||
}
|
||||
|
||||
static void CProcessApuStateCooldown(void)
|
||||
{
|
||||
Uint16 IsRpmZero;
|
||||
Uint16 IsTimeout;
|
||||
|
||||
// 쿨다운: 발전 중지 -> 엔진 IDLE로 변경
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP);
|
||||
|
||||
IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U;
|
||||
IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U;
|
||||
|
||||
if ((IsRpmZero == 1U) || (IsTimeout == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING;
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateStopping(void)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING)
|
||||
{
|
||||
CInitialStandby();
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
}
|
||||
}
|
||||
|
||||
static void CProcessApuStateTransition(void)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY;
|
||||
CInitialStandby();
|
||||
}
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY)
|
||||
{
|
||||
if (KeyOperValue.KeyList.EngineStartStop == 1U)
|
||||
{
|
||||
GeneralOperValue.uiRetryCrankingCount = 0U;
|
||||
if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U;
|
||||
CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING))
|
||||
{
|
||||
if (KeyOperValue.KeyList.EngineStartStop == 0U)
|
||||
{
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN;
|
||||
}
|
||||
else
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CApuOperProcedure(void)
|
||||
{
|
||||
// 입력 신호 Lo Active
|
||||
Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U;
|
||||
Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U;
|
||||
|
||||
// 비상 상황 체크
|
||||
if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U))
|
||||
{
|
||||
GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY;
|
||||
CEmergencyStop();
|
||||
}
|
||||
else
|
||||
{
|
||||
// 외부 조작에 의한 상태 변경 확인
|
||||
CProcessApuStateTransition();
|
||||
|
||||
// ECU Aux Bypass 제어
|
||||
if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY)
|
||||
{
|
||||
CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig);
|
||||
CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig);
|
||||
CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig);
|
||||
CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig);
|
||||
}
|
||||
|
||||
// 각 상태별 동작 수행
|
||||
switch (GeneralOperValue.uiApuState)
|
||||
{
|
||||
case (Uint16)IDX_APU_OPER_READY:
|
||||
{
|
||||
CProcessApuStateReady();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_PREHEAT:
|
||||
{
|
||||
CProcessApuStatePreheat();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_CRANKING:
|
||||
{
|
||||
CProcessApuStateCranking();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_RETRY_CRANKING:
|
||||
{
|
||||
CProcessApuStateRetryCranking();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_ENGINE_IDLE:
|
||||
{
|
||||
CProcessApuStateEngineIdle();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_GENERATING:
|
||||
{
|
||||
CProcessApuStateGenerating();
|
||||
break;
|
||||
}
|
||||
case (Uint16)IDX_APU_OPER_COOLDOWN:
|
||||
{
|
||||
CProcessApuStateCooldown();
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
CProcessApuStateStopping();
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static Uint16 CDynamicRpmControl(void)
|
||||
{
|
||||
float32 TargetRPM;
|
||||
Uint16 ReturnRpm;
|
||||
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
// 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산
|
||||
TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw
|
||||
|
||||
ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림
|
||||
}
|
||||
else
|
||||
{
|
||||
// 발전 상태가 아닐 때는 기본 2400 RPM 반환
|
||||
ReturnRpm = ENGINE_OPERATION_SPEED;
|
||||
}
|
||||
|
||||
ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED;
|
||||
|
||||
return ReturnRpm;
|
||||
}
|
||||
|
||||
static void CInitialStandby(void)
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP);
|
||||
|
||||
COffChipSelect();
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN);
|
||||
|
||||
GeneralOperValue.uiEmergency = 0U;
|
||||
|
||||
GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD
|
||||
}
|
||||
|
||||
static void CEmergencyStop(void)
|
||||
{
|
||||
KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화
|
||||
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
|
||||
CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY);
|
||||
|
||||
COffChipSelect();
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING);
|
||||
|
||||
CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN);
|
||||
|
||||
GeneralOperValue.uiEmergency = 1U;
|
||||
|
||||
GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD
|
||||
}
|
||||
|
||||
static void CSetEngineActualRpm(Uint16 Rpm)
|
||||
{
|
||||
GeneralOperValue.EcuCommand.RpmSetPoint = Rpm;
|
||||
}
|
||||
|
||||
Uint16 CGetEngineActualRpm(void)
|
||||
{
|
||||
return (Uint16)Rx320.ActualRpm;
|
||||
}
|
||||
|
||||
static float32 CGetGcuLoadPower(void)
|
||||
{
|
||||
float32 power = ((float32)Rx220.Power * 0.1F);
|
||||
|
||||
// 범위를 0.0 ~ 17.0 으로 제한
|
||||
if (power > 17.0F)
|
||||
{
|
||||
power = 17.0F;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (power < 0.0F)
|
||||
{
|
||||
power = 0.0;
|
||||
}
|
||||
}
|
||||
return power;
|
||||
}
|
||||
|
||||
Uint16 CGetGeneratorRpm(void)
|
||||
{
|
||||
return Rx220.Rpm;
|
||||
}
|
||||
|
||||
void CSetGcuCommand(Uint16 Command)
|
||||
{
|
||||
GeneralOperValue.GcuCommand.PlayCmd = Command;
|
||||
}
|
||||
|
||||
void CSetEcuCommand(Uint16 Command)
|
||||
{
|
||||
if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY))
|
||||
{
|
||||
GeneralOperValue.EcuCommand.EngineStart = 0U;
|
||||
GeneralOperValue.EcuCommand.EngineStop = 1U;
|
||||
CSetEngineActualRpm(0U);
|
||||
}
|
||||
else
|
||||
{
|
||||
// [ECU_OPER_CMD_START]
|
||||
GeneralOperValue.EcuCommand.EngineStart = 1U;
|
||||
GeneralOperValue.EcuCommand.EngineStop = 0U;
|
||||
#if 0 // RPM 테스트
|
||||
CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM);
|
||||
#else
|
||||
CSetEngineActualRpm(2400U);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
int16 CGetEngCoolantTemperature(void)
|
||||
{
|
||||
return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도
|
||||
}
|
||||
|
||||
void CDebugModeProcedure(void)
|
||||
{
|
||||
if (GeneralOperValue.Maintenance.ManualCranking == 1U)
|
||||
{
|
||||
if (GeneralOperValue.uiFaultOccured == 0U)
|
||||
{
|
||||
// 알람이 없을 경우만 동작 하도록 함.
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP);
|
||||
}
|
||||
|
||||
if (GeneralOperValue.Maintenance.LampTest == 1U)
|
||||
{
|
||||
CLedControl(0U, 1U);
|
||||
CLedControl(1U, 1U);
|
||||
CLedControl(2U, 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(0U, 0U);
|
||||
CLedControl(1U, 0U);
|
||||
CLedControl(2U, 0U);
|
||||
}
|
||||
|
||||
if (GeneralOperValue.Maintenance.KeyTest == 1U)
|
||||
{
|
||||
Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U;
|
||||
Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U;
|
||||
|
||||
if ((uiKeyUp == 1U) && (uiKeyDn == 1U))
|
||||
{
|
||||
GeneralOperValue.Maintenance.KeyTest = 0U;
|
||||
OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void CLedControlProcedure(void)
|
||||
{
|
||||
static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블
|
||||
{
|
||||
// FAULT, OPER, STOP
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 0: BOOT
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 2: POST
|
||||
{LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY
|
||||
{LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY
|
||||
|
||||
// --- OPER 깜빡임 구간 (준비~예열) ---
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 5: READY
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING
|
||||
{LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP
|
||||
|
||||
{LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전)
|
||||
|
||||
// --- STOP 깜빡임 구간 (APU 정지 시) ---
|
||||
{LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠)
|
||||
{LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정)
|
||||
};
|
||||
|
||||
CLedPattern TargetLeds = {0, 0, 0};
|
||||
|
||||
Uint64 SoftClock = CGetSoftClock();
|
||||
Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함
|
||||
Uint16 WarningValue = 0U;
|
||||
|
||||
TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState];
|
||||
|
||||
// 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정
|
||||
if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING)
|
||||
{
|
||||
WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U;
|
||||
}
|
||||
|
||||
// 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응
|
||||
if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U))
|
||||
{
|
||||
TargetLeds.Fault = (Uint16)LED_BLINK;
|
||||
}
|
||||
|
||||
// FAULT LED 제어
|
||||
if (TargetLeds.Fault == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(0U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(0U, TargetLeds.Fault);
|
||||
}
|
||||
|
||||
// OPERATION LED 제어
|
||||
if (TargetLeds.Operation == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(1U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(1U, TargetLeds.Operation);
|
||||
}
|
||||
|
||||
// STOP LED 제어
|
||||
if (TargetLeds.Stop == (Uint16)LED_BLINK)
|
||||
{
|
||||
CLedControl(2U, IsBlinkOn);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLedControl(2U, TargetLeds.Stop);
|
||||
}
|
||||
}
|
||||
|
||||
static void CLedControl(Uint16 idx, Uint16 state)
|
||||
{
|
||||
/*
|
||||
* idx
|
||||
* 0 : FAULT LED
|
||||
* 1 : OPER LED
|
||||
* 2 : STOP LED
|
||||
*/
|
||||
|
||||
if (idx == 0U)
|
||||
{
|
||||
// GPIO_CPU_LED_FAULT
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO14 = 1U;
|
||||
}
|
||||
}
|
||||
else if (idx == 1U)
|
||||
{
|
||||
// GPIO_CPU_LED_OPERATION
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO13 = 1U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// GPIO_CPU_LED_STOP
|
||||
if (state == 0U)
|
||||
{
|
||||
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
GpioDataRegs.GPASET.bit.GPIO12 = 1U;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,206 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:45:37 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DefaultIsr.h
|
||||
//
|
||||
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DEFAULT_ISR_H
|
||||
#define DSP2833x_DEFAULT_ISR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Default Interrupt Service Routine Declarations:
|
||||
//
|
||||
// The following function prototypes are for the
|
||||
// default ISR routines used with the default PIE vector table.
|
||||
// This default vector table is found in the DSP2833x_PieVect.h
|
||||
// file.
|
||||
//
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts
|
||||
//
|
||||
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
|
||||
interrupt void INT14_ISR(void); // CPU-Timer2
|
||||
interrupt void DATALOG_ISR(void); // Datalogging interrupt
|
||||
interrupt void RTOSINT_ISR(void); // RTOS interrupt
|
||||
interrupt void EMUINT_ISR(void); // Emulation interrupt
|
||||
interrupt void NMI_ISR(void); // Non-maskable interrupt
|
||||
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
|
||||
interrupt void USER1_ISR(void); // User Defined trap 1
|
||||
interrupt void USER2_ISR(void); // User Defined trap 2
|
||||
interrupt void USER3_ISR(void); // User Defined trap 3
|
||||
interrupt void USER4_ISR(void); // User Defined trap 4
|
||||
interrupt void USER5_ISR(void); // User Defined trap 5
|
||||
interrupt void USER6_ISR(void); // User Defined trap 6
|
||||
interrupt void USER7_ISR(void); // User Defined trap 7
|
||||
interrupt void USER8_ISR(void); // User Defined trap 8
|
||||
interrupt void USER9_ISR(void); // User Defined trap 9
|
||||
interrupt void USER10_ISR(void); // User Defined trap 10
|
||||
interrupt void USER11_ISR(void); // User Defined trap 11
|
||||
interrupt void USER12_ISR(void); // User Defined trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
|
||||
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
|
||||
interrupt void XINT1_ISR(void); // External interrupt 1
|
||||
interrupt void XINT2_ISR(void); // External interrupt 2
|
||||
interrupt void ADCINT_ISR(void); // ADC
|
||||
interrupt void TINT0_ISR(void); // Timer 0
|
||||
interrupt void WAKEINT_ISR(void); // WD
|
||||
|
||||
//
|
||||
// Group 2 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
|
||||
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
|
||||
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
|
||||
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
|
||||
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
|
||||
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
|
||||
|
||||
//
|
||||
// Group 3 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EPWM1_INT_ISR(void); // EPWM-1
|
||||
interrupt void EPWM2_INT_ISR(void); // EPWM-2
|
||||
interrupt void EPWM3_INT_ISR(void); // EPWM-3
|
||||
interrupt void EPWM4_INT_ISR(void); // EPWM-4
|
||||
interrupt void EPWM5_INT_ISR(void); // EPWM-5
|
||||
interrupt void EPWM6_INT_ISR(void); // EPWM-6
|
||||
|
||||
//
|
||||
// Group 4 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void ECAP1_INT_ISR(void); // ECAP-1
|
||||
interrupt void ECAP2_INT_ISR(void); // ECAP-2
|
||||
interrupt void ECAP3_INT_ISR(void); // ECAP-3
|
||||
interrupt void ECAP4_INT_ISR(void); // ECAP-4
|
||||
interrupt void ECAP5_INT_ISR(void); // ECAP-5
|
||||
interrupt void ECAP6_INT_ISR(void); // ECAP-6
|
||||
|
||||
//
|
||||
// Group 5 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void EQEP1_INT_ISR(void); // EQEP-1
|
||||
interrupt void EQEP2_INT_ISR(void); // EQEP-2
|
||||
|
||||
//
|
||||
// Group 6 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SPIRXINTA_ISR(void); // SPI-A
|
||||
interrupt void SPITXINTA_ISR(void); // SPI-A
|
||||
interrupt void MRINTA_ISR(void); // McBSP-A
|
||||
interrupt void MXINTA_ISR(void); // McBSP-A
|
||||
interrupt void MRINTB_ISR(void); // McBSP-B
|
||||
interrupt void MXINTB_ISR(void); // McBSP-B
|
||||
|
||||
//
|
||||
// Group 7 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
|
||||
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
|
||||
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
|
||||
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
|
||||
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
|
||||
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
|
||||
|
||||
//
|
||||
// Group 8 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void I2CINT1A_ISR(void); // I2C-A
|
||||
interrupt void I2CINT2A_ISR(void); // I2C-A
|
||||
interrupt void SCIRXINTC_ISR(void); // SCI-C
|
||||
interrupt void SCITXINTC_ISR(void); // SCI-C
|
||||
|
||||
//
|
||||
// Group 9 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void SCIRXINTA_ISR(void); // SCI-A
|
||||
interrupt void SCITXINTA_ISR(void); // SCI-A
|
||||
interrupt void SCIRXINTB_ISR(void); // SCI-B
|
||||
interrupt void SCITXINTB_ISR(void); // SCI-B
|
||||
interrupt void ECAN0INTA_ISR(void); // eCAN-A
|
||||
interrupt void ECAN1INTA_ISR(void); // eCAN-A
|
||||
interrupt void ECAN0INTB_ISR(void); // eCAN-B
|
||||
interrupt void ECAN1INTB_ISR(void); // eCAN-B
|
||||
|
||||
//
|
||||
// Group 10 PIE Interrupt Service Routines
|
||||
//
|
||||
|
||||
//
|
||||
// Group 11 PIE Interrupt Service Routines
|
||||
//
|
||||
|
||||
//
|
||||
// Group 12 PIE Interrupt Service Routines
|
||||
//
|
||||
interrupt void XINT3_ISR(void); // External interrupt 3
|
||||
interrupt void XINT4_ISR(void); // External interrupt 4
|
||||
interrupt void XINT5_ISR(void); // External interrupt 5
|
||||
interrupt void XINT6_ISR(void); // External interrupt 6
|
||||
interrupt void XINT7_ISR(void); // External interrupt 7
|
||||
interrupt void LVF_ISR(void); // Latched overflow flag
|
||||
interrupt void LUF_ISR(void); // Latched underflow flag
|
||||
|
||||
//
|
||||
// Catch-all for Reserved Locations For testing purposes
|
||||
//
|
||||
interrupt void PIE_RESERVED(void); // Reserved for test
|
||||
interrupt void rsvd_ISR(void); // for test
|
||||
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DEFAULT_ISR_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,484 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: May 12, 2008 09:34:58 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SysCtrl.h
|
||||
//
|
||||
// TITLE: DSP2833x Device System Control Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_SYS_CTRL_H
|
||||
#define DSP2833x_SYS_CTRL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// System Control Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// PLL Status Register
|
||||
//
|
||||
struct PLLSTS_BITS { // bits description
|
||||
Uint16 PLLLOCKS:1; // 0 PLL lock status
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 PLLOFF:1; // 2 PLL off bit
|
||||
Uint16 MCLKSTS:1; // 3 Missing clock status bit
|
||||
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
|
||||
Uint16 OSCOFF:1; // 5 Oscillator clock off
|
||||
Uint16 MCLKOFF:1; // 6 Missing clock detect
|
||||
Uint16 DIVSEL:2; // 7 Divide Select
|
||||
Uint16 rsvd2:7; // 15:7 reserved
|
||||
};
|
||||
|
||||
union PLLSTS_REG {
|
||||
Uint16 all;
|
||||
struct PLLSTS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// High speed peripheral clock register bit definitions
|
||||
//
|
||||
struct HISPCP_BITS { // bits description
|
||||
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union HISPCP_REG {
|
||||
Uint16 all;
|
||||
struct HISPCP_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Low speed peripheral clock register bit definitions
|
||||
//
|
||||
struct LOSPCP_BITS { // bits description
|
||||
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
|
||||
Uint16 rsvd1:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union LOSPCP_REG {
|
||||
Uint16 all;
|
||||
struct LOSPCP_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 0 bit definitions
|
||||
//
|
||||
struct PCLKCR0_BITS { // bits description
|
||||
Uint16 rsvd1:2; // 1:0 reserved
|
||||
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
|
||||
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
|
||||
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
|
||||
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
|
||||
Uint16 rsvd2:2; // 7:6 reserved
|
||||
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
|
||||
Uint16 rsvd3:1; // 9 reserved
|
||||
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
|
||||
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
|
||||
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
|
||||
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
|
||||
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
|
||||
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
|
||||
};
|
||||
|
||||
union PCLKCR0_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR0_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 1 bit definitions
|
||||
//
|
||||
struct PCLKCR1_BITS { // bits description
|
||||
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
|
||||
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
|
||||
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
|
||||
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
|
||||
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
|
||||
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
|
||||
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
|
||||
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
|
||||
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
|
||||
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
|
||||
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
|
||||
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
|
||||
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
|
||||
};
|
||||
|
||||
union PCLKCR1_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Peripheral clock control register 2 bit definitions
|
||||
//
|
||||
struct PCLKCR3_BITS { // bits description
|
||||
Uint16 rsvd1:8; // 7:0 reserved
|
||||
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
|
||||
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
|
||||
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
|
||||
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
|
||||
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
|
||||
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
|
||||
Uint16 rsvd2:2; // 15:14 reserved
|
||||
};
|
||||
|
||||
union PCLKCR3_REG {
|
||||
Uint16 all;
|
||||
struct PCLKCR3_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PLL control register bit definitions
|
||||
//
|
||||
struct PLLCR_BITS { // bits description
|
||||
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
|
||||
Uint16 rsvd1:12; // 15:4 reserved
|
||||
};
|
||||
|
||||
union PLLCR_REG {
|
||||
Uint16 all;
|
||||
struct PLLCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Low Power Mode 0 control register bit definitions
|
||||
//
|
||||
struct LPMCR0_BITS { // bits description
|
||||
Uint16 LPM:2; // 1:0 Set the low power mode
|
||||
Uint16 QUALSTDBY:6; // 7:2 Qualification
|
||||
Uint16 rsvd1:7; // 14:8 reserved
|
||||
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
|
||||
};
|
||||
|
||||
union LPMCR0_REG {
|
||||
Uint16 all;
|
||||
struct LPMCR0_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Dual-mapping configuration register bit definitions
|
||||
//
|
||||
struct MAPCNF_BITS { // bits description
|
||||
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
|
||||
Uint16 rsvd1:15; // 15:1 reserved
|
||||
};
|
||||
|
||||
union MAPCNF_REG {
|
||||
Uint16 all;
|
||||
struct MAPCNF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// System Control Register File
|
||||
//
|
||||
struct SYS_CTRL_REGS {
|
||||
Uint16 rsvd1; // 0
|
||||
union PLLSTS_REG PLLSTS; // 1
|
||||
Uint16 rsvd2[8]; // 2-9
|
||||
|
||||
//
|
||||
// 10: High-speed peripheral clock pre-scaler
|
||||
//
|
||||
union HISPCP_REG HISPCP;
|
||||
|
||||
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
|
||||
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
|
||||
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
|
||||
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
|
||||
Uint16 rsvd3; // 15: reserved
|
||||
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
|
||||
union PLLCR_REG PLLCR; // 17: PLL control register
|
||||
|
||||
//
|
||||
// No bit definitions are defined for SCSR because
|
||||
// a read-modify-write instruction can clear the WDOVERRIDE bit
|
||||
//
|
||||
Uint16 SCSR; // 18: System control and status register
|
||||
|
||||
Uint16 WDCNTR; // 19: WD counter register
|
||||
Uint16 rsvd4; // 20
|
||||
Uint16 WDKEY; // 21: WD reset key register
|
||||
Uint16 rsvd5[3]; // 22-24
|
||||
|
||||
//
|
||||
// No bit definitions are defined for WDCR because
|
||||
// the proper value must be written to the WDCHK field
|
||||
// whenever writing to this register.
|
||||
//
|
||||
Uint16 WDCR; // 25: WD timer control register
|
||||
|
||||
Uint16 rsvd6[4]; // 26-29
|
||||
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
|
||||
Uint16 rsvd7[1]; // 31
|
||||
};
|
||||
|
||||
//
|
||||
// CSM Registers
|
||||
//
|
||||
|
||||
//
|
||||
// CSM Status & Control register bit definitions
|
||||
//
|
||||
struct CSMSCR_BITS { // bit description
|
||||
Uint16 SECURE:1; // 0 Secure flag
|
||||
Uint16 rsvd1:14; // 14-1 reserved
|
||||
Uint16 FORCESEC:1; // 15 Force Secure control bit
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union CSMSCR_REG {
|
||||
Uint16 all;
|
||||
struct CSMSCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// CSM Register File
|
||||
//
|
||||
struct CSM_REGS {
|
||||
Uint16 KEY0; // KEY reg bits 15-0
|
||||
Uint16 KEY1; // KEY reg bits 31-16
|
||||
Uint16 KEY2; // KEY reg bits 47-32
|
||||
Uint16 KEY3; // KEY reg bits 63-48
|
||||
Uint16 KEY4; // KEY reg bits 79-64
|
||||
Uint16 KEY5; // KEY reg bits 95-80
|
||||
Uint16 KEY6; // KEY reg bits 111-96
|
||||
Uint16 KEY7; // KEY reg bits 127-112
|
||||
Uint16 rsvd1; // reserved
|
||||
Uint16 rsvd2; // reserved
|
||||
Uint16 rsvd3; // reserved
|
||||
Uint16 rsvd4; // reserved
|
||||
Uint16 rsvd5; // reserved
|
||||
Uint16 rsvd6; // reserved
|
||||
Uint16 rsvd7; // reserved
|
||||
union CSMSCR_REG CSMSCR; // CSM Status & Control register
|
||||
};
|
||||
|
||||
//
|
||||
// Password locations
|
||||
//
|
||||
struct CSM_PWL {
|
||||
Uint16 PSWD0; // PSWD bits 15-0
|
||||
Uint16 PSWD1; // PSWD bits 31-16
|
||||
Uint16 PSWD2; // PSWD bits 47-32
|
||||
Uint16 PSWD3; // PSWD bits 63-48
|
||||
Uint16 PSWD4; // PSWD bits 79-64
|
||||
Uint16 PSWD5; // PSWD bits 95-80
|
||||
Uint16 PSWD6; // PSWD bits 111-96
|
||||
Uint16 PSWD7; // PSWD bits 127-112
|
||||
};
|
||||
|
||||
//
|
||||
// Defines for Flash Registers
|
||||
//
|
||||
#define FLASH_SLEEP 0x0000;
|
||||
#define FLASH_STANDBY 0x0001;
|
||||
#define FLASH_ACTIVE 0x0003;
|
||||
|
||||
//
|
||||
// Flash Option Register bit definitions
|
||||
//
|
||||
struct FOPT_BITS { // bit description
|
||||
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
|
||||
Uint16 rsvd:15; // 1-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FOPT_REG {
|
||||
Uint16 all;
|
||||
struct FOPT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Power Modes Register bit definitions
|
||||
//
|
||||
struct FPWR_BITS { // bit description
|
||||
Uint16 PWR:2; // 0-1 Power Mode bits
|
||||
Uint16 rsvd:14; // 2-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FPWR_REG {
|
||||
Uint16 all;
|
||||
struct FPWR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Status Register bit definitions
|
||||
//
|
||||
struct FSTATUS_BITS { // bit description
|
||||
Uint16 PWRS:2; // 0-1 Power Mode Status bits
|
||||
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
|
||||
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
|
||||
Uint16 rsvd1:4; // 4-7 reserved
|
||||
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
|
||||
Uint16 rsvd2:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FSTATUS_REG {
|
||||
Uint16 all;
|
||||
struct FSTATUS_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Sleep to Standby Wait Counter Register bit definitions
|
||||
//
|
||||
struct FSTDBYWAIT_BITS { // bit description
|
||||
//
|
||||
// 0-8 Bank/Pump Sleep to Standby Wait Count bits
|
||||
//
|
||||
Uint16 STDBYWAIT:9;
|
||||
|
||||
Uint16 rsvd:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FSTDBYWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FSTDBYWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Flash Standby to Active Wait Counter Register bit definitions
|
||||
//
|
||||
struct FACTIVEWAIT_BITS { // bit description
|
||||
//
|
||||
// 0-8 Bank/Pump Standby to Active Wait Count bits
|
||||
//
|
||||
Uint16 ACTIVEWAIT:9;
|
||||
|
||||
Uint16 rsvd:7; // 9-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FACTIVEWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FACTIVEWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Bank Read Access Wait State Register bit definitions
|
||||
//
|
||||
struct FBANKWAIT_BITS { // bit description
|
||||
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
|
||||
Uint16 rsvd1:4; // 4-7 reserved
|
||||
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
|
||||
Uint16 rsvd2:4; // 12-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FBANKWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FBANKWAIT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// OTP Read Access Wait State Register bit definitions
|
||||
//
|
||||
struct FOTPWAIT_BITS { // bit description
|
||||
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
|
||||
Uint16 rsvd:11; // 5-15 reserved
|
||||
};
|
||||
|
||||
//
|
||||
// Allow access to the bit fields or entire register
|
||||
//
|
||||
union FOTPWAIT_REG {
|
||||
Uint16 all;
|
||||
struct FOTPWAIT_BITS bit;
|
||||
};
|
||||
|
||||
struct FLASH_REGS {
|
||||
union FOPT_REG FOPT; // Option Register
|
||||
Uint16 rsvd1; // reserved
|
||||
union FPWR_REG FPWR; // Power Modes Register
|
||||
union FSTATUS_REG FSTATUS; // Status Register
|
||||
|
||||
//
|
||||
// Pump/Bank Sleep to Standby Wait State Register
|
||||
//
|
||||
union FSTDBYWAIT_REG FSTDBYWAIT;
|
||||
|
||||
//
|
||||
// Pump/Bank Standby to Active Wait State Register
|
||||
//
|
||||
union FACTIVEWAIT_REG FACTIVEWAIT;
|
||||
|
||||
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
|
||||
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
|
||||
};
|
||||
|
||||
//
|
||||
// System Control External References & Function Declarations
|
||||
//
|
||||
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
|
||||
extern volatile struct CSM_REGS CsmRegs;
|
||||
extern volatile struct CSM_PWL CsmPwl;
|
||||
extern volatile struct FLASH_REGS FlashRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_SYS_CTRL_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,139 @@
|
||||
// TI File $Revision: /main/2 $
|
||||
// Checkin $Date: August 14, 2007 16:32:29 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Dma_defines.h
|
||||
//
|
||||
// TITLE: #defines used in DMA examples
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DMA_DEFINES_H
|
||||
#define DSP2833x_DMA_DEFINES_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// MODE
|
||||
//
|
||||
// PERINTSEL bits
|
||||
//
|
||||
#define DMA_SEQ1INT 1
|
||||
#define DMA_SEQ2INT 2
|
||||
#define DMA_XINT1 3
|
||||
#define DMA_XINT2 4
|
||||
#define DMA_XINT3 5
|
||||
#define DMA_XINT4 6
|
||||
#define DMA_XINT5 7
|
||||
#define DMA_XINT6 8
|
||||
#define DMA_XINT7 9
|
||||
#define DMA_XINT13 10
|
||||
#define DMA_TINT0 11
|
||||
#define DMA_TINT1 12
|
||||
#define DMA_TINT2 13
|
||||
#define DMA_MXEVTA 14
|
||||
#define DMA_MREVTA 15
|
||||
#define DMA_MXREVTB 16
|
||||
#define DMA_MREVTB 17
|
||||
|
||||
//
|
||||
// OVERINTE bit
|
||||
//
|
||||
#define OVRFLOW_DISABLE 0x0
|
||||
#define OVEFLOW_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PERINTE bit
|
||||
//
|
||||
#define PERINT_DISABLE 0x0
|
||||
#define PERINT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHINTMODE bits
|
||||
//
|
||||
#define CHINT_BEGIN 0x0
|
||||
#define CHINT_END 0x1
|
||||
|
||||
//
|
||||
// ONESHOT bits
|
||||
//
|
||||
#define ONESHOT_DISABLE 0x0
|
||||
#define ONESHOT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CONTINOUS bit
|
||||
//
|
||||
#define CONT_DISABLE 0x0
|
||||
#define CONT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCE bit
|
||||
//
|
||||
#define SYNC_DISABLE 0x0
|
||||
#define SYNC_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCSEL bit
|
||||
//
|
||||
#define SYNC_SRC 0x0
|
||||
#define SYNC_DST 0x1
|
||||
|
||||
//
|
||||
// DATASIZE bit
|
||||
//
|
||||
#define SIXTEEN_BIT 0x0
|
||||
#define THIRTYTWO_BIT 0x1
|
||||
|
||||
//
|
||||
// CHINTE bit
|
||||
//
|
||||
#define CHINT_DISABLE 0x0
|
||||
#define CHINT_ENABLE 0x1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of DSP2833x_EPWM_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,285 @@
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: August 18, 2006 13:51:50 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Adc.h
|
||||
//
|
||||
// TITLE: DSP2833x Device ADC Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_ADC_H
|
||||
#define DSP2833x_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// ADC Individual Register Bit Definitions:
|
||||
//
|
||||
struct ADCTRL1_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 reserved
|
||||
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
|
||||
Uint16 SEQ_OVRD:1; // 5 Sequencer override
|
||||
Uint16 CONT_RUN:1; // 6 Continuous run
|
||||
Uint16 CPS:1; // 7 ADC core clock pre-scalar
|
||||
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
|
||||
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
|
||||
Uint16 RESET:1; // 14 ADC reset
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union ADCTRL1_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL1_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCTRL2_BITS { // bits description
|
||||
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
|
||||
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
|
||||
Uint16 rsvd2:1; // 4 reserved
|
||||
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
|
||||
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
|
||||
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
|
||||
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
|
||||
Uint16 rsvd3:1; // 9 reserved
|
||||
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
|
||||
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
|
||||
Uint16 rsvd4:1; // 12 reserved
|
||||
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
|
||||
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
|
||||
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
|
||||
};
|
||||
|
||||
union ADCTRL2_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL2_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCASEQSR_BITS { // bits description
|
||||
Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
|
||||
Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
|
||||
Uint16 rsvd1:1; // 7 reserved
|
||||
Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
|
||||
Uint16 rsvd2:4; // 15:12 reserved
|
||||
};
|
||||
|
||||
union ADCASEQSR_REG {
|
||||
Uint16 all;
|
||||
struct ADCASEQSR_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCMAXCONV_BITS { // bits description
|
||||
Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
|
||||
Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
|
||||
Uint16 rsvd1:9; // 15:7 reserved
|
||||
};
|
||||
|
||||
union ADCMAXCONV_REG {
|
||||
Uint16 all;
|
||||
struct ADCMAXCONV_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ1_BITS { // bits description
|
||||
Uint16 CONV00:4; // 3:0 Conversion selection 00
|
||||
Uint16 CONV01:4; // 7:4 Conversion selection 01
|
||||
Uint16 CONV02:4; // 11:8 Conversion selection 02
|
||||
Uint16 CONV03:4; // 15:12 Conversion selection 03
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ1_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ1_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ2_BITS { // bits description
|
||||
Uint16 CONV04:4; // 3:0 Conversion selection 04
|
||||
Uint16 CONV05:4; // 7:4 Conversion selection 05
|
||||
Uint16 CONV06:4; // 11:8 Conversion selection 06
|
||||
Uint16 CONV07:4; // 15:12 Conversion selection 07
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ2_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ2_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ3_BITS { // bits description
|
||||
Uint16 CONV08:4; // 3:0 Conversion selection 08
|
||||
Uint16 CONV09:4; // 7:4 Conversion selection 09
|
||||
Uint16 CONV10:4; // 11:8 Conversion selection 10
|
||||
Uint16 CONV11:4; // 15:12 Conversion selection 11
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ3_REG{
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ3_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCCHSELSEQ4_BITS { // bits description
|
||||
Uint16 CONV12:4; // 3:0 Conversion selection 12
|
||||
Uint16 CONV13:4; // 7:4 Conversion selection 13
|
||||
Uint16 CONV14:4; // 11:8 Conversion selection 14
|
||||
Uint16 CONV15:4; // 15:12 Conversion selection 15
|
||||
};
|
||||
|
||||
union ADCCHSELSEQ4_REG {
|
||||
Uint16 all;
|
||||
struct ADCCHSELSEQ4_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCTRL3_BITS { // bits description
|
||||
Uint16 SMODE_SEL:1; // 0 Sampling mode select
|
||||
Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
|
||||
Uint16 ADCPWDN:1; // 5 ADC powerdown
|
||||
Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ADCTRL3_REG {
|
||||
Uint16 all;
|
||||
struct ADCTRL3_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCST_BITS { // bits description
|
||||
Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
|
||||
Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
|
||||
Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
|
||||
Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
|
||||
Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
|
||||
Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
|
||||
Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
|
||||
Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
|
||||
Uint16 rsvd1:8; // 15:8 reserved
|
||||
};
|
||||
|
||||
union ADCST_REG {
|
||||
Uint16 all;
|
||||
struct ADCST_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCREFSEL_BITS { // bits description
|
||||
Uint16 rsvd1:14; // 13:0 reserved
|
||||
Uint16 REF_SEL:2; // 15:14 Reference select
|
||||
};
|
||||
union ADCREFSEL_REG {
|
||||
Uint16 all;
|
||||
struct ADCREFSEL_BITS bit;
|
||||
};
|
||||
|
||||
struct ADCOFFTRIM_BITS{ // bits description
|
||||
int16 OFFSET_TRIM:9; // 8:0 Offset Trim
|
||||
Uint16 rsvd1:7; // 15:9 reserved
|
||||
};
|
||||
|
||||
union ADCOFFTRIM_REG{
|
||||
Uint16 all;
|
||||
struct ADCOFFTRIM_BITS bit;
|
||||
};
|
||||
|
||||
struct ADC_REGS {
|
||||
union ADCTRL1_REG ADCTRL1; //ADC Control 1
|
||||
union ADCTRL2_REG ADCTRL2; //ADC Control 2
|
||||
union ADCMAXCONV_REG ADCMAXCONV; //Max conversions
|
||||
union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1
|
||||
union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2
|
||||
union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3
|
||||
union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4
|
||||
union ADCASEQSR_REG ADCASEQSR; //Autosequence status register
|
||||
Uint16 ADCRESULT0; //Conversion Result Buffer 0
|
||||
Uint16 ADCRESULT1; //Conversion Result Buffer 1
|
||||
Uint16 ADCRESULT2; //Conversion Result Buffer 2
|
||||
Uint16 ADCRESULT3; //Conversion Result Buffer 3
|
||||
Uint16 ADCRESULT4; //Conversion Result Buffer 4
|
||||
Uint16 ADCRESULT5; //Conversion Result Buffer 5
|
||||
Uint16 ADCRESULT6; //Conversion Result Buffer 6
|
||||
Uint16 ADCRESULT7; //Conversion Result Buffer 7
|
||||
Uint16 ADCRESULT8; //Conversion Result Buffer 8
|
||||
Uint16 ADCRESULT9; //Conversion Result Buffer 9
|
||||
Uint16 ADCRESULT10; //Conversion Result Buffer 10
|
||||
Uint16 ADCRESULT11; //Conversion Result Buffer 11
|
||||
Uint16 ADCRESULT12; //Conversion Result Buffer 12
|
||||
Uint16 ADCRESULT13; //Conversion Result Buffer 13
|
||||
Uint16 ADCRESULT14; //Conversion Result Buffer 14
|
||||
Uint16 ADCRESULT15; //Conversion Result Buffer 15
|
||||
union ADCTRL3_REG ADCTRL3; //ADC Control 3
|
||||
union ADCST_REG ADCST; //ADC Status Register
|
||||
Uint16 rsvd1;
|
||||
Uint16 rsvd2;
|
||||
union ADCREFSEL_REG ADCREFSEL; //Reference Select Register
|
||||
union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register
|
||||
};
|
||||
|
||||
struct ADC_RESULT_MIRROR_REGS
|
||||
{
|
||||
Uint16 ADCRESULT0; // Conversion Result Buffer 0
|
||||
Uint16 ADCRESULT1; // Conversion Result Buffer 1
|
||||
Uint16 ADCRESULT2; // Conversion Result Buffer 2
|
||||
Uint16 ADCRESULT3; // Conversion Result Buffer 3
|
||||
Uint16 ADCRESULT4; // Conversion Result Buffer 4
|
||||
Uint16 ADCRESULT5; // Conversion Result Buffer 5
|
||||
Uint16 ADCRESULT6; // Conversion Result Buffer 6
|
||||
Uint16 ADCRESULT7; // Conversion Result Buffer 7
|
||||
Uint16 ADCRESULT8; // Conversion Result Buffer 8
|
||||
Uint16 ADCRESULT9; // Conversion Result Buffer 9
|
||||
Uint16 ADCRESULT10; // Conversion Result Buffer 10
|
||||
Uint16 ADCRESULT11; // Conversion Result Buffer 11
|
||||
Uint16 ADCRESULT12; // Conversion Result Buffer 12
|
||||
Uint16 ADCRESULT13; // Conversion Result Buffer 13
|
||||
Uint16 ADCRESULT14; // Conversion Result Buffer 14
|
||||
Uint16 ADCRESULT15; // Conversion Result Buffer 15
|
||||
};
|
||||
|
||||
//
|
||||
// ADC External References & Function Declarations:
|
||||
//
|
||||
extern volatile struct ADC_REGS AdcRegs;
|
||||
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_ADC_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,807 @@
|
||||
// TI File $Revision: /main/5 $
|
||||
// Checkin $Date: May 14, 2008 16:30:31 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Mcbsp.h
|
||||
//
|
||||
// TITLE: DSP2833x Device McBSP Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_MCBSP_H
|
||||
#define DSP2833x_MCBSP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// McBSP Individual Register Bit Definitions
|
||||
//
|
||||
|
||||
//
|
||||
// McBSP DRR2 register bit definitions
|
||||
//
|
||||
struct DRR2_BITS { // bit description
|
||||
Uint16 HWLB:8; // 16:23 High word low byte
|
||||
Uint16 HWHB:8; // 24:31 High word high byte
|
||||
};
|
||||
|
||||
union DRR2_REG {
|
||||
Uint16 all;
|
||||
struct DRR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DRR1 register bit definitions
|
||||
//
|
||||
struct DRR1_BITS { // bit description
|
||||
Uint16 LWLB:8; // 16:23 Low word low byte
|
||||
Uint16 LWHB:8; // 24:31 low word high byte
|
||||
};
|
||||
|
||||
union DRR1_REG {
|
||||
Uint16 all;
|
||||
struct DRR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DXR2 register bit definitions
|
||||
//
|
||||
struct DXR2_BITS { // bit description
|
||||
Uint16 HWLB:8; // 16:23 High word low byte
|
||||
Uint16 HWHB:8; // 24:31 High word high byte
|
||||
};
|
||||
|
||||
union DXR2_REG {
|
||||
Uint16 all;
|
||||
struct DXR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP DXR1 register bit definitions
|
||||
//
|
||||
struct DXR1_BITS { // bit description
|
||||
Uint16 LWLB:8; // 16:23 Low word low byte
|
||||
Uint16 LWHB:8; // 24:31 low word high byte
|
||||
};
|
||||
|
||||
union DXR1_REG {
|
||||
Uint16 all;
|
||||
struct DXR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPCR2 control register bit definitions
|
||||
//
|
||||
struct SPCR2_BITS { // bit description
|
||||
Uint16 XRST:1; // 0 transmit reset
|
||||
Uint16 XRDY:1; // 1 transmit ready
|
||||
Uint16 XEMPTY:1; // 2 Transmit empty
|
||||
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
|
||||
Uint16 XINTM:2; // 5:4 Transmit interrupt types
|
||||
Uint16 GRST:1; // 6 CLKG reset
|
||||
Uint16 FRST:1; // 7 Frame sync reset
|
||||
Uint16 SOFT:1; // 8 SOFT bit
|
||||
Uint16 FREE:1; // 9 FREE bit
|
||||
Uint16 rsvd:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union SPCR2_REG {
|
||||
Uint16 all;
|
||||
struct SPCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SPCR1 control register bit definitions
|
||||
//
|
||||
struct SPCR1_BITS { // bit description
|
||||
Uint16 RRST:1; // 0 Receive reset
|
||||
Uint16 RRDY:1; // 1 Receive ready
|
||||
Uint16 RFULL:1; // 2 Receive full
|
||||
Uint16 RSYNCERR:1; // 7 Receive syn error
|
||||
Uint16 RINTM:2; // 5:4 Receive interrupt types
|
||||
Uint16 rsvd1:1; // 6 reserved
|
||||
Uint16 DXENA:1; // 7 DX hi-z enable
|
||||
Uint16 rsvd2:3; // 10:8 reserved
|
||||
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
|
||||
Uint16 RJUST:2; // 13:14 Right justified
|
||||
Uint16 DLB:1; // 15 Digital loop back
|
||||
};
|
||||
|
||||
union SPCR1_REG {
|
||||
Uint16 all;
|
||||
struct SPCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCR2 control register bit definitions
|
||||
//
|
||||
struct RCR2_BITS { // bit description
|
||||
Uint16 RDATDLY:2; // 1:0 Receive data delay
|
||||
Uint16 RFIG:1; // 2 Receive frame sync ignore
|
||||
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
|
||||
Uint16 RWDLEN2:3; // 7:5 Receive word length
|
||||
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
|
||||
Uint16 RPHASE:1; // 15 Receive Phase
|
||||
};
|
||||
|
||||
union RCR2_REG {
|
||||
Uint16 all;
|
||||
struct RCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCR1 control register bit definitions
|
||||
//
|
||||
struct RCR1_BITS { // bit description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 RWDLEN1:3; // 7:5 Receive word length
|
||||
Uint16 RFRLEN1:7; // 14:8 Receive frame length
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union RCR1_REG {
|
||||
Uint16 all;
|
||||
struct RCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCR2 control register bit definitions
|
||||
//
|
||||
struct XCR2_BITS { // bit description
|
||||
Uint16 XDATDLY:2; // 1:0 Transmit data delay
|
||||
Uint16 XFIG:1; // 2 Transmit frame sync ignore
|
||||
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
|
||||
Uint16 XWDLEN2:3; // 7:5 Transmit word length
|
||||
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
|
||||
Uint16 XPHASE:1; // 15 Transmit Phase
|
||||
};
|
||||
|
||||
union XCR2_REG {
|
||||
Uint16 all;
|
||||
struct XCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCR1 control register bit definitions
|
||||
//
|
||||
struct XCR1_BITS { // bit description
|
||||
Uint16 rsvd1:5; // 4:0 reserved
|
||||
Uint16 XWDLEN1:3; // 7:5 Transmit word length
|
||||
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
|
||||
Uint16 rsvd2:1; // 15 reserved
|
||||
};
|
||||
|
||||
union XCR1_REG {
|
||||
Uint16 all;
|
||||
struct XCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SRGR2 Sample rate generator control register bit definitions
|
||||
//
|
||||
struct SRGR2_BITS { // bit description
|
||||
Uint16 FPER:12; // 11:0 Frame period
|
||||
Uint16 FSGM:1; // 12 Frame sync generator mode
|
||||
Uint16 CLKSM:1; // 13 Sample rate generator mode
|
||||
Uint16 rsvd:1; // 14 reserved
|
||||
Uint16 GSYNC:1; // 15 CLKG sync
|
||||
};
|
||||
|
||||
union SRGR2_REG {
|
||||
Uint16 all;
|
||||
struct SRGR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// SRGR1 control register bit definitions
|
||||
//
|
||||
struct SRGR1_BITS { // bit description
|
||||
Uint16 CLKGDV:8; // 7:0 CLKG divider
|
||||
Uint16 FWID:8; // 15:8 Frame width
|
||||
};
|
||||
|
||||
union SRGR1_REG {
|
||||
Uint16 all;
|
||||
struct SRGR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// MCR2 Multichannel control register bit definitions
|
||||
//
|
||||
struct MCR2_BITS { // bit description
|
||||
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
|
||||
Uint16 XCBLK:3; // 2:4 Transmit current block
|
||||
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
|
||||
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
|
||||
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
|
||||
Uint16 rsvd:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union MCR2_REG {
|
||||
Uint16 all;
|
||||
struct MCR2_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// MCR1 Multichannel control register bit definitions
|
||||
//
|
||||
struct MCR1_BITS { // bit description
|
||||
Uint16 RMCM:1; // 0 Receive multichannel mode
|
||||
Uint16 rsvd:1; // 1 reserved
|
||||
Uint16 RCBLK:3; // 4:2 Receive current block
|
||||
Uint16 RPABLK:2; // 6:5 Receive partition A Block
|
||||
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
|
||||
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
|
||||
Uint16 rsvd1:6; // 15:10 reserved
|
||||
};
|
||||
|
||||
union MCR1_REG {
|
||||
Uint16 all;
|
||||
struct MCR1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERA control register bit definitions
|
||||
//
|
||||
struct RCERA_BITS { // bit description
|
||||
Uint16 RCEA0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEA1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEA2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEA3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEA4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEA5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEA6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEA7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEA8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEA9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEA10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEA11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEA12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEA13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEA14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEA15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERA_REG {
|
||||
Uint16 all;
|
||||
struct RCERA_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERB control register bit definitions
|
||||
//
|
||||
struct RCERB_BITS { // bit description
|
||||
Uint16 RCEB0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEB1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEB2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEB3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEB4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEB5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEB6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEB7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEB8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEB9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEB10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEB11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEB12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEB13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEB14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEB15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERB_REG {
|
||||
Uint16 all;
|
||||
struct RCERB_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERA control register bit definitions
|
||||
//
|
||||
struct XCERA_BITS { // bit description
|
||||
Uint16 XCERA0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERA1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERA2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERA3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERA4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERA5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERA6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERA7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERA8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERA9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERA10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERA11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERA12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERA13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERA14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERA15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERA_REG {
|
||||
Uint16 all;
|
||||
struct XCERA_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERB control register bit definitions
|
||||
//
|
||||
struct XCERB_BITS { // bit description
|
||||
Uint16 XCERB0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERB1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERB2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERB3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERB4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERB5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERB6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERB7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERB8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERB9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERB10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERB11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERB12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERB13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERB14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERB15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERB_REG {
|
||||
Uint16 all;
|
||||
struct XCERB_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PCR control register bit definitions
|
||||
//
|
||||
struct PCR_BITS { // bit description
|
||||
Uint16 CLKRP:1; // 0 Receive Clock polarity
|
||||
Uint16 CLKXP:1; // 1 Transmit clock polarity
|
||||
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
|
||||
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
|
||||
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
|
||||
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
|
||||
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
|
||||
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
|
||||
Uint16 CLKRM:1; // 8 Receiver Clock Mode
|
||||
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
|
||||
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
|
||||
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
|
||||
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in
|
||||
// this 28x-McBSP
|
||||
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in
|
||||
// this 28x-McBSP
|
||||
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
|
||||
Uint16 rsvd:1 ; // 15 reserved
|
||||
};
|
||||
|
||||
union PCR_REG {
|
||||
Uint16 all;
|
||||
struct PCR_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERC control register bit definitions
|
||||
//
|
||||
struct RCERC_BITS { // bit description
|
||||
Uint16 RCEC0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEC1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEC2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEC3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEC4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEC5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEC6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEC7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEC8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEC9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEC10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEC11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEC12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEC13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEC14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEC15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERC_REG {
|
||||
Uint16 all;
|
||||
struct RCERC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERD control register bit definitions
|
||||
//
|
||||
struct RCERD_BITS { // bit description
|
||||
Uint16 RCED0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCED1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCED2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCED3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCED4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCED5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCED6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCED7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCED8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCED9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCED10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCED11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCED12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCED13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCED14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCED15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERD_REG {
|
||||
Uint16 all;
|
||||
struct RCERD_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERC control register bit definitions
|
||||
//
|
||||
struct XCERC_BITS { // bit description
|
||||
Uint16 XCERC0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERC1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERC2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERC3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERC4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERC5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERC6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERC7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERC8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERC9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERC10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERC11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERC12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERC13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERC14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERC15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERC_REG {
|
||||
Uint16 all;
|
||||
struct XCERC_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERD control register bit definitions
|
||||
//
|
||||
struct XCERD_BITS { // bit description
|
||||
Uint16 XCERD0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERD1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERD2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERD3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERD4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERD5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERD6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERD7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERD8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERD9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERD10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERD11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERD12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERD13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERD14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERD15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERD_REG {
|
||||
Uint16 all;
|
||||
struct XCERD_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERE control register bit definitions
|
||||
//
|
||||
struct RCERE_BITS { // bit description
|
||||
Uint16 RCEE0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEE1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEE2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEE3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEE4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEE5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEE6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEE7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEE8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEE9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEE10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEE11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEE12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEE13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEE14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEE15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERE_REG {
|
||||
Uint16 all;
|
||||
struct RCERE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERF control register bit definitions
|
||||
//
|
||||
struct RCERF_BITS { // bit description
|
||||
Uint16 RCEF0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEF1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEF2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEF3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEF4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEF5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEF6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEF7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEF8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEF9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEF10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEF11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEF12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEF13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEF14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEF15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERF_REG {
|
||||
Uint16 all;
|
||||
struct RCERF_BITS bit;
|
||||
};
|
||||
|
||||
// XCERE control register bit definitions:
|
||||
struct XCERE_BITS { // bit description
|
||||
Uint16 XCERE0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERE1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERE2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERE3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERE4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERE5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERE6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERE7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERE8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERE9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERE10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERE11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERE12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERE13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERE14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERE15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERE_REG {
|
||||
Uint16 all;
|
||||
struct XCERE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERF control register bit definitions
|
||||
//
|
||||
struct XCERF_BITS { // bit description
|
||||
Uint16 XCERF0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERF1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERF2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERF3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERF4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERF5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERF6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERF7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERF8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERF9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERF10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERF11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERF12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERF13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERF14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERF15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERF_REG {
|
||||
Uint16 all;
|
||||
struct XCERF_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// RCERG control register bit definitions
|
||||
//
|
||||
struct RCERG_BITS { // bit description
|
||||
Uint16 RCEG0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEG1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEG2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEG3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEG4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEG5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEG6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEG7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEG8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEG9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEG10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEG11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEG12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEG13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEG14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEG15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERG_REG {
|
||||
Uint16 all;
|
||||
struct RCERG_BITS bit;
|
||||
};
|
||||
|
||||
// RCERH control register bit definitions:
|
||||
struct RCERH_BITS { // bit description
|
||||
Uint16 RCEH0:1; // 0 Receive Channel enable bit
|
||||
Uint16 RCEH1:1; // 1 Receive Channel enable bit
|
||||
Uint16 RCEH2:1; // 2 Receive Channel enable bit
|
||||
Uint16 RCEH3:1; // 3 Receive Channel enable bit
|
||||
Uint16 RCEH4:1; // 4 Receive Channel enable bit
|
||||
Uint16 RCEH5:1; // 5 Receive Channel enable bit
|
||||
Uint16 RCEH6:1; // 6 Receive Channel enable bit
|
||||
Uint16 RCEH7:1; // 7 Receive Channel enable bit
|
||||
Uint16 RCEH8:1; // 8 Receive Channel enable bit
|
||||
Uint16 RCEH9:1; // 9 Receive Channel enable bit
|
||||
Uint16 RCEH10:1; // 10 Receive Channel enable bit
|
||||
Uint16 RCEH11:1; // 11 Receive Channel enable bit
|
||||
Uint16 RCEH12:1; // 12 Receive Channel enable bit
|
||||
Uint16 RCEH13:1; // 13 Receive Channel enable bit
|
||||
Uint16 RCEH14:1; // 14 Receive Channel enable bit
|
||||
Uint16 RCEH15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union RCERH_REG {
|
||||
Uint16 all;
|
||||
struct RCERH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERG control register bit definitions
|
||||
//
|
||||
struct XCERG_BITS { // bit description
|
||||
Uint16 XCERG0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCERG1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCERG2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCERG3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCERG4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCERG5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCERG6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCERG7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCERG8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCERG9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCERG10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCERG11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCERG12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCERG13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCERG14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCERG15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERG_REG {
|
||||
Uint16 all;
|
||||
struct XCERG_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// XCERH control register bit definitions
|
||||
//
|
||||
struct XCERH_BITS { // bit description
|
||||
Uint16 XCEH0:1; // 0 Receive Channel enable bit
|
||||
Uint16 XCEH1:1; // 1 Receive Channel enable bit
|
||||
Uint16 XCEH2:1; // 2 Receive Channel enable bit
|
||||
Uint16 XCEH3:1; // 3 Receive Channel enable bit
|
||||
Uint16 XCEH4:1; // 4 Receive Channel enable bit
|
||||
Uint16 XCEH5:1; // 5 Receive Channel enable bit
|
||||
Uint16 XCEH6:1; // 6 Receive Channel enable bit
|
||||
Uint16 XCEH7:1; // 7 Receive Channel enable bit
|
||||
Uint16 XCEH8:1; // 8 Receive Channel enable bit
|
||||
Uint16 XCEH9:1; // 9 Receive Channel enable bit
|
||||
Uint16 XCEH10:1; // 10 Receive Channel enable bit
|
||||
Uint16 XCEH11:1; // 11 Receive Channel enable bit
|
||||
Uint16 XCEH12:1; // 12 Receive Channel enable bit
|
||||
Uint16 XCEH13:1; // 13 Receive Channel enable bit
|
||||
Uint16 XCEH14:1; // 14 Receive Channel enable bit
|
||||
Uint16 XCEH15:1; // 15 Receive Channel enable bit
|
||||
};
|
||||
|
||||
union XCERH_REG {
|
||||
Uint16 all;
|
||||
struct XCERH_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP Interrupt enable register for RINT/XINT
|
||||
//
|
||||
struct MFFINT_BITS { // bits description
|
||||
Uint16 XINT:1; // 0 XINT interrupt enable
|
||||
Uint16 rsvd1:1; // 1 reserved
|
||||
Uint16 RINT:1; // 2 RINT interrupt enable
|
||||
Uint16 rsvd2:13; // 15:3 reserved
|
||||
};
|
||||
|
||||
union MFFINT_REG {
|
||||
Uint16 all;
|
||||
struct MFFINT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP Register File
|
||||
//
|
||||
struct MCBSP_REGS {
|
||||
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
|
||||
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
|
||||
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
|
||||
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
|
||||
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
|
||||
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
|
||||
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
|
||||
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
|
||||
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
|
||||
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
|
||||
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
|
||||
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
|
||||
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
|
||||
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
|
||||
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
|
||||
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
|
||||
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
|
||||
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
|
||||
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
|
||||
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
|
||||
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
|
||||
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
|
||||
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
|
||||
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
|
||||
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
|
||||
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
|
||||
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
|
||||
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
|
||||
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
|
||||
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
|
||||
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
|
||||
Uint16 rsvd1[4]; // reserved
|
||||
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for
|
||||
// RINT/XINT
|
||||
Uint16 rsvd2; // reserved
|
||||
};
|
||||
|
||||
//
|
||||
// McBSP External References & Function Declarations
|
||||
//
|
||||
extern volatile struct MCBSP_REGS McbspaRegs;
|
||||
extern volatile struct MCBSP_REGS McbspbRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_MCBSP_H definition
|
||||
|
||||
//
|
||||
// No more
|
||||
//
|
||||
|
||||
@@ -0,0 +1,397 @@
|
||||
// TI File $Revision: /main/11 $
|
||||
// Checkin $Date: June 23, 2008 11:34:15 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_DMA.h
|
||||
//
|
||||
// TITLE: DSP2833x DMA Module Register Bit Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: 2833x/2823x Header Files V1.32 $
|
||||
// $Release Date: June 28, 2010 $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP2833x_DMA_H
|
||||
#define DSP2833x_DMA_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Channel MODE register bit definitions
|
||||
//
|
||||
struct MODE_BITS { // bits description
|
||||
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
|
||||
// 0 no interrupt
|
||||
// 1 SEQ1INT & ADCSYNC
|
||||
// 2 SEQ2INT
|
||||
// 3 XINT1
|
||||
// 4 XINT2
|
||||
// 5 XINT3
|
||||
// 6 XINT4
|
||||
// 7 XINT5
|
||||
// 8 XINT6
|
||||
// 9 XINT7
|
||||
// 10 XINT13
|
||||
// 11 TINT0
|
||||
// 12 TINT1
|
||||
// 13 TINT2
|
||||
// 14 MXEVTA & MXSYNCA
|
||||
// 15 MREVTA & MRSYNCA
|
||||
// 16 MXEVTB & MXSYNCB
|
||||
// 17 MREVTB & MRSYNCB
|
||||
// 18 ePWM1SOCA
|
||||
// 19 ePWM1SOCB
|
||||
// 20 ePWM2SOCA
|
||||
// 21 ePWM2SOCB
|
||||
// 22 ePWM3SOCA
|
||||
// 23 ePWM3SOCB
|
||||
// 24 ePWM4SOCA
|
||||
// 25 ePWM4SOCB
|
||||
// 26 ePWM5SOCA
|
||||
// 27 ePWM5SOCB
|
||||
// 28 ePWM6SOCA
|
||||
// 29 ePWM6SOCB
|
||||
// 30:31 no interrupt
|
||||
Uint16 rsvd1:2; // 6:5 (R=0:0)
|
||||
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
|
||||
// 0 overflow interrupt disabled
|
||||
// 1 overflow interrupt enabled
|
||||
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
|
||||
// 0 peripheral interrupt disabled
|
||||
// 1 peripheral interrupt enabled
|
||||
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
|
||||
// 0 generate interrupt at beginning of new
|
||||
// transfer
|
||||
// 1 generate interrupt at end of transfer
|
||||
Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
|
||||
// 0 only interrupt event triggers single
|
||||
// burst transfer
|
||||
// 1 first interrupt triggers burst,
|
||||
// continue until transfer count is zero
|
||||
Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
|
||||
// 0 stop when transfer count is zero
|
||||
// 1 re-initialize when transfer count is
|
||||
// zero
|
||||
Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
|
||||
// 0 ignore selected interrupt sync signal
|
||||
// 1 enable selected interrupt sync signal
|
||||
Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
|
||||
// 0 sync signal controls source wrap
|
||||
// counter
|
||||
// 1 sync signal controls destination wrap
|
||||
// counter
|
||||
Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
|
||||
// 0 16-bit data transfer size
|
||||
// 1 32-bit data transfer size
|
||||
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
|
||||
// 0 channel interrupt disabled
|
||||
// 1 channel interrupt enabled
|
||||
};
|
||||
|
||||
union MODE_REG {
|
||||
Uint16 all;
|
||||
struct MODE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Channel CONTROL register bit definitions
|
||||
//
|
||||
struct CONTROL_BITS { // bits description
|
||||
Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
|
||||
Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
|
||||
Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
|
||||
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
|
||||
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
|
||||
Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
|
||||
Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
|
||||
Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
|
||||
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
|
||||
// 0 no interrupt pending
|
||||
// 1 interrupt pending
|
||||
Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
|
||||
// 0 no sync pending
|
||||
// 1 sync pending
|
||||
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
|
||||
// 0 no sync error
|
||||
// 1 sync error detected
|
||||
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
|
||||
// 0 no transfer in progress or pending
|
||||
// 1 transfer in progress or pending
|
||||
Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
|
||||
// 0 no burst in progress or pending
|
||||
// 1 burst in progress or pending
|
||||
Uint16 RUNSTS:1; // 13 Run Status Bit (R):
|
||||
// 0 channel not running or halted
|
||||
// 1 channel running
|
||||
Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
|
||||
// 0 no overflow event
|
||||
// 1 overflow event
|
||||
Uint16 rsvd1:1; // 15 (R=0)
|
||||
};
|
||||
|
||||
union CONTROL_REG {
|
||||
Uint16 all;
|
||||
struct CONTROL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DMACTRL register bit definitions
|
||||
//
|
||||
struct DMACTRL_BITS { // bits description
|
||||
Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
|
||||
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
|
||||
Uint16 rsvd1:14; // 15:2 (R=0:0)
|
||||
};
|
||||
|
||||
union DMACTRL_REG {
|
||||
Uint16 all;
|
||||
struct DMACTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DEBUGCTRL register bit definitions
|
||||
//
|
||||
struct DEBUGCTRL_BITS { // bits description
|
||||
Uint16 rsvd1:15; // 14:0 (R=0:0)
|
||||
Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
|
||||
// 0 halt after current read-write operation
|
||||
// 1 continue running
|
||||
};
|
||||
|
||||
union DEBUGCTRL_REG {
|
||||
Uint16 all;
|
||||
struct DEBUGCTRL_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PRIORITYCTRL1 register bit definitions
|
||||
//
|
||||
struct PRIORITYCTRL1_BITS { // bits description
|
||||
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
|
||||
// 0 same priority as all other channels
|
||||
// 1 highest priority channel
|
||||
Uint16 rsvd1:15; // 15:1 (R=0:0)
|
||||
};
|
||||
|
||||
union PRIORITYCTRL1_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYCTRL1_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// PRIORITYSTAT register bit definitions:
|
||||
//
|
||||
struct PRIORITYSTAT_BITS { // bits description
|
||||
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
|
||||
// 0,0,0 no channel active
|
||||
// 0,0,1 Ch1 channel active
|
||||
// 0,1,0 Ch2 channel active
|
||||
// 0,1,1 Ch3 channel active
|
||||
// 1,0,0 Ch4 channel active
|
||||
// 1,0,1 Ch5 channel active
|
||||
// 1,1,0 Ch6 channel active
|
||||
Uint16 rsvd1:1; // 3 (R=0)
|
||||
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
|
||||
// 0,0,0 no channel active & interrupted by Ch1
|
||||
// 0,0,1 cannot occur
|
||||
// 0,1,0 Ch2 was active and interrupted by Ch1
|
||||
// 0,1,1 Ch3 was active and interrupted by Ch1
|
||||
// 1,0,0 Ch4 was active and interrupted by Ch1
|
||||
// 1,0,1 Ch5 was active and interrupted by Ch1
|
||||
// 1,1,0 Ch6 was active and interrupted by Ch1
|
||||
Uint16 rsvd2:9; // 15:7 (R=0:0)
|
||||
};
|
||||
|
||||
union PRIORITYSTAT_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYSTAT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Burst Size
|
||||
//
|
||||
struct BURST_SIZE_BITS { // bits description
|
||||
Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union BURST_SIZE_REG {
|
||||
Uint16 all;
|
||||
struct BURST_SIZE_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// Burst Count
|
||||
//
|
||||
struct BURST_COUNT_BITS { // bits description
|
||||
Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
|
||||
Uint16 rsvd1:11; // 15:5 reserved
|
||||
};
|
||||
|
||||
union BURST_COUNT_REG {
|
||||
Uint16 all;
|
||||
struct BURST_COUNT_BITS bit;
|
||||
};
|
||||
|
||||
//
|
||||
// DMA Channel Registers:
|
||||
//
|
||||
struct CH_REGS {
|
||||
union MODE_REG MODE; // Mode Register
|
||||
union CONTROL_REG CONTROL; // Control Register
|
||||
|
||||
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
|
||||
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
|
||||
|
||||
//
|
||||
// Source Burst Step Register
|
||||
//
|
||||
int16 SRC_BURST_STEP;
|
||||
|
||||
//
|
||||
// Destination Burst Step Register
|
||||
//
|
||||
int16 DST_BURST_STEP;
|
||||
|
||||
Uint16 TRANSFER_SIZE; // Transfer Size Register
|
||||
Uint16 TRANSFER_COUNT; // Transfer Count Register
|
||||
|
||||
//
|
||||
// Source Transfer Step Register
|
||||
//
|
||||
int16 SRC_TRANSFER_STEP;
|
||||
|
||||
//
|
||||
// Destination Transfer Step Register
|
||||
//
|
||||
int16 DST_TRANSFER_STEP;
|
||||
|
||||
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
|
||||
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
|
||||
int16 SRC_WRAP_STEP; // Source Wrap Step Register
|
||||
|
||||
//
|
||||
// Destination Wrap Size Register
|
||||
//
|
||||
Uint16 DST_WRAP_SIZE;
|
||||
|
||||
//
|
||||
// Destination Wrap Count Register
|
||||
//
|
||||
Uint16 DST_WRAP_COUNT;
|
||||
|
||||
//
|
||||
// Destination Wrap Step Register
|
||||
//
|
||||
int16 DST_WRAP_STEP;
|
||||
|
||||
//
|
||||
// Source Begin Address Shadow Register
|
||||
//
|
||||
Uint32 SRC_BEG_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Source Address Shadow Register
|
||||
//
|
||||
Uint32 SRC_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Source Begin Address Active Register
|
||||
//
|
||||
Uint32 SRC_BEG_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Source Address Active Register
|
||||
//
|
||||
Uint32 SRC_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Destination Begin Address Shadow Register
|
||||
//
|
||||
Uint32 DST_BEG_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Destination Address Shadow Register
|
||||
//
|
||||
Uint32 DST_ADDR_SHADOW;
|
||||
|
||||
//
|
||||
// Destination Begin Address Active Register
|
||||
//
|
||||
Uint32 DST_BEG_ADDR_ACTIVE;
|
||||
|
||||
//
|
||||
// Destination Address Active Register
|
||||
//
|
||||
Uint32 DST_ADDR_ACTIVE;
|
||||
};
|
||||
|
||||
//
|
||||
// DMA Registers
|
||||
//
|
||||
struct DMA_REGS {
|
||||
union DMACTRL_REG DMACTRL; // DMA Control Register
|
||||
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
|
||||
Uint16 rsvd0; // reserved
|
||||
Uint16 rsvd1; //
|
||||
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
|
||||
Uint16 rsvd2; //
|
||||
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
|
||||
Uint16 rsvd3[25]; //
|
||||
struct CH_REGS CH1; // DMA Channel 1 Registers
|
||||
struct CH_REGS CH2; // DMA Channel 2 Registers
|
||||
struct CH_REGS CH3; // DMA Channel 3 Registers
|
||||
struct CH_REGS CH4; // DMA Channel 4 Registers
|
||||
struct CH_REGS CH5; // DMA Channel 5 Registers
|
||||
struct CH_REGS CH6; // DMA Channel 6 Registers
|
||||
};
|
||||
|
||||
//
|
||||
// External References & Function Declarations
|
||||
//
|
||||
extern volatile struct DMA_REGS DmaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of DSP2833x_DMA_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
|
||||
// TI File $Revision: /main/1 $
|
||||
// Checkin $Date: April 22, 2008 14:35:56 $
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP28x_Project.h
|
||||
//
|
||||
// TITLE: DSP28x Project Headerfile and Examples Include File
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef DSP28x_PROJECT_H
|
||||
#define DSP28x_PROJECT_H
|
||||
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
#endif // end of DSP28x_PROJECT_H definition
|
||||
|
||||
@@ -0,0 +1,219 @@
|
||||
#ifndef SOURCE_STATE_H_
|
||||
#define SOURCE_STATE_H_
|
||||
|
||||
#define COMM_TIME_OUT_COUNT (3000U) // 3sec
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_ADC_ENGINE_HEATER_V = 0U, // 0
|
||||
IDX_ADC_GLOW_PLUG_V, // 1
|
||||
IDX_ADC_SOLENOID_V, // 2
|
||||
IDX_ADC_FUEL_PUMP_V, // 3
|
||||
IDX_ADC_COOLANT_PUMP_V, // 4
|
||||
IDX_ADC_FAN1_V, // 5
|
||||
IDX_ADC_FAN2_V, // 6
|
||||
IDX_ADC_ENGINE_HEATER_I, // 7
|
||||
IDX_ADC_GLOW_PLUG_I, // 8
|
||||
IDX_ADC_SOLENOID_I, // 9
|
||||
IDX_ADC_FUEL_PUMP_I, // 10
|
||||
IDX_ADC_COOLANT_PUMP_I, // 11
|
||||
IDX_ADC_FAN1_I, // 12
|
||||
IDX_ADC_FAN2_I, // 13
|
||||
IDX_ADC_MAX
|
||||
} E_IDX_ADC;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_WARNING_GCU_PCB_OT = 0U,
|
||||
IDX_WARNING_GCU_FET_OT,
|
||||
IDX_WARNING_GCU_WINDING1_OH,
|
||||
IDX_WARNING_GCU_WINDING2_OH,
|
||||
IDX_WARNING_GCU_MAX
|
||||
} E_IDX_WARNING_GCU;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_WARNING_ECU_ENGINE_OH = 0U,
|
||||
IDX_WARNING_ECU_RESERVED,
|
||||
IDX_WARNING_ECU_LO_OIL_PRESS,
|
||||
IDX_WARNING_ECU_INTAKE_OH,
|
||||
IDX_WARNING_ECU_INTAKE_LO_PRESS,
|
||||
IDX_WARNING_ECU_ENGINE_LO_TEMP,
|
||||
IDX_WARNING_ECU_ENGINE_SENSOR,
|
||||
IDX_WARNING_ECU_DEFAULT_ACTIVE,
|
||||
IDX_WARNING_ECU_MAX
|
||||
} E_IDX_WARNING_ECU;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_DCU_CAR_COMM = 0U, // 0
|
||||
IDX_FAULT_DCU_GCU_COMM, // 1
|
||||
IDX_FAULT_DCU_ECU_COMM, // 2
|
||||
IDX_FAULT_DCU_RPM_ERR, // 3
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4
|
||||
IDX_FAULT_DCU_GLOW_PLUG_OC, // 5
|
||||
IDX_FAULT_DCU_SOLENOID_OC, // 6
|
||||
IDX_FAULT_DCU_FUEL_PUMP_OC, // 7
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8
|
||||
IDX_FAULT_DCU_FAN1_OC, // 9
|
||||
IDX_FAULT_DCU_FAN2_OC, // 10
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11
|
||||
IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12
|
||||
IDX_FAULT_DCU_GLOW_PLUG_UV, // 13
|
||||
IDX_FAULT_DCU_GLOW_PLUG_OV, // 14
|
||||
IDX_FAULT_DCU_SOLENOID_UV, // 15
|
||||
IDX_FAULT_DCU_SOLENOID_OV, // 16
|
||||
IDX_FAULT_DCU_FUEL_PUMP_UV, // 17
|
||||
IDX_FAULT_DCU_FUEL_PUMP_OV, // 18
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19
|
||||
IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20
|
||||
IDX_FAULT_DCU_FAN1_UV, // 21
|
||||
IDX_FAULT_DCU_FAN1_OV, // 22
|
||||
IDX_FAULT_DCU_FAN2_UV, // 23
|
||||
IDX_FAULT_DCU_FAN2_OV, // 24
|
||||
IDX_FAULT_DCU_CRANKING_FAIL, // 25
|
||||
IDX_FAULT_DCU_MAX
|
||||
} E_IDX_DCU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_GCU_HWTRIP = 0U, // 0
|
||||
IDX_FAULT_GCU_HWIGBT, // 1
|
||||
IDX_FAULT_GCU_HW_DC, // 2
|
||||
IDX_FAULT_GCU_GEN_OCU, // 3
|
||||
IDX_FAULT_GCU_GEN_OCV, // 4
|
||||
IDX_FAULT_GCU_GEN_OCW, // 5
|
||||
IDX_FAULT_GCU_DC_OV, // 6
|
||||
IDX_FAULT_GCU_DC_OC, // 7
|
||||
|
||||
IDX_FAULT_GCU_CRANK_OC, // 8
|
||||
IDX_FAULT_GCU_PCB_OT, // 9
|
||||
IDX_FAULT_GCU_FET_OT, // 10
|
||||
IDX_FAULT_GCU_WINDING1_OH, // 11
|
||||
IDX_FAULT_GCU_WINDING2_OH, // 12
|
||||
IDX_FAULT_GCU_GEN_OS, // 13
|
||||
IDX_FAULT_GCU_RES_IC, // 14
|
||||
IDX_FAULT_GCU_RES_PRTY, // 15
|
||||
IDX_FAULT_GCU_MAX
|
||||
} E_IDX_GCU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_FAULT_ECU_OIL_MS = 0U, // 0
|
||||
IDX_FAULT_ECU_INT_OH, // 1
|
||||
IDX_FAULT_ECU_ENG_OH, // 2
|
||||
IDX_FAULT_ECU_ACTUATOR, // 3
|
||||
IDX_FAULT_ECU_RPM_SIG, // 4
|
||||
IDX_FAULT_ECU_ENG_SF, // 5
|
||||
IDX_FAULT_MAX
|
||||
} E_IDX_ECU_FAULT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IDX_KEY_MAIN_POWER = 0U, // 0
|
||||
IDX_KEY_ARR_UP, // 1
|
||||
IDX_KEY_ARR_DOWN, // 2
|
||||
IDX_KEY_ENTER, // 3
|
||||
IDX_KEY_MENU, // 4
|
||||
IDX_KEY_ENG_START_STOP, // 5
|
||||
IDX_KEY_EMERGENCY, // 6
|
||||
IDX_KEY_REMOTE_START, // 7
|
||||
IDX_KEY_REMOTE_STOP, // 8
|
||||
IDX_KEY_REMOTE_EMERGENCY, // 9
|
||||
IDX_KEY_BATTLE_MODE, // 10
|
||||
IDX_KEY_MAX // 11
|
||||
} E_IDX_KEY;
|
||||
|
||||
typedef struct ClassKeyHandler
|
||||
{
|
||||
E_IDX_KEY eKey;
|
||||
void (*pAction) (void);
|
||||
} CKeyHandler;
|
||||
|
||||
typedef struct ClassAdcOperValue
|
||||
{
|
||||
Uint16 uiAdcOffsetIndex;
|
||||
Uint16 uiOffsetAdjustStart;
|
||||
} CAdcOperValue;
|
||||
|
||||
typedef struct ClassAdcCalcValue
|
||||
{
|
||||
float32 fLpfValue;
|
||||
float32 fSampledValue;
|
||||
float32 fSampledSum;
|
||||
float32 fTempAdcOffset;
|
||||
float32 fGain;
|
||||
float32 fOffset;
|
||||
Uint16 uiSamplingCount;
|
||||
int16 iAdcValue;
|
||||
} CAdcCalcValue;
|
||||
|
||||
typedef struct ClassWarningOperValue
|
||||
{
|
||||
float32 fCheckLimit; // 경고 한계 값
|
||||
Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중
|
||||
Uint16 uiDetectCount; // 경고 검출 카운터
|
||||
Uint16 uiReleaseCount; // 경고 해제 카운터
|
||||
Uint16 uiCheckTime;
|
||||
} CWarningOperValue;
|
||||
|
||||
typedef struct ClassAlarmOperValue
|
||||
{
|
||||
float32 fCheckLimit;
|
||||
float32 fFaultValue;
|
||||
Uint16 uiCheck;
|
||||
Uint16 uiCheckCount;
|
||||
Uint16 uiCheckTime;
|
||||
} CAlarmOperValue;
|
||||
|
||||
typedef struct ClassKeyList
|
||||
{
|
||||
Uint16 MainPower;
|
||||
Uint16 ArrowUp;
|
||||
Uint16 ArrowDown;
|
||||
Uint16 Enter;
|
||||
Uint16 Menu;
|
||||
Uint16 EngineStartStop;
|
||||
Uint16 Emergency;
|
||||
Uint16 BattleMode;
|
||||
} CKeyList;
|
||||
|
||||
typedef struct ClassKeyOperValue
|
||||
{
|
||||
Uint16 uiKeyWaitCount;
|
||||
Uint16 uiPreviousKey;
|
||||
Uint16 uiKeyWait;
|
||||
CKeyList KeyList;
|
||||
} CKeyOperValue;
|
||||
|
||||
extern CAdcCalcValue Adc_EngineHeater_V;
|
||||
extern CAdcCalcValue Adc_GlowPlug_V;
|
||||
extern CAdcCalcValue Adc_Solenoid_V;
|
||||
extern CAdcCalcValue Adc_FuelPump_V;
|
||||
extern CAdcCalcValue Adc_CoolantPump_V;
|
||||
extern CAdcCalcValue Adc_Fan1_V;
|
||||
extern CAdcCalcValue Adc_Fan2_V;
|
||||
|
||||
extern CAdcCalcValue Adc_EngineHeater_I;
|
||||
extern CAdcCalcValue Adc_GlowPlug_I;
|
||||
extern CAdcCalcValue Adc_Solenoid_I;
|
||||
extern CAdcCalcValue Adc_FuelPump_I;
|
||||
extern CAdcCalcValue Adc_CoolantPump_I;
|
||||
extern CAdcCalcValue Adc_Fan1_I;
|
||||
extern CAdcCalcValue Adc_Fan2_I;
|
||||
|
||||
extern CAdcOperValue AdcOperValue;
|
||||
extern CKeyOperValue KeyOperValue;
|
||||
|
||||
extern Uint32 ulDcuTotalAlarm;
|
||||
extern Uint32 ulGcuTotalAlarm;
|
||||
extern Uint32 ulEcuTotalAlarm;
|
||||
|
||||
interrupt void CAdcInterrupt(void);
|
||||
void CAlarmProcedure(void);
|
||||
void CInitAdc(void);
|
||||
void CKeyCheckProcedure(void);
|
||||
void CKeyWaitCount(void);
|
||||
void CDisplayAlarmPopup(void);
|
||||
|
||||
#endif /* SOURCE_STATE_H_ */
|
||||
@@ -0,0 +1,282 @@
|
||||
{
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_GLOBALPROTOTYPES.H": [
|
||||
"5087ebaeb4c90cf7a0a088e87497fcc2_",
|
||||
false,
|
||||
true,
|
||||
"22571950",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_GlobalPrototypes.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_EXAMPLES.H": [
|
||||
"886250910e6bddafd7e95146e1f5f406_",
|
||||
false,
|
||||
true,
|
||||
"f93bad3c",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_Examples.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_ADC.H": [
|
||||
"f4c48238da22647d03d8d119102df0e8_",
|
||||
false,
|
||||
true,
|
||||
"1b54d9f4",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Adc.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_SYSCTRL.H": [
|
||||
"dd8d114f9d4090743a4f2678af8cc2dd_",
|
||||
false,
|
||||
true,
|
||||
"eab4c7f8",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_SysCtrl.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DMA.H": [
|
||||
"fe4f1419c3c067e59d2698ac4835fd68_",
|
||||
false,
|
||||
true,
|
||||
"ab81ed1e",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_DMA.h"
|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/_TI_CONFIG.H": [
|
||||
"_bbbf7244a602c743d7694c03650a07cc",
|
||||
true,
|
||||
false,
|
||||
"a649eb66",
|
||||
"C:/ti/ccs1281/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/_ti_config.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/OPER.C": [
|
||||
"d4d10244d3cbba60805c13f0c6e2a0c2",
|
||||
false,
|
||||
false,
|
||||
"ed3e6820",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Oper.c"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/STATE.C": [
|
||||
"28df5e74bd8ddae9115a4fb8166fcf29",
|
||||
false,
|
||||
false,
|
||||
"43294764",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/State.c"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/STATE.H": [
|
||||
"ffd39a99ec5176ce64cc758f34a11f56",
|
||||
false,
|
||||
false,
|
||||
"c4b929cf",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/State.h"
|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/STRING.H": [
|
||||
"_37542ab4f6589d7027e75c2a30519b32",
|
||||
true,
|
||||
false,
|
||||
"931833a5",
|
||||
"C:/ti/ccs1281/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/string.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_DEFAULTISR.H": [
|
||||
"d75fd8a9a8f6a4d86ed87452f4b37e5e_",
|
||||
false,
|
||||
true,
|
||||
"2036dd9a",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_DefaultIsr.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/OPER.H": [
|
||||
"04e43fb5be4196c8a44f0c60a3b1677e",
|
||||
false,
|
||||
false,
|
||||
"5cd0d37f",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Oper.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/MAIN.C": [
|
||||
"b5d424479a96c0e4f4fc5ca18a4ffdc3",
|
||||
false,
|
||||
false,
|
||||
"646f103c",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/main.c"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_EPWM_DEFINES.H": [
|
||||
"1784ef9f6544b15ca51cc304251630b3_",
|
||||
false,
|
||||
true,
|
||||
"f4f62f4b",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_EPwm_defines.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_ECAN.H": [
|
||||
"70868bbf531d9aa79c87c32e4788ee4e_",
|
||||
false,
|
||||
true,
|
||||
"3e22f84d",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_ECan.h"
|
||||
],
|
||||
"C:/TI/CCS1281/CCS/TOOLS/COMPILER/TI-CGT-C2000_22.6.1.LTS/INCLUDE/LINKAGE.H": [
|
||||
"_bb64ad2ba728094bd1eb236fd1301908",
|
||||
true,
|
||||
false,
|
||||
"d0b2ad68",
|
||||
"C:/ti/ccs1281/ccs/tools/compiler/ti-cgt-c2000_22.6.1.LTS/include/linkage.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_CPUTIMERS.H": [
|
||||
"c3ce07430b9437ddee99bdc151b20aae_",
|
||||
false,
|
||||
true,
|
||||
"33c71996",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_CpuTimers.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_I2C_DEFINES.H": [
|
||||
"3932151096406d1bbe5a24cc2d6f26ea_",
|
||||
false,
|
||||
true,
|
||||
"b4ba7982",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/common/include/DSP2833x_I2c_defines.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_GPIO.H": [
|
||||
"7db20b7d65499aa92f223811bf4e2ee0_",
|
||||
false,
|
||||
true,
|
||||
"77654875",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_Gpio.h"
|
||||
],
|
||||
"C:/TI/PROJECT/K2APU_DCU_V019/SOURCE/COMM.H": [
|
||||
"b677a266db0b1d5e23cf54c2eb3101a8",
|
||||
false,
|
||||
false,
|
||||
"b48ea0b5",
|
||||
"C:/ti/Project/K2APU_DCU_v019/Source/Comm.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_PIEVECT.H": [
|
||||
"7d86d3df0c09119c711baf3e0fc3da7a_",
|
||||
false,
|
||||
true,
|
||||
"f09c16ca",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_PieVect.h"
|
||||
],
|
||||
"C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DEVEMU.H": [
|
||||
"3639c9c8a3264ec88cb369751be62a8d_",
|
||||
false,
|
||||
true,
|
||||
"3ccf955e",
|
||||
"C:/ti/c2000/C2000Ware_4_03_00_00/device_support/f2833x/headers/include/DSP2833x_DevEmu.h"
|
||||
],
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245
Source/.staticdata/.previous/20260407_213608/K2DCU/project.json
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Normal file
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Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user