diff --git a/.STATICFILE b/.STATICFILE new file mode 100644 index 0000000..889740c --- /dev/null +++ b/.STATICFILE @@ -0,0 +1,69 @@ +{ + "REANALYZE": false, + "WORKING_DIR": "C:\\ti\\Project\\K2APU_DCU_v005\\.staticdata", + "COMPILER_INSTALLATION_PATH": [], + "PRE_BUILD_COMMAND": "", + "COMMAND": [], + "STATIC_SERVER_ADDRESS": "gw.seoltech.com:8080", + "PROJECT_KEY": "K2DCU", + "TOOLCHAIN_FILENAME": "TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf", + "PARSING": { + "C": { + "include": [ + "C:\\ti\\ccs1281\\ccs\\tools\\compiler\\ti-cgt-c2000_22.6.2.LTS\\include" + ], + "conf": [ + "cs_encoding", + "cs_define_macro_value=__has_include(STR);0" + ], + "removes": [] + }, + "CPP": { + "include": [ + "C:\\ti\\ccs1281\\ccs\\tools\\compiler\\ti-cgt-c2000_22.6.2.LTS\\include" + ], + "conf": [ + "cs_encoding", + "cs_define_macro_value=__has_include(STR);0" + ], + "removes": [] + } + }, + "USER_DEFINED_EXTENSIONS": { + "header": [ + ".h", + ".H", + ".hpp", + ".HPP", + ".tcc", + ".inl", + ".INL" + ], + "source": [ + ".c", + ".C", + ".c++", + ".C++", + ".cpp", + ".CPP", + ".cxx", + ".CXX", + ".cc", + ".CC", + ".cp", + ".CP" + ], + "object": [ + ".o", + ".O", + ".lo", + ".obj", + ".OBJ" + ] + }, + "MULTI_PROCESSOR": false, + "EXCLUSIONS": [], + "EXTRA_OPTIONS": { + "SPECIFIED_ANALYSIS_AGENT_VERSION": "" + } +} \ No newline at end of file diff --git a/.ccsproject b/.ccsproject new file mode 100644 index 0000000..0847cd1 --- /dev/null +++ b/.ccsproject @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/.clangd b/.clangd new file mode 100644 index 0000000..8b17bdc --- /dev/null +++ b/.clangd @@ -0,0 +1,8 @@ +# This is an auto-generated file - do not add it to source-control + +CompileFlags: + CompilationDatabase: Debug/.clangd + +Diagnostics: + Suppress: '*' + diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..9402203 --- /dev/null +++ b/.cproject @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/.launches/APU_GCU_20241206_STATIC_OK.launch b/.launches/APU_GCU_20241206_STATIC_OK.launch new file mode 100644 index 0000000..7e2e582 --- /dev/null +++ b/.launches/APU_GCU_20241206_STATIC_OK.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.launches/GCU.launch b/.launches/GCU.launch new file mode 100644 index 0000000..5aa3751 --- /dev/null +++ b/.launches/GCU.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_20240518.launch b/.launches/GCU_20240518.launch new file mode 100644 index 0000000..9718ac9 --- /dev/null +++ b/.launches/GCU_20240518.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_20240701.launch b/.launches/GCU_20240701.launch new file mode 100644 index 0000000..48cd375 --- /dev/null +++ b/.launches/GCU_20240701.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_20240704_HW3.launch b/.launches/GCU_20240704_HW3.launch new file mode 100644 index 0000000..0aafd8e --- /dev/null +++ b/.launches/GCU_20240704_HW3.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_20240704_HW4.launch b/.launches/GCU_20240704_HW4.launch new file mode 100644 index 0000000..c1838b9 --- /dev/null +++ b/.launches/GCU_20240704_HW4.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_20240704_HW4_V1.launch b/.launches/GCU_20240704_HW4_V1.launch new file mode 100644 index 0000000..302ae10 --- /dev/null +++ b/.launches/GCU_20240704_HW4_V1.launch @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/.launches/GCU_240419.launch b/.launches/GCU_240419.launch new file mode 100644 index 0000000..b5763de --- /dev/null +++ b/.launches/GCU_240419.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v001.launch b/.launches/K2APU_DCU_v001.launch new file mode 100644 index 0000000..a19a1ee --- /dev/null +++ b/.launches/K2APU_DCU_v001.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v005.launch b/.launches/K2APU_DCU_v005.launch new file mode 100644 index 0000000..5f98c3e --- /dev/null +++ b/.launches/K2APU_DCU_v005.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v006.launch b/.launches/K2APU_DCU_v006.launch new file mode 100644 index 0000000..64a73af --- /dev/null +++ b/.launches/K2APU_DCU_v006.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v016.launch b/.launches/K2APU_DCU_v016.launch new file mode 100644 index 0000000..005e2bb --- /dev/null +++ b/.launches/K2APU_DCU_v016.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v017.launch b/.launches/K2APU_DCU_v017.launch new file mode 100644 index 0000000..ed4ee3a --- /dev/null +++ b/.launches/K2APU_DCU_v017.launch @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v018.launch b/.launches/K2APU_DCU_v018.launch new file mode 100644 index 0000000..a05d91b --- /dev/null +++ b/.launches/K2APU_DCU_v018.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v019.launch b/.launches/K2APU_DCU_v019.launch new file mode 100644 index 0000000..23ee06e --- /dev/null +++ b/.launches/K2APU_DCU_v019.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.launches/K2APU_DCU_v019_IDLE_SEQ_MOD_260413.launch b/.launches/K2APU_DCU_v019_IDLE_SEQ_MOD_260413.launch new file mode 100644 index 0000000..71166d9 --- /dev/null +++ b/.launches/K2APU_DCU_v019_IDLE_SEQ_MOD_260413.launch @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/.project b/.project new file mode 100644 index 0000000..b2585fd --- /dev/null +++ b/.project @@ -0,0 +1,27 @@ + + + K2APU_DCU_v019_IDLE_SEQ_MOD_260413 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..98b6350 --- /dev/null +++ b/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/.settings/org.eclipse.cdt.debug.core.prefs b/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..58d4fb2 --- /dev/null +++ b/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..8d086a3 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,14 @@ +eclipse.preferences.version=1 +encoding//Debug/Description/subdir_rules.mk=UTF-8 +encoding//Debug/Description/subdir_vars.mk=UTF-8 +encoding//Debug/Lib/Src/subdir_rules.mk=UTF-8 +encoding//Debug/Lib/Src/subdir_vars.mk=UTF-8 +encoding//Debug/Lib/asm/subdir_rules.mk=UTF-8 +encoding//Debug/Lib/asm/subdir_vars.mk=UTF-8 +encoding//Debug/Source/subdir_rules.mk=UTF-8 +encoding//Debug/Source/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/.spec b/.spec new file mode 100644 index 0000000..f1aaf48 --- /dev/null +++ b/.spec @@ -0,0 +1,44 @@ +[ + { + NAME: K2APU_DCU + COMMON_COMPILE_FLAG: -I "C:\ti\c2000\C2000Ware_5_04_00_00\device_support\f2833x\common\include" -I "C:\ti\c2000\C2000Ware_5_04_00_00\device_support\f2833x\headers\include" + SOURCES: + [ + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS}\Source + FILENAME: Comm.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS}\Source + FILENAME: Display.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS}\Source + FILENAME: Oper.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS}\Source + FILENAME: State.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS}\Source + FILENAME: main.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + ] + } +] \ No newline at end of file diff --git a/.staticdata/.hint b/.staticdata/.hint new file mode 100644 index 0000000..6051ffd --- /dev/null +++ b/.staticdata/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v005\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/.hint b/.staticdata/.previous/20260113_090354/.hint new file mode 100644 index 0000000..f255c84 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/.spec b/.staticdata/.previous/20260113_090354/.spec new file mode 100644 index 0000000..0c6a03b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v005\Source\.spec \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090354/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090354/K2DCU/config/.inf b/.staticdata/.previous/20260113_090354/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/K2DCU/config/ci.ini b/.staticdata/.previous/20260113_090354/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090354/K2DCU/config/csa.exe b/.staticdata/.previous/20260113_090354/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090354/K2DCU/config/csa.exe differ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/config/psionic.ini b/.staticdata/.previous/20260113_090354/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 b/.staticdata/.previous/20260113_090354/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 new file mode 100644 index 0000000..476e6ce --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 @@ -0,0 +1,180 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define PI2 (6.283185f) +#define ADC_FREQ (10000.0f) // 10kHz = 0.0001sec +#define ADC_LPF_COFF_TEMP (0.2f) +#define ADC_LPF_GAIN_TEMP (0.00012566f) //(PI2 * ADC_LPF_COFF_TEMP * (1.0f / ADC_FREQ)) +#define ADC_LPF_COFF (30.0f) +#define ADC_LPF_GAIN (0.01884955f) //(PI2 * ADC_LPF_COFF * (1.0f / ADC_FREQ)) + +#define LONG_KEY_TIME (1000UL) +#define KEY_POWER_MASK (0x00000001UL) + +#define COMM_TIME_OUT_COUNT (30U) + +enum +{ + IDX_ADC_ENGINE_HEATER_I = 0U, // 0 + IDX_ADC_GLOW_PLUG_I, // 1 + IDX_ADC_SOLENOID_I, // 2 + IDX_ADC_FUEL_PUMP_I, // 3 + IDX_ADC_COOLANT_PUMP_I, // 4 + IDX_ADC_FAN1_I, // 5 + IDX_ADC_FAN2_I, // 6 + IDX_ADC_MAX +}; + +typedef enum +{ + IDX_FAULT_CAR_COMM = 0U, // 0 + IDX_FAULT_GCU_COMM, // 1 + IDX_FAULT_ECU_COMM, // 2 + IDX_FAULT_RPM_ERR, // 3 + IDX_FAULT_ENGINE_HEAT_OC, // 4 + IDX_FAULT_GLOW_PLUG_OC, // 5 + IDX_FAULT_SOLENOID_OC, // 6 + IDX_FAULT_FUEL_PUMP_OC, // 7 + IDX_FAULT_COOLANT_PUMP_OC, // 8 + IDX_FAULT_FAN1_OC, // 9 + IDX_FAULT_FAN2_OC, // 10 + IDX_FAULT_ENGINE_HEAT_LINE_OPEN, // 11 + IDX_FAULT_GLOW_PLUG_LINE_OPEN, // 12 + IDX_FAULT_SOLENOID_LINE_OPEN, // 13 + IDX_FAULT_FUEL_PUMP_LINE_OPEN, // 14 + IDX_FAULT_COOLANT_PUMP_LINE_OPEN, // 15 + IDX_FAULT_FAN1_LINE_OPEN, // 16 + IDX_FAULT_FAN2_LINE_OPEN, // 17 + IDX_FAULT_MAX +} ALARM_TYPE; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fOffset; + float32 fLpfValue; + float32 fSampledValue; + float32 fGain; + float32 fSampledSum; + float32 fTempAdcOffset; + int16 iAdcValue; + Uint16 uiSamplingCount; +} CAdcCalcValue; + +typedef union ClassFaultBitValue +{ + Uint32 ulTotal; + struct + { + Uint16 CarCommTimeout : 1; + Uint16 GcuCommTimeout : 1; + Uint16 EcuCommTimeOut : 1; + Uint16 RpmError : 1; + Uint16 EngineHeatOverCurrent : 1; + Uint16 GlowPlugOverCurrent : 1; + Uint16 SolenoidOverCurrent : 1; + Uint16 FuelPumpOverCurrent : 1; + + Uint16 CoolantPumpOverCurrent : 1; + Uint16 Fan1OverCurrent : 1; + Uint16 Fan2OverCurrent : 1; + Uint16 EngineHeatOpen : 1; + Uint16 GlowPlugOpen : 1; + Uint16 SolenoidOpen : 1; + Uint16 FuelPumpOpen : 1; + Uint16 CoolantPumpOpen : 1; + + Uint16 Fan1Open : 1; + Uint16 Fan2Open : 1; + Uint16 rsvd_padding1 : 6; + + Uint16 rsvd_padding2 : 8; + } bit; +} CFaultBitValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // Ѱ + Uint16 uiWarning; // 0: , 1: ߻ + Uint16 uiDetectCount; // ī + Uint16 uiReleaseCount; // ī + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, + IDX_KEY_ARR_UP, + IDX_KEY_ARR_DOWN, + IDX_KEY_ENTER, + IDX_KEY_MENU, + IDX_KEY_ENG_START_STOP, + IDX_KEY_EMERGENCY, + IDX_KEY_MAX +} EKeyIndex; + +typedef struct ClassKeyHandler +{ + EKeyIndex eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef union ClassKeyList +{ + Uint16 uiTotal; + struct + { + Uint16 MainPower : 1; + Uint16 ArrowUp : 1; + Uint16 ArrowDown : 1; + Uint16 Enter : 1; + Uint16 Menu : 1; + Uint16 EngineStartStop : 1; + Uint16 Emergency : 1; + } bit; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; +extern CAdcOperValue AdcOperValue; +extern CFaultBitValue FaultBitValue; +extern CKeyOperValue KeyOperValue; + +#endif /* SOURCE_STATE_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ new file mode 100644 index 0000000..9a06c75 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 b/.staticdata/.previous/20260113_090354/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 new file mode 100644 index 0000000..8eb157e --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 @@ -0,0 +1,1443 @@ +#include "main.h" +#include "CFont.h" + +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +volatile Uint16 CommandBus, DataBus; +const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; +int8 cNumBuffer[7] = { 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; +int8 *pNumBuffer = cNumBuffer; + +COledOperValue OledOperValue; + +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenence(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +Uint16 CStrLen(const int8 *s); +void CInitOledModule(void); +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +void CInitProgress(void); +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len); +void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CLcdWrite(Uint16 Data, Uint16 Command); +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CSetPageAddress(Uint16 Address); +void CSetColumnAddress(Uint16 x); +void COledWrite(Uint16 Data, Uint16 Command); +void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(eApuOperIdx idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); + +static const CPageHandler PageTable[OLED_PAGE_MAX] = +{ + { OLED_PAGE_APU1, CPageApu1 }, + { OLED_PAGE_APU2, CPageApu2 }, + { OLED_PAGE_MENU1, CPageMenu1 }, + { OLED_PAGE_MENU2, CPageMenu2 }, + { OLED_PAGE_TEMP, CPageTemp }, + { OLED_PAGE_SENSOR1, CPageSensor1 }, + { OLED_PAGE_SENSOR2, CPageSensor2 }, + { OLED_PAGE_SENSOR3, CPageSensor3 }, + { OLED_PAGE_SENSOR4, CPageSensor4 }, + { OLED_PAGE_WARNING1, CPageWarning1 }, + { OLED_PAGE_WARNING2, CPageWarning2 }, + { OLED_PAGE_FAULT1, CPageFault1 }, + { OLED_PAGE_FAULT2, CPageFault2 }, + { OLED_PAGE_FAULT3, CPageFault3 }, + { OLED_PAGE_FAULT4, CPageFault4 }, + { OLED_PAGE_FAULT5, CPageFault5 }, + { OLED_PAGE_FAULT6, CPageFault6 }, + { OLED_PAGE_RESET_ALARM, CPageAlarmReset }, + { OLED_PAGE_PASSWORD, CPagePassword }, + { OLED_PAGE_MAINTENENCE, CPageMaintenence }, + { OLED_PAGE_KEY_TEST, CPageKeyTest }, + { OLED_PAGE_SHUTDOWN, CPageShutdown } +}; + +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], title, CStrLen(title)); + CDrawStr(10U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0])); + + CDrawTitleBox(CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0]) * 6U); + + if (pageNumStr != NULL) + { + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], pageNumStr, CStrLen(pageNumStr)); + CDrawStr(100U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen(OledOperValue.cStrBuff[OLED_ROW_0])); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY = 0U; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; // Invalid row + } + + CStrncpy(OledOperValue.cStrBuff[row], label, CStrLen(label)); + + if (valueStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], valueStr, CStrLen(valueStr)); + } + + if (unitStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], unitStr, CStrLen(unitStr)); + } + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + CFloatToString(value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + CDecToString((int16)value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + Uint16 drawY = 0U; + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageApu1(void) +{ + const int8 *cTemp = ""; + float32 fTemp; + + // TITLE + CDrawPageTitle("APU Status", "1/2"); + + // LINE 1 + fTemp = Rx220.GcuData.DcVoltage; + CDrawPageLineFloat(OLED_ROW_1, "DC Voltage ", fTemp, " V"); + + // LINE 2 + fTemp = Rx220.GcuData.DcCurrent; + CDrawPageLineFloat(OLED_ROW_2, "DC Current ", fTemp, " A"); + + // LINE 3 + fTemp = (Rx220.GcuData.DcVoltage * Rx220.GcuData.DcCurrent); + CDrawPageLineFloat(OLED_ROW_3, "Power ", fTemp, " kW"); + + // LINE 4 + cTemp = CGetApuStateString((eApuOperIdx)GeneralOperValue.uiApuState); + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_4], "Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[OLED_ROW_4], cTemp); + CStrncat(OledOperValue.cStrBuff[OLED_ROW_4], cTemp, CStrLen(cTemp)); + CDrawStr(0U, OLED_LINE_4, OledOperValue.cStrBuff[OLED_ROW_4], CStrLen(OledOperValue.cStrBuff[OLED_ROW_4])); +} + +static void CPageApu2(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngineActualRpm(); + CDrawPageLineInt(OLED_ROW_1, "ENG.RPM ", (int32)iTemp, " rpm"); + + // LINE 2 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt(OLED_ROW_2, "Coolant ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx320.EcuData.ActualTorque; + CDrawPageLineInt(OLED_ROW_3, "Torque ", (int32)iTemp, " %"); + + // LINE 4 + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, pNumBuffer); + CDrawPageLine(OLED_ROW_4, "ENG.Hour ", pNumBuffer, " Hr"); +} +static void CPageMenu1(void) +{ + // TITLE + CDrawPageTitle("Menu", "1/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "1. APU Status ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "2. Temperature ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "3. Sensor ", NULL, NULL); + + // LINE 4 + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_4, "4. Warning ", NULL, NULL); +} + +static void CPageMenu2(void) +{ + // TITLE + CDrawPageTitle("Menu", "2/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "5. Fault ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "6. Alarm Reset ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "7. Maintenence ", NULL, NULL); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = Rx221.GcuData.PcbTemperature - 40; + CDrawPageLineInt(OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " "); + + // LINE 2 + iTemp = Rx221.GcuData.FetTemperature - 40; + CDrawPageLineInt(OLED_ROW_2, "FET Temp. ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx221.GcuData.GenTemperature1 - 40; + CDrawPageLineInt(OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " "); + + // LINE4 + iTemp = Rx221.GcuData.GenTemperature2 - 40; + CDrawPageLineInt(OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " "); +} +static void CPageSensor1(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "1/4"); + + // LINE 1 + fTemp = (Adc_EngineHeater_I.fLpfValue < 0.0f) ? 0.0f : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "EngineHeater", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_GlowPlug_I.fLpfValue < 0.0f) ? 0.0f : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "GlowPlug ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Solenoid_I.fLpfValue < 0.0f) ? 0.0f : Adc_Solenoid_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Solenoid ", fTemp, " A"); + + // LINE 4 + fTemp = (Adc_FuelPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_FuelPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_4, "FuelPump ", fTemp, " A"); +} + +static void CPageSensor2(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "2/4"); + + // LINE 1 + fTemp = (Adc_CoolantPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "CoolantPump ", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_Fan1_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan1_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "Fan1 ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Fan2_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan2_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Fan2 ", fTemp, " A"); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = Rx321.EcuData.BarometicPressure; + CDrawPageLineInt(OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = Rx321.EcuData.Fan1Speed; + CDrawPageLineInt(OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = Rx321.EcuData.Fan2Speed; + CDrawPageLineInt(OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = Rx321.EcuData.CoolantPumpSpeed; + CDrawPageLineInt(OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = Rx220.GcuData.Rpm; + CDrawPageLineInt(OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "PCBOT:", Rx210.GcuWarning.bit.PcbOverHeat, "FETOT:", Rx210.GcuWarning.bit.FetOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "GEOT1:", Rx210.GcuWarning.bit.GenOverHeat1, "GEOT2:", Rx210.GcuWarning.bit.GenOverHeat2); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "ENGOT:", Rx310.EcuWarning.bit.EngineOverHeat, "L-OIL:", Rx310.EcuWarning.bit.LowOilLevel); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "INTOT:", Rx310.EcuWarning.bit.IntakeOverHeat, "INTLP:", Rx310.EcuWarning.bit.IntakeLoPressure); +} + +static void CPageWarning2(void) +{ + // TITLE + CDrawPageTitle("Warning", "2/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "ENGLT:", Rx310.EcuWarning.bit.EngineLoTemperature, "ENGSF:", Rx310.EcuWarning.bit.EngineSensor); + + // LINE 2 + CDrawPageLineStatus(OLED_ROW_2, "DEFAC:", Rx310.EcuWarning.bit.DefaltValueActive); +} +static void CPageFault1(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "1/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CARCT:", FaultBitValue.bit.CarCommTimeout, "GCUCT:", FaultBitValue.bit.GcuCommTimeout); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ECUCT:", FaultBitValue.bit.EcuCommTimeOut, "RPMER:", FaultBitValue.bit.RpmError); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "EHLOC:", FaultBitValue.bit.EngineHeatOverCurrent, "GPLOC:", FaultBitValue.bit.GlowPlugOverCurrent); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SOLOC:", FaultBitValue.bit.SolenoidOverCurrent, "FPLOC:", FaultBitValue.bit.FuelPumpOverCurrent); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "2/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CPLOC:", FaultBitValue.bit.CoolantPumpOverCurrent, "F1LOC:", FaultBitValue.bit.Fan1OverCurrent); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "F2LOC:", FaultBitValue.bit.Fan2OverCurrent, "EHLLO:", FaultBitValue.bit.EngineHeatOpen); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GPLLO:", FaultBitValue.bit.GlowPlugOpen, "SOLLO:", FaultBitValue.bit.SolenoidOpen); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "FPLLO:", FaultBitValue.bit.FuelPumpOpen, "CPLLO:", FaultBitValue.bit.CoolantPumpOpen); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "3/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "F1LLO:", FaultBitValue.bit.Fan1Open, "F2LLO:", FaultBitValue.bit.Fan2Open); +} + +static void CPageFault4(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "4/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "HTRIP:", Rx210.GcuFault.bit.HwTrip, "HIGBT:", Rx210.GcuFault.bit.HwIgbt); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "HDCOV:", Rx210.GcuFault.bit.HwDc, "GNOCU:", Rx210.GcuFault.bit.GenOverCurrentU); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GNOCV:", Rx210.GcuFault.bit.GenOverCurrentV, "GNOCW:", Rx210.GcuFault.bit.GenOverCurrentW); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SDCOV:", Rx210.GcuFault.bit.DcOverVoltage, "SDCOC:", Rx210.GcuFault.bit.DcOverCurrent); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "5/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "SMOOC:", Rx210.GcuFault.bit.CrankningOverCurrent, "PCBOT:", Rx210.GcuFault.bit.PcbOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "FETOT:", Rx210.GcuFault.bit.FetOverHeat, "GW1OT:", Rx210.GcuFault.bit.GenTempOverHeat1); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GW2OT:", Rx210.GcuFault.bit.GenTempOverHeat2, "GENOS:", Rx210.GcuFault.bit.GenOverSpeed); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "RSICF:", Rx210.GcuFault.bit.ResolverIC, "RSPRT:", Rx210.GcuFault.bit.ResolverParity); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawPageTitle("Ecu Fault", "6/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "OILMS:", Rx310.EcuFault.bit.OilPressureMissing, "INTOT:", Rx310.EcuFault.bit.IntakeOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ENGOT:", Rx310.EcuFault.bit.EngineOverHeat, "ACTUA:", Rx310.EcuFault.bit.Actuator); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "RPMSG:", Rx310.EcuFault.bit.RpmSignal, "ENGSF:", Rx310.EcuFault.bit.EngineStartFail); +} +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 0U) ? (const int8*)"P" : (const int8*)"F"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l3, 13U); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + + switch(row) + { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine(OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + int16 iTemp[2] = { 0, '\0' }; + + // TITLE + CDrawPageTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case OLED_PASS_DIGIT_1: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case OLED_PASS_DIGIT_2: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case OLED_PASS_DIGIT_3: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CTextAlign(OledOperValue.cAlignBuffer, maskBuffer); + CDrawStr(0U, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageMaintenence(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawPageTitle("Maintenence", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "Switch Test ", NULL, NULL); +} +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + Uint16 y = 0U; + switch(row) { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine(OLED_LINE_TITLE + 2U, "Key input Test"); + + // TITLE2 + CDrawCenteredLine(OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + // " Stat:" + Status + // This is special indentation. + // I can reuse CDrawKeyStatusLine if I pass proper label. + // " Stat:" is 19 chars. + CDrawKeyStatusLine(OLED_ROW_2, " Stat:", GPIO_KEY_START(), NULL, 0, NULL, 0); + + // LINE 3 + // " Up:" + s + " " + "Entr:" + s + " " + "Powr:" + s + CDrawKeyStatusLine(OLED_ROW_3, " Up:", GPIO_KEY_UP(), "Entr:", GPIO_KEY_ENTER(), "Powr:", GPIO_KEY_POWER()); + + // LINE 4 + // "Down:" + s + " " + "Menu:" + s + " " + "Emgc:" + s + CDrawKeyStatusLine(OLED_ROW_4, "Down:", GPIO_KEY_DOWN(), "Menu:", GPIO_KEY_MENU(), "Emgc:", GPIO_KEY_EMERGENCY()); +} +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "Shutting down..."); +} +void CSetPage(Uint16 PageNum) +{ + int16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0; i < OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler + } + } +} + +void COledBufferReset(void) +{ + (void) memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void) memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // + CDrawLine(8U, 10U, 10U, 12U); // 𼭸 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // Ʒ + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 𼭸 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // + + if (OledOperValue.uiPageNum != OLED_PAGE_PASSWORD) + { + // ŸƲ ڽ + CDrawLine(98U, 0U, 98U, 9U); // + CDrawLine(98U, 10U, 100U, 12U); // 𼭸 + CDrawLine(101U, 12U, 118U, 12U); // Ʒ + CDrawLine(119U, 12U, 121U, 10U); // 𼭸 + CDrawLine(121U, 0U, 121U, 9U); // + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = y / 8; j < (y + height) / 8; j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + int16 i; + + CInitOledModule(); + + for(uiPageNum = 0; uiPageNum < 8; uiPageNum++) + { + COledWrite((Uint16)(0xB0 | uiPageNum), MODE_COMMAND); + + for(i = 0; i < OLED_WIDTH; i++) + { + COledWrite(0x00, MODE_DATA); + } + } + + CInitProgress(); +} + +void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, OLED_LINE_TITLE, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void) memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = (TXT_MAX_LEN - 1) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0; + i = 0; + + while (str[i] != '\0') // str int8* ̹Ƿ, int8 Ÿ (0) ã + { + uiLen++; + i++; + } + + if (uiLen >= TXT_MAX_LEN) + { + uiIndent = 0; + } + else + { + uiIndent = ((TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < TXT_MAX_LEN)) // ҽ Һ + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = (int8)' '; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = 0; +} + +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // + CDrawLine(x, (y + 1U), x, (y + h)); // + CDrawLine(x, (y + h), w, (y + h)); // Ʒ + CDrawLine(w, (y + 1U), w, (y + h - 1U)); // +} + +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + if (x2 > OledOperValue.Point.X2) + { + OledOperValue.Point.X2 = x2; + } + if (y2 > OledOperValue.Point.Y2) + { + OledOperValue.Point.Y2 = y2; + } +} + +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 tmp = 0, x = 0, y = 0, dx = 0, dy = 0, swapxy = 0; + Uint16 loop_end = 0; + Uint16 minor_limit = 0; // (y) Ѱ谪 + int16 err = 0, ystep = 0; + + dx = x2 - x1; + + dy = (y1 > y2) ? (y1 - y2) : (y2 - y1); + + if (dy > dx) + { + swapxy = 1; + tmp = dx; dx = dy; dy = tmp; + tmp = x1; x1 = y1; y1 = tmp; + tmp = x2; x2 = y2; y2 = tmp; + + loop_end = OLED_HEIGHT - 1; + minor_limit = OLED_WIDTH - 1; + } + else + { + loop_end = OLED_WIDTH - 1; + minor_limit = OLED_HEIGHT - 1; + } + + if (x2 > loop_end) + { + x2 = loop_end; + } + + err = dx >> 1; + ystep = (y2 > y1) ? 1 : -1; + y = y1; + + if (swapxy == 0) + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } + else + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage = y / 8U; + Uint16 uiOffset = y % 8U; + + if (x >= OLED_WIDTH || y >= OLED_HEIGHT) + { + x = OLED_WIDTH; + y = OLED_HEIGHT; + } + else + { + if (x < OLED_WIDTH) + { + if (Color) + { + OledOperValue.uiBuff[x][uiPage] |= (0x01U << uiOffset); + } + else + { + OledOperValue.uiBuff[x][uiPage] &= (Uint16) ~(0x01U << uiOffset); + } + } + } +} + +void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0), MODE_COMMAND); +} + +void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0F) | 0x10; + LowAddress = x & 0x0F; + + COledWrite(LowAddress, MODE_COMMAND); + COledWrite(HighAddress, MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 1; + XintfRegs.XTIMING6.bit.XWRACTIVE = 13; + XintfRegs.XTIMING6.bit.XWRTRAIL = 1; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 1; + XintfRegs.XTIMING6.bit.XRDACTIVE = 13; + XintfRegs.XTIMING6.bit.XRDTRAIL = 1; + + XintfRegs.XTIMING6.bit.X2TIMING = 1; + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len) +{ + Uint16 i; + + if ((len > 0U) && (len < TXT_MAX_LEN)) // ҽ Һ + { + for(i = 0; i < len; i++) + { + if (str[i] & 0x80) + { + CDrawChar(x, y, (Uint16)((str[i] << 8) | str[i + 1]), TXT_TYPE_ETC); + i++; + x += TXT_ENG_WIDTH * 2U; + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + } + } +} + +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0) // Eng Char + { + uiCharWidth = TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = TXT_ENG_WIDTH * 2U; + ch = (ch == 0xA1C9U) ? 0x00U : ch; + pFontData = EtcFontTable[ch]; + } + + CSetDrawRegion(x, y, (x + TXT_ENG_WIDTH), (y + TXT_ENG_HEIGHT)); + + for(j = 0; j < TXT_ENG_HEIGHT; j++) + { + for(i = 0; i < uiCharWidth; i++) + { + if (pFontData[uiFontIndex / 8] & uiBitMask[uiFontIndex % 8]) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +void CInitOledModule(void) +{ + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + GPIO_OLED_RESET(0U); + DELAY_US(2000L); + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + + COledWrite(0xFD, MODE_COMMAND); // Command Lock + COledWrite(0x12, MODE_COMMAND); // + COledWrite(0xAE, MODE_COMMAND); // oled off + COledWrite(0xA1, MODE_COMMAND); // 1U segment column address high to low + + COledWrite(0xC8, MODE_COMMAND); // COM output scan from high to low + + COledWrite(0x81, MODE_COMMAND); // 1U contrast + COledWrite(0xFF, MODE_COMMAND); + + COledWrite(0xAF, MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = OLED_LOAD_PROGRESS_X + 1; +} + +void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +void CInitOledStructure(void) +{ + (void) memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void) memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +Uint16 CStrLen(const int8 *s) +{ + // ּҸ մϴ. + const int8 *p = s; + + // Ͱ ('\0', ASCII 0) Ű ͸ ŵϴ. + // ڿ ӵ ޸ Ǿ ֽϴ. + while (*p != '\0') + { + p++; + } + + // ּ( ) ּ ̰ ڿ ̰ ˴ϴ. + return (Uint16)(p - s); +} + +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + + for (i = 0; i < Size; i++) + { + pTarget[i] = pSource[i]; + } + pTarget[i] = '\0'; +} + +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + + uiTargetSize = (Uint16)CStrLen(pTarget); + + if ((uiTargetSize + Size) < TXT_MAX_LEN) + { + for (i = 0; i < Size; i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = '\0'; + } +} + +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U, uiSignLocate = 0U, i; + Uint16 x, y; + int32 lData = (int32) Data * 10; + int8 cTmp[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + if (lData < 0) + { + // ǥ ڰ + uiSign = 1U; + lData = -lData; + } + + while (lData > 0U) + { + cTmp[x++] = (lData % 10) + '0'; + lData /= 10U; + } + + if (x == 0) // ġ 0 . + { + y = 3U; + Array[y++] = '0'; + } + else + { + y = 5 - x; // Ǵ . + x = x - 1; // ε . + + if (y < 1) + { + uiSignLocate = 0U; + } + else + { + if ((y >= 1) && (y <= 5)) + { + uiSignLocate = (Uint16)(y - 1); // '-' ȣ ǥ ڸ + } + } + + if (uiSign == 1U) // '-' ȣ ǥ ġ ϱ . + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U)) + { + Array[uiSignLocate] = '-'; + } + } + else + { + Array[uiSignLocate] = ' '; + } + + while (x > 0) + { + Array[y++] = cTmp[x--]; + } + } + Array[y] = '\0'; // End of string. +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 x = 0U, y = 0U, i; + int16 iTemp = (int16)(Data * 10); + int8 cTmp[4] = { 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + while (iTemp > 0U) + { + cTmp[x++] = (iTemp % 10) + '0'; + iTemp /= 10U; + } + + if (x == 0U) // ġ 0.0 . + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = '0'; + } + else + { + if (x == 1U) + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + else + { + y = 5U - x; // Ǵ . + x = x - 1U; // ε . + + while (x > 0U) + { + Array[y++] = cTmp[x--]; + if (x == 0U) + { + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + } + } + } + Array[y] = '\0'; // End of string. +} + +void CInitializePage(void) +{ + if (AdcOperValue.uiOffsetAdjustStart == 0U) + { + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < OLED_LOAD_PROGRESS_W - 3) // -3 α׷ ¿ 1ȼ . + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(OLED_ROW_2, "EHT:", PowerOnCheckValue.EngineHeaterSensor, "GPL:", PowerOnCheckValue.GlowPlugSensor, "SOL:", PowerOnCheckValue.SolenoidSensor); + + // LINE 3 + CDrawPostStatusLine(OLED_ROW_3, "FUP:", PowerOnCheckValue.FuelPumpSensor, "CLP:", PowerOnCheckValue.CoolantPumpSensor, "FN1:", PowerOnCheckValue.Fan1Sensor); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(OLED_ROW_4, "FN2:", PowerOnCheckValue.Fan2Sensor, NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +void CReversString(int8 *str, int16 length) +{ + Uint16 i = 0U; + Uint16 end = length - 1U; + int8 temp; + + while (i < end) + { + temp = str[i]; + str[i] = str[end]; + str[end] = temp; + i++; + end--; + } +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = num; // Է¹ (: 1234567 -> "12345.67") + + // 1. Ҽ ° ڸ (100 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 2. Ҽ ù° ڸ (10 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 3. Ҽ + str[i++] = '.'; + + // 4. ȯ + // Է 0̾ ּ "0" do-while + do + { + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + } + while (temp != 0); + + // 5. ä (ڸ ) + // 5ڸ + 1ڸ + Ҽ2ڸ = 8ڸ + while (i < 8U) + { + str[i++] = ' '; + } + + str[i] = '\0'; // ڿ ˸ + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(eApuOperIdx idx) +{ + // ε 1:1 ĪǴ ڿ 迭 static Ͽ Լ ȣ 迭 ٽ ʵ + static const int8* strTable[] = + { + "BOOT", // 0: APU_OPER_IDX_BOOT + "INIT", // 1: APU_OPER_IDX_INITIAL + "POST", // 2: APU_OPER_IDX_POST + "EMERGENCY", // 3: APU_OPER_IDX_EMERGENCY + "STANDBY", // 4: APU_OPER_IDX_STANDBY + "START_CHECK", // 5: APU_OPER_IDX_START_CHECK + "PREHEAT", // 6: APU_OPER_IDX_ACTIVE_ENG_HEAT + "CRANKING", // 7: APU_OPER_IDX_CRANKING + "WARM_UP", // 8: APU_OPER_IDX_ENG_WARMING_UP + "CHECK_OPER", // 9: APU_OPER_IDX_CHECK_OPERATION + "GENERATING", // 10: APU_OPER_IDX_SET_GCU_GEN_START + "STABLED", // 11: APU_OPER_IDX_ENG_START_DONE + "STOP", // 12: APU_OPER_IDX_ENG_STOP_NORMAL + "COOLDOWN" // 13: APU_OPER_IDX_ENG_STOP_COOLDOWN + }; + + return strTable[idx]; +} diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ new file mode 100644 index 0000000..95dd823 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ new file mode 100644 index 0000000..be86c38 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ new file mode 100644 index 0000000..e2d1e35 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ new file mode 100644 index 0000000..545526b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ new file mode 100644 index 0000000..cfe478f --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ new file mode 100644 index 0000000..4714194 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ new file mode 100644 index 0000000..b5a7be5 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void InitXintf(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 b/.staticdata/.previous/20260113_090354/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 new file mode 100644 index 0000000..a9a4b68 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 @@ -0,0 +1,1143 @@ +#include "main.h" + +CCommCheck CommCheck; + +// Tx +static CTx100 Tx100; +static CTx101 Tx101; +CTx102 Tx102; +CTx103 Tx103; +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx130 Tx130; +static CTx131 Tx131; +static CTx132 Tx132; + +// Rx - GCU +static CRx200 Rx200; +static CRx201 Rx201; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +static CRx300 Rx300; +static CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); + +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // ѹ̶ ŵǾٸ ش ġ Ǿٰ Ǵ. + CommCheck.CarComputer = 0U; // ۽ ŸӾƿ īƮ Ŭ + /* + if (ECanShadow.CANRMP.bit.RMP15 == 1U) + { + ECanShadow.CANRMP.bit.RMP15 = 1U; + } + + if (ECanShadow.CANRMP.bit.RMP16 == 1U) + { + ECanShadow.CANRMP.bit.RMP16 = 1U; + } +*/ + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +void CSendECanDataA(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + Uint16 uiTemp; + + // 10ms + ECanaMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.ApuData.PlayState & 0x7U; + + uiTemp = (Tx101.ApuData.AlarmOccured << 0U) | (Tx101.ApuData.Emergency << 1U) | (Tx101.ApuData.PowerSwitch << 2U); + ECanaMboxes.MBOX1.MDL.byte.BYTE1 = uiTemp; + ECanaMboxes.MBOX1.MDL.byte.BYTE2 = Tx101.ApuData.GcuPlayState & 0x7U; + + uiTemp = (Tx101.ApuData.GcuAlarmOccured << 0U) | (Tx101.ApuData.GcuShutdown << 1U); + ECanaMboxes.MBOX1.MDL.byte.BYTE3 = uiTemp; + + uiTemp = (Tx101.ApuData.EcuAlarmOccured << 0U) | + ((Tx101.ApuData.EcuPlayState & 0x3FU) << 1U) | + (Tx101.ApuData.OverrideActive << 4U) | + (Tx101.ApuData.GlowPlugActive << 5U) | + (Tx101.ApuData.HeaterActive << 6U) | + (Tx101.ApuData.OilPressureMissing); + ECanaMboxes.MBOX1.MDH.byte.BYTE4 = uiTemp; + + ECanaMboxes.MBOX1.MDH.byte.BYTE5 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE6 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE7 = 0; + + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanaMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX2.MDH.all = 0x00000000U; + ECanaMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanaMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX3.MDH.all = 0x00000000U; + ECanaMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanaMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX4.MDH.all = 0x00000000U; + ECanaMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanaMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX6.MDH.all = 0x00000000U; + ECanaMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanaMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX7.MDH.all = 0x00000000U; + ECanaMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanaMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX8.MDH.all = 0x00000000U; + ECanaMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanaMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX9.MDH.all = 0x00000000U; + ECanaMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanaMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX28.MDH.all = 0x00000000U; + ECanaMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanaMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX29.MDH.all = 0x00000000U; + ECanaMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanaMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX30.MDH.all = 0x00000000U; + ECanaMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanaRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanaRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.GcuData.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.GcuData.VersionMajor = (Uint8)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.GcuData.VersionMinor = (Uint8)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.GcuData.VersionPatch = (Uint8)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.GcuData.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + + Rx201.GcuData.AlarmOccured = (Uint16)((uiMBOXMdl >> 16U) & 0x1U); + Rx201.GcuData.Shutdown = (Uint16)((uiMBOXMdl >> 17U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX17 - 210h (Ʈ ʵ ) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx210.GcuWarning.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat1 = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat2 = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + + Rx210.GcuFault.bit.HwTrip = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx210.GcuFault.bit.HwIgbt = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx210.GcuFault.bit.HwDc = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentU = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentV = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentW = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + Rx210.GcuFault.bit.DcOverVoltage = (Uint16)((uiMBOXMdl >> 14U) & 0x1U); + Rx210.GcuFault.bit.DcOverCurrent = (Uint16)((uiMBOXMdl >> 15U) & 0x1U); + + Rx210.GcuFault.bit.CrankningOverCurrent = (Uint16)((uiMBOXMdl >> 0U) & 0x1U); + Rx210.GcuFault.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 1U) & 0x1U); + Rx210.GcuFault.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 2U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat1 = (Uint16)((uiMBOXMdl >> 3U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat2 = (Uint16)((uiMBOXMdl >> 4U) & 0x1U); + Rx210.GcuFault.bit.GenOverSpeed = (Uint16)((uiMBOXMdl >> 5U) & 0x1U); + Rx210.GcuFault.bit.ResolverIC = (Uint16)((uiMBOXMdl >> 6U) & 0x1U); + Rx210.GcuFault.bit.ResolverParity = (Uint16)((uiMBOXMdl >> 7U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.GcuData.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.GcuData.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // MDH Reverse: Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.GcuData.Rpm = uiRpmL | (uiRpmH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.GcuData.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.GcuData.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GcuData.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GcuData.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.EcuData.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.EcuData.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.EcuData.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.OperationInfo.AlarmOccured = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx301.OperationInfo.PlayState = (Uint16)((uiMBOXMdl >> 25U) & 0x7U); // (24 + 1) + Rx301.OperationInfo.OverrideActive = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); // (24 + 4) + Rx301.OperationInfo.GlowPlugActive = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx301.OperationInfo.HeaterActive = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx301.OperationInfo.OilPressureMissing = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx310.EcuWarning.bit.reserved = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx310.EcuWarning.bit.LowOilLevel = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx310.EcuWarning.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx310.EcuWarning.bit.IntakeLoPressure = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx310.EcuWarning.bit.EngineLoTemperature = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx310.EcuWarning.bit.EngineSensor = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx310.EcuWarning.bit.DefaltValueActive = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + + // [Reverse] Byte 2 -> >> 8 + Rx310.EcuFault.bit.OilPressureMissing = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx310.EcuFault.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx310.EcuFault.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx310.EcuFault.bit.Actuator = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx310.EcuFault.bit.RpmSignal = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx310.EcuFault.bit.EngineStartFail = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.EcuData.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.EcuData.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.EcuData.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.EcuData.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.EcuData.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.EcuData.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.EcuData.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.EcuData.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.EcuData.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.EcuData.BarometicPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.EcuData.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.EcuData.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.EcuData.TotalOperTimeL) | ((Uint32)Rx322.EcuData.TotalOperTimeH << 16U); + GeneralOperValue.ulTotalOperationHour = (GeneralOperValue.ulTotalOperationHour > 1000000UL) ? 1000000UL : GeneralOperValue.ulTotalOperationHour; + } + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + // 10ms + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = 0x1; + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = 0x2; + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x3; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x4; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x5; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = 0x6; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = 0x7; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = 0x8; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; // 100h + ECanShadow.CANTRS.bit.TRS4 = 1U; // 110h + ECanShadow.CANTRS.bit.TRS5 = 1U; // 120h + ECanShadow.CANTRS.bit.TRS6 = 1U; // 121h + ECanShadow.CANTRS.bit.TRS7 = 1U; // 130h + ECanShadow.CANTRS.bit.TRS8 = 1U; // 131h + ECanShadow.CANTRS.bit.TRS9 = 1U; // 132h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; // 100h + ECanShadow.CANTA.bit.TA4 = 1U; // 110h + ECanShadow.CANTA.bit.TA5 = 1U; // 120h + ECanShadow.CANTA.bit.TA6 = 1U; // 121h + ECanShadow.CANTA.bit.TA7 = 1U; // 130h + ECanShadow.CANTA.bit.TA8 = 1U; // 131h + ECanShadow.CANTA.bit.TA9 = 1U; // 132h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void) memset(&Tx100, 0, sizeof(CTx100)); + (void) memset(&Tx101, 0, sizeof(CTx101)); + (void) memset(&Tx102, 0, sizeof(CTx102)); + (void) memset(&Tx103, 0, sizeof(CTx103)); + (void) memset(&Tx110, 0, sizeof(CTx110)); + (void) memset(&Tx120, 0, sizeof(CTx120)); + (void) memset(&Tx121, 0, sizeof(CTx121)); + (void) memset(&Tx130, 0, sizeof(CTx130)); + (void) memset(&Tx131, 0, sizeof(CTx131)); + (void) memset(&Tx132, 0, sizeof(CTx132)); + + // Rx - GCU + (void) memset(&Rx200, 0, sizeof(CRx200)); + (void) memset(&Rx201, 0, sizeof(CRx201)); + (void) memset(&Rx210, 0, sizeof(CRx210)); + (void) memset(&Rx220, 0, sizeof(CRx220)); + (void) memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void) memset(&Rx300, 0, sizeof(CRx300)); + (void) memset(&Rx301, 0, sizeof(CRx301)); + (void) memset(&Rx310, 0, sizeof(CRx310)); + (void) memset(&Rx320, 0, sizeof(CRx320)); + (void) memset(&Rx321, 0, sizeof(CRx321)); + (void) memset(&Rx322, 0, sizeof(CRx322)); +} diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 b/.staticdata/.previous/20260113_090354/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 new file mode 100644 index 0000000..e8d04e5 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 @@ -0,0 +1,434 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + struct + { + Uint16 Heartbit : 16; + Uint16 : 8; + Uint16 : 8; + Uint16 : 8; + Uint16 VersionMajor : 8; + Uint16 VersionMinor : 8; + Uint16 VersionPatch : 8; + } ApuData; +} CTx100; + +typedef struct ClassTx101 +{ + struct + { + /* byte 0 */ + Uint16 PlayState : 3; + Uint16 : 5; + + /* byte 1 */ + Uint16 AlarmOccured : 1; + Uint16 Emergency : 1; + Uint16 PowerSwitch : 1; + Uint16 : 5; + + /* byte 2 */ + Uint16 GcuPlayState : 3; + Uint16 : 5; + + /* byte 3 */ + Uint16 GcuAlarmOccured : 1; + Uint16 GcuShutdown : 1; + Uint16 : 6; + + /* byte 4 */ + Uint16 EcuAlarmOccured : 1; + Uint16 EcuPlayState : 3; + Uint16 OverrideActive : 1; + Uint16 GlowPlugActive : 1; + Uint16 HeaterActive : 1; + Uint16 OilPressureMissing : 1; + } ApuData; +} CTx101; + +typedef struct ClassTx102 +{ + struct + { + Uint16 PlayCommand : 4; // 0:3 bit + Uint16 rsvd_padding1 : 4; // 4:7 bit + Uint16 rsvd_padding2 : 8; // 1 byte + Uint16 rsvd_padding3 : 16; // 2:3 byte + Uint16 rsvd_padding4 : 16; // 4:5 byte + Uint16 rsvd_padding5 : 16; // 6:7 byte + } GcuCommand; +} CTx102; + +typedef struct ClassTx103 +{ + struct + { + Uint16 EngineStart : 8; // 0 byte + Uint16 EngineStop : 8; // 1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 RpmSetpoint : 16; // 4:5 byte + Uint16 Override : 8; // 6 byte + Uint16 Emergency : 8; // 7 byte + } EcuCommand; +} CTx103; + +typedef struct ClassTx110 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilLevel : 1; // 1 bit + Uint16 IntakeOverHeat : 1; // 2 bit + Uint16 IntakeLoPressure : 1; // 3 bit + Uint16 EngineLoTemperature : 1; // 4 bit + Uint16 EngineSensor : 1; // 5 bit + Uint16 DefaltValueActive : 1; // 6 bit + Uint16 rsvd_padding : 1; // 16bit е + } bit; + } EcuWarning; + + struct + { + CFaultBitValue ApuFault; + }; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + } GcuFault; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilPressure : 1; // 1 bit + Uint16 Actuator : 1; // 2 bit + Uint16 RpmSignal : 1; // 3 bit + Uint16 EngineStartFail : 1; // 4 bit + Uint16 rsvd_padding : 11; // 16bit е + } bit; + } EcuFault; +} CTx110; + +typedef struct ClassTx120 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx120; + +typedef struct ClassTx121 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx121; + +typedef struct ClassTx130 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CTx130; + +typedef struct ClassTx131 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding1 : 8; // 6 byte + Uint16 rsvd_padding2 : 8; // 7 byte + } EcuData; +} CTx131; + +typedef struct ClassTx132 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } EcuData; +} CTx132; + +typedef struct ClassRx200 +{ + struct + { + Uint16 HeartBit : 16; // 0:1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 rsvd_padding3 : 8; // 4 byte + Uint16 VersionMajor : 8; // 5 byte + Uint16 VersionMinor : 8; // 6 byte + Uint16 VersionPatch : 8; // 7 byte + } GcuData; +} CRx200; + +typedef struct ClassRx201 +{ + struct + { + Uint16 PlayState : 3; // 0:3 bit + Uint16 rsvd_padding1 : 5; // 4:7 bit + + Uint16 AlarmOccured : 1; // 0 bit + Uint16 Shutdown : 1; // 1 bit + Uint16 rsvd_padding2 : 6; // 2:7 bit + } GcuData; +} CRx201; + +typedef struct ClassRx210 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + }GcuFault; +} CRx210; + +typedef struct ClassRx220 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } GcuData; +} CRx220; + +typedef struct ClassRx221 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } GcuData; +} CRx221; + +typedef struct ClassRx300 +{ + struct + { + Uint16 VersionMajor : 8; // 0 byte + Uint16 VersionMinor : 8; // 1 byte + Uint16 VersionPatch : 8; // 2 byte + Uint16 rsvd_padding1 : 8; // 3 byte + Uint16 rsvd_padding2 : 16; // 4:5 byte + Uint16 rsvd_padding3 : 16; // 6:7 byte + } EcuData; +} CRx300; + +typedef struct ClassRx301 +{ + struct + { + Uint16 AlarmOccured : 1; // 0 bit + Uint16 PlayState : 3; // 1:3 bit + Uint16 OverrideActive : 1; // 4 bit + Uint16 GlowPlugActive : 1; // 5 bit + Uint16 HeaterActive : 1; // 6 bit + Uint16 OilPressureMissing : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } OperationInfo; +} CRx301; + +typedef struct ClassRx310 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 reserved : 1; // 1 bit + Uint16 LowOilLevel : 1; // 2 bit + Uint16 IntakeOverHeat : 1; // 3 bit + Uint16 IntakeLoPressure : 1; // 4 bit + Uint16 EngineLoTemperature : 1; // 5 bit + Uint16 EngineSensor : 1; // 6 bit + Uint16 DefaltValueActive : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } bit; + } EcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 OilPressureMissing : 1; // 0 bit + Uint16 IntakeOverHeat : 1; // 1 bit + Uint16 EngineOverHeat : 1; // 2 bit + Uint16 Actuator : 1; // 3 bit + Uint16 RpmSignal : 1; // 4 bit + Uint16 EngineStartFail : 1; // 5 bit + Uint16 rsvd_padding : 10; // 16bit е + } bit; + } EcuFault; +} CRx310; + +typedef struct ClassRx320 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CRx320; + +typedef struct ClassRx321 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } EcuData; +} CRx321; + +typedef struct ClassRx322 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } EcuData; +} CRx322; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CTx102 Tx102; +extern CTx103 Tx103; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +#endif /* SOURCE_COMM_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf b/.staticdata/.previous/20260113_090354/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf new file mode 100644 index 0000000..c4f5352 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf @@ -0,0 +1,214 @@ +#include "main.h" + +void CApuStartReady(void); +void CApuStopProcedure(Uint16 Level); +void CSetEngineActualRpm(Uint16 Rpm); +static void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); +Uint16 CStartSwitchCheck(void); + + +void CApuOperProcedure(void) +{ + if (CApuSystemAlarmCheck() > 0U || KeyOperValue.KeyList.bit.Emergency == 1U) + { + // ˶ ( , ) + CSetApuOperIndex(APU_OPER_IDX_EMERGENCY); + + CActiveChipSelect(0U); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_STANDBY: + { + if (KeyOperValue.KeyList.bit.EngineStartStop == 1U) + { + CSetApuOperIndex(APU_OPER_IDX_START_CHECK); + + CActiveChipSelect(1U); // õŰ ԷµǸ CS ON + + if (CGetEngCoolantTemperature() < -10) // ð µ üũ + { + CSetApuOperIndex(APU_OPER_IDX_ENGINE_PREHEAT); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_CRANKING); + } + } + break; + } + case APU_OPER_IDX_ENGINE_PREHEAT: + { + break; + } + case APU_OPER_IDX_CRANKING: + { + CSetGcuCommand(GCU_OPER_CMD_CRANKING); + + if (CGetGeneratorRpm() > 800) + { + CSetGcuCommand(GCU_OPER_CMD_STOP_CRANKING); + CSetApuOperIndex(APU_OPER_IDX_CHECK_OPERATION); + } + break; + } + case APU_OPER_IDX_CHECK_OPERATION: + { + + } + } + + + } +} + +void CSetApuOperIndex(eApuOperIdx idx) +{ + GeneralOperValue.uiApuState = (Uint16) idx; +} + +eApuOperIdx CGetApuOperIndex(void) +{ + return (eApuOperIdx)GeneralOperValue.uiApuState; +} + +Uint16 CStartSwitchCheck(void) +{ + return KeyOperValue.KeyList.bit.EngineStartStop; +} + + +Uint16 CApuSystemAlarmCheck(void) +{ + return ((FaultBitValue.ulTotal | Rx210.GcuFault.uiTotal | Rx310.EcuFault.uiTotal) > 0) ? 1U : 0U; +} + +void CSetEngineActualRpm(Uint16 Rpm) +{ + float32 fTemp = (float32) Rpm / 0.125f; // 0.125 mean : J1939 Scaling Factor. + + Tx103.EcuCommand.RpmSetpoint = (Uint16) fTemp; +} + +Uint16 CGetEngineActualRpm(void) +{ + float32 fTemp = (float32) Rx320.EcuData.ActualRpm * 0.125f; + + return (Uint16) fTemp; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.GcuData.Rpm; +} + +static void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if (Command == ECU_OPER_CMD_STOP) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(2400U); + } + else if (Command == ECU_OPER_CMD_START) + { + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; + CSetEngineActualRpm(2400U); + } + else + { + // Emergency + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.EcuData.CoolantTemperature - 40; // µ -40 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenence.ManualCranking == 1U) + { + if (CApuSystemAlarmCheck() == 0U) + { + ; // ˶ 츸 ϵ . + } + } + else + { + ; + } + + if (GeneralOperValue.Maintenence.LampTest == 1U) + { + GPIO_CPU_LED_OPERATION(1U); + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + } + else + { + GPIO_CPU_LED_OPERATION(0U); + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + } + + if (GeneralOperValue.Maintenence.KeyTest == 1U) + { + if ((GPIO_KEY_UP() == 1U) && (GPIO_KEY_DOWN() == 1U)) + { + GeneralOperValue.Maintenence.KeyTest = 0U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + } + } +} + +void CLedControlProcedure(void) +{ + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_EMERGENCY: + { + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_STANDBY: + { + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_ENGINE_STABLED: + { + GPIO_CPU_LED_OPERATION(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + break; + } + default: + { + break; + } + } +} diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ new file mode 100644 index 0000000..3d2dc0f --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ new file mode 100644 index 0000000..4d3413d --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ new file mode 100644 index 0000000..ff2d98b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b b/.staticdata/.previous/20260113_090354/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b new file mode 100644 index 0000000..6b72ad5 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b @@ -0,0 +1,151 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +enum +{ + OLED_LINE_TITLE = 0U, + OLED_LINE_1 = 14U, + OLED_LINE_2 = 27U, + OLED_LINE_3 = 40U, + OLED_LINE_4 = 53U +}; + +enum +{ + OLED_ROW_0 = 0U, + OLED_ROW_1, + OLED_ROW_2, + OLED_ROW_3, + OLED_ROW_4 +}; + +enum +{ + OLED_PASS_DIGIT_1 = 0U, + OLED_PASS_DIGIT_2, + OLED_PASS_DIGIT_3, + OLED_PASS_DIGIT_4 +}; + +typedef enum +{ + OLED_PAGE_APU1 = 0U, // 0 + OLED_PAGE_APU2, // 1 + OLED_PAGE_MENU1, // 2 + OLED_PAGE_MENU2, // 3 + OLED_PAGE_TEMP, // 4 + OLED_PAGE_SENSOR1, // 5 + OLED_PAGE_SENSOR2, // 6 + OLED_PAGE_SENSOR3, // 7 + OLED_PAGE_SENSOR4, // 8 + OLED_PAGE_WARNING1, // 9 + OLED_PAGE_WARNING2, // 10 + OLED_PAGE_FAULT1, // 11 + OLED_PAGE_FAULT2, // 12 + OLED_PAGE_FAULT3, // 13 + OLED_PAGE_FAULT4, // 14 + OLED_PAGE_FAULT5, // 15 + OLED_PAGE_FAULT6, // 16 + OLED_PAGE_RESET_ALARM, // 17 + OLED_PAGE_PASSWORD, // 18 + OLED_PAGE_MAINTENENCE, // 19 + OLED_PAGE_KEY_TEST, // 20 + OLED_PAGE_SHUTDOWN, // 21 + OLED_PAGE_MAX +} EOledPage; + +enum +{ + OLED_MENU_APU = 0U, // 0 + OLED_MENU_TEMP, // 1 + OLED_MENU_SENSOR, // 2 + OLED_MENU_WARNING, // 3 + + OLED_MENU_FAULT = 0U, // 0 + OLED_MENU_RESET, // 1 + OLED_MENU_DEBUG // 2 +}; + +enum +{ + OLED_LINE_FOCUS_1 = 0U, + OLED_LINE_FOCUS_2, + OLED_LINE_FOCUS_3, + OLED_LINE_FOCUS_4 +}; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiAlarmPopCheck; + Uint16 uiAlreadyAlarm; + Uint16 uiPrevAlarmPage; + Uint16 uiResetAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X1; + Uint16 Y1; + Uint16 X2; + Uint16 Y2; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe b/.staticdata/.previous/20260113_090354/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe new file mode 100644 index 0000000..fe8e0e0 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe @@ -0,0 +1,47 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef enum +{ + APU_OPER_IDX_BOOT = 0U, // 0 + APU_OPER_IDX_INITIAL, // 1 + APU_OPER_IDX_POST, // 2 + APU_OPER_IDX_EMERGENCY, // 3 + APU_OPER_IDX_STANDBY, // 4 + APU_OPER_IDX_START_CHECK, // 5 + APU_OPER_IDX_ENGINE_PREHEAT, // 6 + APU_OPER_IDX_CRANKING, // 7 + APU_OPER_IDX_ENGINE_WARM_UP, // 8 + APU_OPER_IDX_CHECK_OPERATION, // 9 + APU_OPER_IDX_GENERATING, // 10 + APU_OPER_IDX_ENGINE_STABLED, // 11 + APU_OPER_IDX_ENGINE_STOP, // 12 + APU_OPER_IDX_ENGINE_COOLDOWN // 13 +} eApuOperIdx; + +typedef enum +{ + GCU_OPER_CMD_STOP = 0U, // 0 + GCU_OPER_CMD_CRANKING, // 1 + GCU_OPER_CMD_STOP_CRANKING, // 2 + GCU_OPER_CMD_GENERATING // 3 +} eGcuCmdIdx; + +typedef enum +{ + ECU_OPER_CMD_STOP = 0U, // 0 + ECU_OPER_CMD_START, // 1 + ECU_OPER_CMD_EMERGENCY // 2 +} eEcuCmdIdx; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +Uint16 CApuSystemAlarmCheck(void); +void CSetApuOperIndex(eApuOperIdx idx); +eApuOperIdx CGetApuOperIndex(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); + +#endif /* SOURCE_OPER_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ new file mode 100644 index 0000000..5b0001b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/.staticdata/.previous/20260113_090354/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/.staticdata/.previous/20260113_090354/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/.staticdata/.previous/20260113_090354/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ new file mode 100644 index 0000000..4ce9ce2 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ new file mode 100644 index 0000000..4831619 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ new file mode 100644 index 0000000..4c4b852 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ new file mode 100644 index 0000000..c40164d --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ new file mode 100644 index 0000000..0aa33dc --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ new file mode 100644 index 0000000..6614163 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ new file mode 100644 index 0000000..3b00d75 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 b/.staticdata/.previous/20260113_090354/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 new file mode 100644 index 0000000..19b41d3 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 @@ -0,0 +1,192 @@ +#ifndef CFONT_H +#define CFONT_H + +const Uint16 EngFontTable[96][9] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ! + { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // # + { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $ + { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // % + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // & + { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' + { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // ( + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // ) + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // * + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // , + { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // - + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // . + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // / + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0 + { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1 + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2 + { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3 + { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4 + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5 + { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6 + { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7 + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8 + { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9 + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // : + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ; + { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // < + { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // = + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // > + { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ? + { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @ + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A + { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B + { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D + { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E + { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G + { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J + { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K + { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M + { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S + { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T + { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V + { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W + { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // Y + { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z + { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [ + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON) + { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ] + { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _ + { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ` + { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b + { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c + { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e + { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k + { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l + { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n + { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q + { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r + { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t + { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w + { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z + { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // { + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // | + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // } + { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~ + { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, //  +}; + +const Uint16 EtcFontTable[81][18] = +{ + { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }, // , A1C9 + { 0x00, 0x06, 0x00, 0x78, 0x07, 0xE0, 0x7F, 0x87, 0xFC, 0x7F, 0x87, 0xE0, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00 }, // , A2BA + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x12, 0xA1, 0x2A, 0x24, 0xC2, 0x48, 0x3C, 0xA4, 0x34, 0x40, 0x00, 0x00 }, // , A7A1 + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x68, 0xA5, 0x4A, 0x54, 0xC5, 0x48, 0x54, 0xA5, 0x54, 0x00, 0x00, 0x00 }, // , A7A2 + { 0x00, 0x00, 0x44, 0x04, 0xA0, 0x4A, 0x1C, 0xA2, 0x4A, 0x24, 0xC2, 0x48, 0x25, 0xA1, 0xE4, 0x00, 0x00, 0x00 }, // , A7A3 + { 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0x05, 0x00, 0x50, 0x06, 0x00, 0x40, 0x0D, 0x00, 0x20, 0x00, 0x00, 0x00 }, // , A7A4 + { 0x00, 0x02, 0x04, 0x20, 0xA2, 0x0A, 0x24, 0xA2, 0x8A, 0x30, 0xC3, 0x08, 0x29, 0x52, 0x62, 0x00, 0x00, 0x00 }, // , A7A5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xC2, 0x52, 0x21, 0x02, 0x10, 0x25, 0x21, 0x8C, 0x00, 0x00, 0x00 }, // , A7A6 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x6A, 0x95, 0x56, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7A7 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x36, 0x94, 0xD6, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7A8 + { 0x00, 0x00, 0x04, 0x00, 0x20, 0x04, 0x76, 0x24, 0x94, 0x49, 0x04, 0x90, 0x49, 0x04, 0x90, 0x00, 0x00, 0x00 }, // , A7A9 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x02, 0x4E, 0x95, 0x56, 0x65, 0x45, 0x54, 0x4D, 0x44, 0x54, 0x00, 0x00, 0x00 }, // , A7AA + { 0x00, 0x00, 0x80, 0x10, 0x01, 0x00, 0x3B, 0x41, 0x2A, 0x12, 0xA1, 0x2A, 0x12, 0xA1, 0x2A, 0x00, 0x00, 0x00 }, // , A7AB + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x44, 0xAA, 0x4A, 0xA4, 0xAA, 0x4A, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7AC + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0xA1, 0x55, 0x29, 0x52, 0x95, 0x35, 0x54, 0x15, 0x40, 0x00, 0x00 }, // , A7AD + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xA5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00 }, // , A7AE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x44, 0xAA, 0x42, 0xA4, 0x2A, 0x4A, 0xA3, 0x2A, 0x00, 0x00, 0x00 }, // , A7AF + { 0x00, 0x04, 0x00, 0x40, 0x04, 0x00, 0x4B, 0x45, 0x2A, 0x62, 0xA6, 0x2A, 0x52, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7B0 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x6A, 0xA5, 0x57, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7B1 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x36, 0xA4, 0xD7, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7B2 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x3B, 0x22, 0x4B, 0x24, 0x82, 0x48, 0x24, 0x82, 0x48, 0x00, 0x00, 0x00 }, // , A7B3 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x01, 0x4E, 0xA5, 0x57, 0x65, 0x46, 0x54, 0x55, 0x44, 0xD4, 0x00, 0x00, 0x00 }, // , A7B4 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x38, 0xC2, 0x52, 0x24, 0xE2, 0x52, 0x25, 0x22, 0x4D, 0x00, 0x00, 0x00 }, // , A7B5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xE1, 0x52, 0x29, 0x22, 0x92, 0x34, 0xE4, 0x12, 0x40, 0xC0, 0x00 }, // , A7B6 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xE5, 0x52, 0x55, 0x25, 0x52, 0x54, 0xE5, 0x52, 0x00, 0xC0, 0x00 }, // , A7B7 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x24, 0xE2, 0x92, 0x31, 0x23, 0x12, 0x28, 0xE2, 0x52, 0x00, 0xC0, 0x00 }, // , A7B8 + { 0x00, 0x02, 0x08, 0x20, 0x82, 0x08, 0x25, 0xC2, 0x88, 0x30, 0x83, 0x08, 0x28, 0xA2, 0x44, 0x00, 0x00, 0x00 }, // , A7B9 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x33, 0x14, 0xC9, 0x43, 0x94, 0x49, 0x4C, 0x93, 0x35, 0x00, 0x00, 0x00 }, // , A7BA + { 0x00, 0x04, 0x01, 0x40, 0x14, 0x01, 0x56, 0x96, 0x95, 0x68, 0xD6, 0x95, 0x59, 0x55, 0x6B, 0x00, 0x00, 0x00 }, // , A7BB + { 0x00, 0x00, 0x5C, 0x05, 0x20, 0x52, 0x1D, 0x22, 0x5C, 0x25, 0x22, 0x52, 0x25, 0x21, 0xDC, 0x00, 0x00, 0x00 }, // , A7BC + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x68, 0xE5, 0x59, 0x55, 0x45, 0x52, 0x55, 0x95, 0x56, 0x00, 0x00, 0x00 }, // , A7BD + { 0x00, 0x00, 0x12, 0x01, 0x10, 0x21, 0x6A, 0xE5, 0x73, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7BE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x39, 0x22, 0x0C, 0x20, 0x00, 0x00 }, // , A7BF + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x25, 0x22, 0x4C, 0x00, 0x00, 0x00 }, // , A7C0 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x61, 0x29, 0x24, 0x42, 0x42, 0x3A, 0x94, 0x06, 0x40, 0x00, 0x00 }, // , A7C1 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC5, 0x52, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7C2 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x39, 0x42, 0x54, 0x25, 0x42, 0x48, 0x38, 0x82, 0x08, 0x20, 0x00, 0x00 }, // , A7C3 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x71, 0x44, 0x94, 0x49, 0x44, 0x88, 0x48, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C4 + { 0x00, 0x00, 0x11, 0x01, 0x10, 0x11, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x44, 0x3A, 0x44, 0x04, 0x40, 0x00, 0x00 }, // , A7C5 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x69, 0x45, 0x54, 0x55, 0x45, 0x48, 0x54, 0x85, 0x48, 0x00, 0x00, 0x00 }, // , A7C6 + { 0x00, 0x04, 0x22, 0x42, 0x24, 0x22, 0x49, 0x45, 0x14, 0x61, 0x46, 0x08, 0x50, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C7 + { 0x00, 0x04, 0x51, 0x45, 0x16, 0xD1, 0x6C, 0xA5, 0x4A, 0x54, 0xA5, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00 }, // , A7C8 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0x44, 0xBE, 0x72, 0x24, 0x22, 0x40, 0x00, 0x00 }, // , A7C9 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0xC4, 0xA2, 0x4A, 0x24, 0xA2, 0x00, 0x00, 0x00 }, // , A7CA + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x5F, 0x3B, 0x14, 0x11, 0x40, 0x00, 0x00 }, // , A7CB + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x68, 0xA5, 0x4A, 0x54, 0xA5, 0x5F, 0x55, 0x15, 0x51, 0x00, 0x00, 0x00 }, // , A7CC + { 0x00, 0x02, 0x04, 0x20, 0x42, 0x04, 0x24, 0xA2, 0x8A, 0x30, 0xA3, 0x1F, 0x29, 0x12, 0x51, 0x00, 0x00, 0x00 }, // , A7CD + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x71, 0x44, 0x14, 0x40, 0x00, 0x00 }, // , A7CE + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x49, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7CF + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x15, 0x51, 0x55, 0x29, 0x52, 0x8A, 0x34, 0xA4, 0x0A, 0x40, 0x00, 0x00 }, // , A7D0 + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x69, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x54, 0xA5, 0x4A, 0x00, 0x00, 0x00 }, // , A7D1 + { 0x00, 0x04, 0x2A, 0x42, 0xA4, 0x2A, 0x4A, 0xA5, 0x2A, 0x62, 0xA6, 0x14, 0x51, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7D2 + { 0x00, 0x04, 0x55, 0x45, 0x56, 0xD5, 0x6D, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x44, 0xA4, 0x4A, 0x00, 0x00, 0x00 }, // , A7D3 + { 0x00, 0x02, 0x40, 0x24, 0x02, 0x40, 0x25, 0xE3, 0xC2, 0x24, 0x42, 0x48, 0x25, 0x02, 0x5E, 0x00, 0x00, 0x00 }, // , A7D4 + { 0x00, 0x04, 0x50, 0x45, 0x04, 0x50, 0x55, 0x75, 0x71, 0x65, 0x26, 0x52, 0x55, 0x45, 0x57, 0x00, 0x00, 0x00 }, // , A7D5 + { 0x00, 0x04, 0x48, 0x44, 0x86, 0xC8, 0x6C, 0xF5, 0x79, 0x54, 0xA5, 0x4A, 0x54, 0xC4, 0x4F, 0x00, 0x00, 0x00 }, // , A7D6 + { 0x00, 0x03, 0x28, 0x4A, 0x84, 0xA8, 0x42, 0xF5, 0xB9, 0x4A, 0xA4, 0xAA, 0x4A, 0xC3, 0xAF, 0x00, 0x00, 0x00 }, // , A7D7 + { 0x00, 0x07, 0xE8, 0x12, 0x81, 0x28, 0x12, 0xF1, 0x39, 0x12, 0xA1, 0x2A, 0x12, 0xC1, 0x2F, 0x00, 0x00, 0x00 }, // , A7D8 + { 0x00, 0x00, 0x00, 0x07, 0x00, 0x88, 0x10, 0x41, 0x04, 0x10, 0x40, 0x88, 0x15, 0x41, 0xDC, 0x00, 0x00, 0x00 }, // , A7D9 + { 0x00, 0x04, 0x1C, 0x42, 0x24, 0x22, 0x4A, 0x25, 0x22, 0x61, 0x46, 0x14, 0x51, 0x44, 0xB6, 0x00, 0x00, 0x00 }, // , A7DA + { 0x00, 0x04, 0x4E, 0x45, 0x16, 0xD1, 0x6D, 0x15, 0x51, 0x54, 0xA5, 0x4A, 0x44, 0xA4, 0x5B, 0x00, 0x00, 0x00 }, // , A7DB + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x72, 0x04, 0x20, 0x40, 0x00, 0x00 }, // , A7DC + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x4A, 0x04, 0xA0, 0x00, 0x00, 0x00 }, // , A7DD + { 0x00, 0x00, 0x0F, 0x00, 0x80, 0x08, 0x12, 0x81, 0x2E, 0x24, 0x82, 0x48, 0x3A, 0x84, 0x08, 0x40, 0x00, 0x00 }, // , A7DE + { 0x00, 0x00, 0x02, 0x00, 0x20, 0x02, 0x6B, 0x25, 0x4A, 0x54, 0xA5, 0x4A, 0x54, 0xA5, 0x72, 0x00, 0x00, 0x00 }, // , A7DF + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x31, 0xC4, 0xA4, 0x42, 0x44, 0x24, 0x4A, 0x43, 0x1C, 0x00, 0x00, 0x00 }, // , A7E0 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x56, 0x36, 0x95, 0x47, 0x54, 0x95, 0x49, 0x54, 0x6B, 0x00, 0x00, 0x00 }, // , A7E1 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x54, 0x4E, 0xC0, 0x07, 0x07, 0x87, 0x86, 0x00, 0xC0, 0x02, 0x00, 0xC0, 0x00 }, // , A7E2 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x57, 0x4E, 0xC0, 0x32, 0x1C, 0x16, 0x1A, 0x03, 0x30, 0x08, 0x03, 0x00, 0x00 }, // , A7E3 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xA2, 0x2C, 0x18, 0x80, 0x48, 0x22, 0x81, 0xC8, 0x00, 0x00, 0x00 }, // , A7E4 + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xC2, 0x52, 0x38, 0xE2, 0x12, 0x21, 0x22, 0x0D, 0x00, 0x00, 0x00 }, // , A7E5 + { 0x00, 0x04, 0x60, 0x45, 0x04, 0x50, 0x55, 0xC5, 0x52, 0x66, 0x66, 0x4A, 0x54, 0xA5, 0x47, 0x00, 0x00, 0x00 }, // , A7E6 + { 0x00, 0x04, 0x58, 0x45, 0x46, 0xD4, 0x6D, 0x65, 0x55, 0x55, 0xB5, 0x55, 0x45, 0x54, 0x53, 0x00, 0x00, 0x00 }, // , A7E7 + { 0x00, 0x03, 0x30, 0x4A, 0x84, 0xA8, 0x42, 0xE5, 0xA9, 0x4B, 0x34, 0xA5, 0x4A, 0x53, 0xA3, 0x00, 0x00, 0x00 }, // , A7E8 + { 0x00, 0x05, 0x50, 0x55, 0x05, 0x50, 0x55, 0xC5, 0x52, 0x55, 0x22, 0x92, 0x29, 0x22, 0x9C, 0x00, 0x00, 0x00 }, // , A7E9 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x26, 0x82, 0x54, 0x25, 0x42, 0x54, 0x25, 0x42, 0x54, 0x00, 0x00, 0x00 }, // , A7EA + { 0x00, 0x01, 0x00, 0x10, 0x01, 0x00, 0x14, 0x41, 0x28, 0x11, 0x01, 0x10, 0x12, 0x81, 0x44, 0x00, 0x00, 0x00 }, // , A7EB + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xE3, 0x92, 0x25, 0x22, 0x52, 0x24, 0xE3, 0x82, 0x00, 0x20, 0x00 }, // , A7EC + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x42, 0x25, 0xA2, 0x49, 0x44, 0x94, 0x48, 0x83, 0x08, 0x03, 0x00, 0x00 }, // , A7ED + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x22, 0x21, 0x22, 0x09, 0x44, 0x94, 0x48, 0x83, 0x08, 0x00, 0x00, 0x00 }, // , A7EE + { 0x24, 0x05, 0x60, 0x56, 0x04, 0xA0, 0x4A, 0xB5, 0xAD, 0x2B, 0x51, 0x35, 0x12, 0xB1, 0x2D, 0x00, 0x20, 0x00 } // , A7EF +}; + +extern const Uint16 EngFontTable[96][9]; +extern const Uint16 EtcFontTable[81][18]; +#endif + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ new file mode 100644 index 0000000..ff7633e --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 b/.staticdata/.previous/20260113_090354/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 new file mode 100644 index 0000000..dcd417b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 @@ -0,0 +1,864 @@ +#include "main.h" + +void CInitAlarmOperValue(void); +void CKeyMainPowerProcess(void); +void CKeyArrowUpProcess(void); +void CKeyArrowDownProcess(void); +void CKeyEnterProcess(void); +void CKeyMenuProcess(void); +void CKeyEngineStartStopProcess(void); +void CKeyEmergencyProcess(void); +void CInitAdcStructure(void); +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh); +Uint32 CGetKey(void); +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void MoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; +CAlarmOperValue AlarmOperValue[IDX_FAULT_MAX]; +CFaultBitValue FaultBitValue; +CKeyOperValue KeyOperValue; + +static const CKeyHandler KeyTable[IDX_KEY_MAX] = +{ + { IDX_KEY_MAIN_POWER, CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, CKeyArrowDownProcess }, + { IDX_KEY_ENTER, CKeyEnterProcess }, + { IDX_KEY_MENU, CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, CKeyEmergencyProcess } +}; + +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN2_I]; + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0f); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0f); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0f); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0f); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0f); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0f); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0f); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + Uint64 ullFaultValue = ((Uint64)FaultBitValue.ulTotal & 0x3FFFFUL) | (((Uint64)Rx210.GcuFault.uiTotal & 0xFFFFU) << 19UL) | (((Uint64)Rx310.EcuFault.uiTotal & 0x3FU) << 35UL); + Uint32 ulWarningValue = ((Uint32)Rx210.GcuWarning.uiTotal & 0x7U) | (((Uint32)Rx310.EcuWarning.uiTotal & 0xFU) << 4U); + Uint16 i; + + if (OledOperValue.uiAlarmPopCheck == 0U) + { + if (ulWarningValue > 0U) + { + for (i = 0U; i < 16U; i++) + { + if ((ulWarningValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = ((i / 9U) + OLED_PAGE_WARNING1); + break; + } + } + } + if (ullFaultValue > 0U) + { + for (i = 0U; i < 64U; i++) + { + if ((ullFaultValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = (((i % 64U) / 8U) + OLED_PAGE_FAULT1); + break; + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0U; + + if (CGetApuOperIndex() == APU_OPER_IDX_EMERGENCY) + { + // Ÿ ƿ ߻ Ʈ Ŭ Ѵ. + GeneralOperValue.Conection.CarComputer = (FaultBitValue.bit.CarCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (FaultBitValue.bit.GcuCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (FaultBitValue.bit.EcuCommTimeOut == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + if (GeneralOperValue.uiAlarmReset == 1U) + { + GeneralOperValue.uiAlarmReset = 0U; + + CInitAlarmOperValue(); + } + } + else + { + if (GeneralOperValue.uiApuState > APU_OPER_IDX_EMERGENCY) + { + // Comm Timeout Checks + FaultBitValue.bit.CarCommTimeout = CAlarmCheck(IDX_FAULT_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GcuCommTimeout = CAlarmCheck(IDX_FAULT_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.EcuCommTimeOut = CAlarmCheck(IDX_FAULT_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK); + + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + // RPM Ǿ Ѵ. + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = ABS(iDiffRpm); + FaultBitValue.bit.RpmError = CAlarmCheck(IDX_FAULT_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK); + } + FaultBitValue.bit.EngineHeatOverCurrent = CAlarmCheck(IDX_FAULT_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GlowPlugOverCurrent = CAlarmCheck(IDX_FAULT_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.SolenoidOverCurrent = CAlarmCheck(IDX_FAULT_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.FuelPumpOverCurrent = CAlarmCheck(IDX_FAULT_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.CoolantPumpOverCurrent = CAlarmCheck(IDX_FAULT_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan1OverCurrent = CAlarmCheck(IDX_FAULT_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan2OverCurrent = CAlarmCheck(IDX_FAULT_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK); + + // Fuse ȣ ġ ϴ CS ON ¿ ۵ϹǷ CS HI , Fuse ȣ HI ܼ + if (CGetApuOperIndex() > APU_OPER_IDX_STANDBY) + { + FaultBitValue.bit.EngineHeatOpen = CheckOpenFault(GPIO_ENGINE_HEATER_CS_READ(), GPIO_ENGINE_HEATER_FUSE()); + FaultBitValue.bit.GlowPlugOpen = CheckOpenFault(GPIO_GLOW_PLUG_CS_READ(), GPIO_GLOW_PLUG_FUSE()); + FaultBitValue.bit.SolenoidOpen = CheckOpenFault(GPIO_SOLENOID_CS_READ(), GPIO_SOLENOID_FUSE()); + FaultBitValue.bit.FuelPumpOpen = CheckOpenFault(GPIO_FUEL_PUMP_CS_READ(), GPIO_FUEL_PUMP_FUSE()); + FaultBitValue.bit.CoolantPumpOpen = CheckOpenFault(GPIO_COOLANT_PUMP_CS_READ(), GPIO_COOLANT_PUMP_FUSE()); + FaultBitValue.bit.Fan1Open = CheckOpenFault(GPIO_FAN1_CS_READ(), GPIO_FAN1_FUSE()); + FaultBitValue.bit.Fan2Open = CheckOpenFault(GPIO_FAN2_CS_READ(), GPIO_FAN2_FUSE()); + } + } + } +} + +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh) +{ + // ȣ 1(High) 1(Fault) ȯ + return ((isCsHigh == 1U) && (isFuseHigh == 1U)) ? 1U : 0U; +} + +void CInitAlarmOperValue(void) +{ + int16 i; + + for (i = 0; i < IDX_FAULT_MAX; i++) + { + (void) memset(&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void) memset(&FaultBitValue, 0, sizeof(CFaultBitValue)); + (void) memset(&CommCheck, 0, sizeof(CCommCheck)); + + // ü/GCU/ECU ȣ ܼ ٸ Լ ó + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[IDX_FAULT_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_RPM_ERR].fCheckLimit = 300.0f; // Value + AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_SOLENOID_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN1_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN2_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime = 10U; // Value + +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_I + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_I + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_I + + AdcRegs.ADCMAXCONV.all = IDX_ADC_MAX; // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + CInitAlarmOperValue(); +} + +void CInitAdcStructure(void) +{ + (void) memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + (void) memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_I.fGain = 0.005637f; + Adc_GlowPlug_I.fGain = 0.005637f; + Adc_Solenoid_I.fGain = 0.005637f; + Adc_FuelPump_I.fGain = 0.005637f; + Adc_CoolantPump_I.fGain = 0.005637f; + Adc_Fan1_I.fGain = 0.005637f; + Adc_Fan2_I.fGain = 0.005637f; + + Adc_EngineHeater_I.fOffset = -2.333f; + Adc_GlowPlug_I.fOffset = -2.333f; + Adc_Solenoid_I.fOffset = -2.333f; + Adc_FuelPump_I.fOffset = -2.333f; + Adc_CoolantPump_I.fOffset = -2.333f; + Adc_Fan1_I.fOffset = -2.333f; + Adc_Fan2_I.fOffset = -2.333f; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ +#if 1 + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 100) + { + AdcBuff->uiSamplingCount = 0; + AdcBuff->fSampledSum /= 100; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledSum) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); + AdcBuff->fSampledSum = 0.0f; + } +#else + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledValue) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); +#endif +} + +Uint32 CGetKey(void) +{ + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + Uint16 ucKeyGpioList[7] = { 67, 39, 31, 30, 29, 66, 64}; + + for (i = 0; i < IDX_KEY_MAX; i++) + { + ucDiv = ucKeyGpioList[i] / 32; + ucMod = ucKeyGpioList[i] % 32; + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + static Uint32 ulLongKeyCnt = 0UL; // Ű īƮ + static Uint16 uiLongKeyProcessed = 0U; // Ű ó Ϸ ÷ (ߺ ) + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~KEY_POWER_MASK; // Ű Ű ϵ, Ű(Bit 0) ȭ (& ~KEY_POWER_MASK) + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // ä͸ + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + // Ű Ű POST ܰ谡 Ѿ Ѵ. + if ((KeyOperValue.uiKeyWaitCount == 0U) && (CGetApuOperIndex() > APU_OPER_IDX_POST)) + { + ulPrevKey = (ulPrevKey & KEY_POWER_MASK) | (ulReadKey & ~KEY_POWER_MASK); // ulPrevKey Ʈ ϰ Ʈ + CKeyCheck(ulChangeKey, ulReadKey); // Ϲ Ű + } + } + } + else + { + // ȭ ä͸ ʱȭ (Ϲ Ű) + // , ִ ulPrevKey ʿ + if ((KeyOperValue.uiKeyWait) != 0U && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // Bit 0 ִ Ȯ (1 = ) + if ((ulReadKey & KEY_POWER_MASK) == KEY_POWER_MASK) + { + // ̹ ó ° ƴ϶ īƮ + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 1(1000ms) + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + CKeyCheck(KEY_POWER_MASK, ulReadKey); // Ű (CKeyCheck Ű Ʈ ) + uiLongKeyProcessed = 1U; // ٽ ʵ ÷ + ulLongKeyCnt = LONG_KEY_TIME; // īƮ ÷ο + } + } + } + else + { + // Ű ʱȭ + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey Bit 0 µ 0 ȭ ( 񱳸 ) + ulPrevKey &= ~KEY_POWER_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + Uint16 i; + + for (i = 0U; i < IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +void CKeyArrowUpProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + } +} + +void CKeyArrowDownProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = OLED_PAGE_APU2; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_4) + { + // Bottom of Menu 1 -> Go to Menu 2 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + MoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CChangePasswordDigit(Uint16 direction) +{ + // Ensure the focus digit is within valid range to avoid out-of-bounds access + if (OledOperValue.uiFocusDigit <= OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void MoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + maxLines - 1U) % maxLines; + } + else // DIR_DOWN + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + 1U) % maxLines; + } +} + +void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case OLED_PAGE_MENU1: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_MENU_APU: + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + break; + } + case OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = OLED_PAGE_TEMP; + break; + } + case OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = OLED_PAGE_WARNING1; + } + break; + } + } + break; + } + case OLED_PAGE_MENU2: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = OLED_PAGE_FAULT1; + break; + } + case OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_RESET_ALARM; + break; + } + case OLED_LINE_FOCUS_3: // Maintenence + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + break; + } + default: + break; + } + break; + } + case OLED_PAGE_PASSWORD: + { + if (OledOperValue.uiFocusDigit < OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + // Check password + const Uint16 uiPassword[4] = DEBUG_MENU_PASSWORD; + + if (memcmp(GeneralOperValue.uiPassword, uiPassword, sizeof(uiPassword)) == 0U) + { + GeneralOperValue.uiMaintenence = 1U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + } + } + break; + } + case OLED_PAGE_RESET_ALARM: + { + // Selected "YES" + if (OledOperValue.uiResetAnswer == 1U) + { + if (CApuSystemAlarmCheck() > 0) + { + GeneralOperValue.uiAlarmReset = 1U; + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + break; + } + case OLED_PAGE_MAINTENENCE: + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenence.ManualCranking = GeneralOperValue.Maintenence.ManualCranking ^ 1U; // Toggle + } + else if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenence.LampTest = GeneralOperValue.Maintenence.LampTest ^ 1U; // Toggle + } + else + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenence.KeyTest = GeneralOperValue.Maintenence.KeyTest ^ 1U; // Toggle + OledOperValue.uiPageNum = OLED_PAGE_KEY_TEST; + } + } + break; + } + default: + { + // Handle Fault/Warning page return logic + if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + if (OledOperValue.uiAlarmPopCheck == 1U) + { + OledOperValue.uiAlreadyAlarm = 1U; + OledOperValue.uiPageNum = OledOperValue.uiPrevAlarmPage; + } + } + break; + } + } +} + +void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_MAINTENENCE)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + GeneralOperValue.uiMaintenence = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + } +} + +void CKeyMainPowerProcess(void) +{ + if (CGetApuOperIndex() <= APU_OPER_IDX_STANDBY) + { + // APU ¿ ġ Է + OledOperValue.uiPageNum = OLED_PAGE_SHUTDOWN; + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, TIME_1SEC) == TIME_OVER) + { + GPIO_POWER_HOLD(0); + } + } +} + +void CKeyEngineStartStopProcess(void) +{ + KeyOperValue.KeyList.bit.EngineStartStop = KeyOperValue.KeyList.bit.EngineStartStop ^ 1U; // Toggle +} + +void CKeyEmergencyProcess(void) +{ + // ġ Ŭ ϱ ؼ APU ýۿ ˶ Ѵ. + KeyOperValue.KeyList.bit.Emergency = KeyOperValue.KeyList.bit.Emergency ^ 1U; // Toggle +} diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ new file mode 100644 index 0000000..9ccf069 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ new file mode 100644 index 0000000..a4564ad --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ new file mode 100644 index 0000000..1461873 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/f9a156ec434632a46725fb267c577743_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/f9a156ec434632a46725fb267c577743_ new file mode 100644 index 0000000..e19cb54 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/f9a156ec434632a46725fb267c577743_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef b/.staticdata/.previous/20260113_090354/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef new file mode 100644 index 0000000..71b6378 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef @@ -0,0 +1,545 @@ +#include "main.h" + +CPowerOnCheckValue PowerOnCheckValue; +CGeneralOperValue GeneralOperValue; + +CSoftTimer SoftTimer[TIMER_MAX]; +CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +Uint32 ulSoftClock; + +void CInitSystem(void); +void CInitGeneralOperValue(void); +void CInitGpio(void); +void CSystemConfigure(void); +void CMappingInterrupt(void); +void CProcessSoftTimer(void); +Uint16 CPowerOnCheck(void); +void CSoftTimerWorkProcess(void); +Uint16 CIsStatusSoftTimer(Uint16 ucTimerIndex); +void CReloadSoftTimer(Uint16 ucTimerIndex); +void CInitSoftTimers(void); +void CInitSoftTimer(void); +void CConfigSoftTimer(Uint16 ucTimerIndex, Uint32 ulDelay); +void CStartSoftTimer(Uint16 ucTimerIndex); +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +Uint32 CGetSoftClock(void); +void CSOftWaitCountCancel(Uint16 Index); + +int main(void) +{ + CSetApuOperIndex(APU_OPER_IDX_BOOT); + + CInitSystem(); + + CInitOled(); + + CSetApuOperIndex(APU_OPER_IDX_INITIAL); + + for ( ; ; ) + { + CSoftTimerWorkProcess(); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == TIME_OVER) + { + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_POST); // Adc Ϸ POST + } + } + } + else if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + if (CPowerOnCheck() == 0U) + { + AdcOperValue.uiOffsetAdjustStart = 1U; // offset . + + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + } + } + else + { + if (GeneralOperValue.uiMaintenence == 0U) + { + // 尡 ־ . + //CApuOperProcedure(); + + CLedControlProcedure(); + + GPIO_ENGINE_HEATER_CS(GPIO_USER_MODE_1()); + GPIO_GLOW_PLUG_CS(GPIO_USER_MODE_1()); + GPIO_SOLENOID_CS(GPIO_USER_MODE_1()); + GPIO_FUEL_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_COOLANT_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_FAN1_CS(GPIO_USER_MODE_1()); + GPIO_FAN2_CS(GPIO_USER_MODE_1()); + } + else + { + CDebugModeProcedure(); + } + } + } +} + +void CSoftTimerWorkProcess(void) +{ + static Uint16 RefeshDelay = 0U; + + if (CIsStatusSoftTimer(TIMER_01MS) == SOFTTIMER_TIME_OVER) // Excute Per 1msec + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > APU_OPER_IDX_POST) // ADC Ϸ + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + if (GeneralOperValue.Maintenence.KeyTest == 0U) + { + // (:Ű׽Ʈ) ƴϸ Ű Է . + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (CIsStatusSoftTimer(TIMER_10MS) == SOFTTIMER_TIME_OVER) // Excute Per 10msec + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataA(); + CSendECanDataB(); + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) + { + if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + CDisplayPostFail(); + } + else + { + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + } + + if (CIsStatusSoftTimer(TIMER_100MS) == SOFTTIMER_TIME_OVER) // Excute Per 100msec + { + CReloadSoftTimer(TIMER_100MS); + + // ǻ ѹ̶ Ǿ ŸӾƿ üũ + if (CApuSystemAlarmCheck() == 0U) + { + // ߻ ŸӾƿ üũ ʴ´. + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer < COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : 0U; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : 0U; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : 0U; + } + } + if (CIsStatusSoftTimer(TIMER_1SEC) == SOFTTIMER_TIME_OVER) // Excute Per 1s + { + CReloadSoftTimer(TIMER_1SEC); + + if (OledOperValue.uiAlreadyAlarm == 1U) // ˶ ߻ 1е ٽ ˾ ϱ . + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_POPUP, (TIME_1SEC * 60UL)) == TIME_OVER) + { + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + else + { + CSOftWaitCountCancel(SOFTTIMER_WAIT_POPUP); + } + } +} + +void CSOftWaitCountCancel(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0f, 100.0f); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0U; // GPIO_COOLING_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U; // GPIO_FUEL_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U; // GPIO_COOLING_FAN1_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U; // GPIO_COOLING_FAN2_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U; // GPIO_GLOW_PLUG_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO6 = 0U; // GPIO_ENGINE_HEATER_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U; // GPIO_STOP_SOLENOID_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U; // GPIO_ECU_ON_OFF + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GPIO_POWER_HOLD(1); + + GPIO_CPU_LED_COM_FAULT_N(1); + GPIO_CPU_LED_COM_RUN_N(1); + GPIO_CPU_LED_COM_STA_N(1); + + EDIS; +} + +void CActiveChipSelect(Uint16 Active) +{ + if (Active == 0U) + { + // Ȳ CS OFFѴ. (0 - CS OFF, 1 - CS ON) + GPIO_ENGINE_HEATER_CS(0); + GPIO_GLOW_PLUG_CS(0); + GPIO_SOLENOID_CS(0); + GPIO_FUEL_PUMP_CS(0); + + GPIO_COOLANT_PUMP_CS(0); + GPIO_FAN1_CS(0); + GPIO_FAN2_CS(0); + } + else + { + //  ¿ EcuSignal ¸ Ȯϰ , ۷ο÷, ̵ַ, Ѵ. + // 0 - CS OFF, 1 - CS ON + GPIO_ENGINE_HEATER_CS(GPIO_ENGINE_HEATER()); + GPIO_GLOW_PLUG_CS(GPIO_GLOW_PLUG()); + GPIO_SOLENOID_CS(GPIO_SOLENOID()); + GPIO_FUEL_PUMP_CS(GPIO_FUEL_PUMP()); + + GPIO_COOLANT_PUMP_CS(1); + GPIO_FAN1_CS(1); + GPIO_FAN2_CS(1); + } +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +void CInitGeneralOperValue(void) +{ + (void) memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + (void) memset(&PowerOnCheckValue, 0x1FF, sizeof(CPowerOnCheckValue)); // Set All bit 1 + + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] = 0; +} + +void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = M_INT1 | M_INT9; + + EDIS; +} + +void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + CConfigSoftTimer(TIMER_1SEC, TIME_1SEC); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); + CStartSoftTimer(TIMER_1SEC); +} + +void CStartSoftTimer(Uint16 ucTimerIndex) +{ + if (SoftTimer[ucTimerIndex].iTimer != -1) + { + SoftTimer[ucTimerIndex].iStart = 1; + } +} + +void CInitSoftTimer(void) +{ + Uint16 i; + + (void) memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void) memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +Uint16 CPowerOnCheck(void) +{ + // Ȯ CAN ͷƮ ߻ , üũ + Uint16 retValue = (*(Uint16*)&PowerOnCheckValue) & 0x7FU; + + PowerOnCheckValue.EngineHeaterSensor = ((Adc_EngineHeater_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.GlowPlugSensor = ((Adc_GlowPlug_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.SolenoidSensor = ((Adc_Solenoid_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.FuelPumpSensor = ((Adc_FuelPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.CoolantPumpSensor = ((Adc_CoolantPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan1Sensor = ((Adc_Fan1_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan2Sensor = ((Adc_Fan2_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + + return retValue; // '0' +} diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ new file mode 100644 index 0000000..0df8e48 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ new file mode 100644 index 0000000..712b04b --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 b/.staticdata/.previous/20260113_090354/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 new file mode 100644 index 0000000..376775e --- /dev/null +++ b/.staticdata/.previous/20260113_090354/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 @@ -0,0 +1,220 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +typedef signed char int8; +typedef unsigned char Uint8; + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "DSP2833x_EPwm_defines.h" +#include "DSP2833x_I2c_defines.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (!GpioDataRegs.GPBDAT.bit.GPIO39) +#define GPIO_KEY_DOWN() (!GpioDataRegs.GPADAT.bit.GPIO31) +#define GPIO_KEY_ENTER() (!GpioDataRegs.GPADAT.bit.GPIO30) +#define GPIO_KEY_MENU() (!GpioDataRegs.GPADAT.bit.GPIO29) +#define GPIO_KEY_POWER() (!GpioDataRegs.GPCDAT.bit.GPIO67) +#define GPIO_KEY_START() (!GpioDataRegs.GPCDAT.bit.GPIO66) +#define GPIO_KEY_EMERGENCY() (!GpioDataRegs.GPCDAT.bit.GPIO64) + +// CS ȰǾ FUSE high ߻ (ips Ĩ Ǵ fuse) +#define GPIO_ENGINE_HEATER_FUSE() (GpioDataRegs.GPADAT.bit.GPIO6) +#define GPIO_GLOW_PLUG_FUSE() (GpioDataRegs.GPADAT.bit.GPIO5) +#define GPIO_SOLENOID_FUSE() (GpioDataRegs.GPADAT.bit.GPIO7) +#define GPIO_FUEL_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO2) +#define GPIO_COOLANT_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO1) +#define GPIO_FAN1_FUSE() (GpioDataRegs.GPADAT.bit.GPIO3) +#define GPIO_FAN2_FUSE() (GpioDataRegs.GPADAT.bit.GPIO4) + +#define GPIO_ECU_ON_OFF() (GpioDataRegs.GPADAT.bit.GPIO8) +#define GPIO_FUEL_PUMP() (GpioDataRegs.GPADAT.bit.GPIO9) +#define GPIO_GLOW_PLUG() (GpioDataRegs.GPADAT.bit.GPIO10) +#define GPIO_SOLENOID() (GpioDataRegs.GPADAT.bit.GPIO11) +#define GPIO_ENGINE_HEATER() (GpioDataRegs.GPADAT.bit.GPIO24) +#define GPIO_USER_MODE_1() (!GpioDataRegs.GPCDAT.bit.GPIO81) +#define GPIO_USER_MODE_2() (!GpioDataRegs.GPCDAT.bit.GPIO82) +#define GPIO_USER_MODE_3() (!GpioDataRegs.GPCDAT.bit.GPIO83) + +#define GPIO_ENGINE_HEATER_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO49) +#define GPIO_GLOW_PLUG_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO27) +#define GPIO_SOLENOID_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO48) +#define GPIO_FUEL_PUMP_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO26) +#define GPIO_COOLANT_PUMP_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO52) +#define GPIO_FAN1_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO50) +#define GPIO_FAN2_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO51) + +// ChipSelect Port +#define GPIO_ENGINE_HEATER_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO49 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1)); +#define GPIO_GLOW_PLUG_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO27 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO27 = 1)); +#define GPIO_SOLENOID_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO48 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1)); +#define GPIO_FUEL_PUMP_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO26 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO26 = 1)); +#define GPIO_COOLANT_PUMP_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO52 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1)); +#define GPIO_FAN1_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO50 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1)); +#define GPIO_FAN2_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO51 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1)); + +// Pannel LED Port +#define GPIO_CPU_LED_STOP(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO12 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO12 = 1)); +#define GPIO_CPU_LED_FAULT(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO14 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO14 = 1)); +#define GPIO_CPU_LED_OPERATION(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO13 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO13 = 1)); + +#define GPIO_OLED_RESET(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO37 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1)); + +#define GPIO_FAULT_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO55 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1)); +#define GPIO_EMERGENCY_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO56 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1)); +#define GPIO_STOP_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO57 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1)); +#define GPIO_START_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO58 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1)); + +#define GPIO_POWER_HOLD(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO65 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1)); +#define GPIO_CPU_LED_COM_FAULT_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO68 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1)); +#define GPIO_CPU_LED_COM_RUN_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO69 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1)); +#define GPIO_CPU_LED_COM_STA_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO70 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1)); + +/* Comment Description + * [!] : + * [?] : ʿ + * [*] : Ǻ + */ + +/* Firmware (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // ȣȯ ʴ ȭ , ȭ +#define FIRMWARE_VERSION_MINOR (0) // ȣȯ Ǹ鼭 ο , ǰų +#define FIRMWARE_VERSION_PATCH (5) // ȣȯ Ǹ鼭 , Ȱ ˾ Ҽ + +/* Version History + * [0.0.1] : DCU Ʈ + * [0.0.2] : DCU ߿ ž + * [0.0.3] : OLED XINTF(BUS) ̺ + * [0.0.4] : OLED ǥ ȭ + * [0.0.5] : CAN-B Ȯ + */ + +#define DEBUG_MENU_PASSWORD {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10U) +#define TIME_10MS (100U) +#define TIME_20MS (200U) +#define TIME_50MS (500U) +#define TIME_100MS (1000U) +#define TIME_500MS (5000U) +#define TIME_1SEC (10000U) + +// 0A ذ 450(0.33V), +/- 150 +#define SENSOR_OFFSET_REF 450 +#define SENSOR_TOLERANCE 150 +#define SENSOR_MIN_LIMIT (SENSOR_OFFSET_REF - SENSOR_TOLERANCE) // 300 +#define SENSOR_MAX_LIMIT (SENSOR_OFFSET_REF + SENSOR_TOLERANCE) // 600 + +#define TIME_OVER (1U) + +#define ABS(x) ((x) < 0 ? -(x) : (x)) + +enum +{ + TIMER_01MS = 0, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0, + SOFTTIMER_WAIT_POPUP, + SOFTTIMER_WAIT_APU_STOP, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef struct ClassPowerOnCheckValue +{ + Uint16 EngineHeaterSensor : 1; + Uint16 GlowPlugSensor : 1; + Uint16 SolenoidSensor : 1; + Uint16 FuelPumpSensor : 1; + Uint16 CoolantPumpSensor : 1; + Uint16 Fan1Sensor : 1; + Uint16 Fan2Sensor : 1; +} CPowerOnCheckValue; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiPassword[4]; + Uint16 uiAlarmOccured; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenence; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd : 4; + Uint16 rsvd_padding : 4; + } GcuCommand; + struct + { + Uint16 EngineStart : 1; + Uint16 EngineStop : 1; + Uint16 rsvd : 2; + Uint16 RpmSetPoint : 2; + Uint16 Override : 1; + Uint16 Emergency : 1; + } EcuCommand; + struct + { + Uint16 CarComputer : 1; + Uint16 Gcu : 1; + Uint16 Ecu : 1; + } Conection; + struct + { + Uint16 ManualCranking : 1; + Uint16 LampTest : 1; + Uint16 KeyTest : 1; + } Maintenence; +} CGeneralOperValue; + +Uint16 CSoftWaitCountProcedure(Uint16 ucIndex, Uint32 ulWaitTime); +void CActiveChipSelect(Uint16 Active); + +extern CGeneralOperValue GeneralOperValue; +extern CPowerOnCheckValue PowerOnCheckValue; + +#endif /* SOURCE_MAIN_H_ */ diff --git a/.staticdata/.previous/20260113_090354/K2DCU/fs/fs_hash_map.json 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\"cs_define_macro_value=__TI_WCHAR_T_BITS__;16\",\n\n \"cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0\",\n\n \"cs_define_macro_value=__TI_STRICT_FP_MODE__;1\",\n\n \"cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1\",\n\n \"cs_set_type_size=int;2\",\n\n \"cs_set_type_size=long;4\",\n\n \"cs_set_type_size=pointer;2\",\n\n \"cs_set_type_size=float;4\",\n\n \"cs_set_type_size=double;4\",\n\n \"cs_plain_char=signed\",\n\n \"cs_plain_bit_field=unsigned\",\n\n \"cs_for_init_scope=outer\",\n\n \"cs_using_std=disable\",\n\n \"gnu_version=40702\"\n\n ],\n\n \"include\": []\n\n },\n\n {\n\n \"language\": \"cpp\",\n\n \"compiler\": \"TI C2000 6.2\",\n\n \"linker\": \"not-used\",\n\n \"archive\": \"not-used\",\n\n \"conf\": [\n\n \"cs_builtin_declaration=\",\n\n \"cs_ignore_single_keyword=far\",\n\n \"cs_ignore_single_keyword=__far\",\n\n \"cs_ignore_single_keyword=cregister\",\n\n \"cs_ignore_single_keyword=interrupt\",\n\n \"cs_ignore_single_keyword=__interrupt\",\n\n \"cs_paren_asm=__asm\",\n\n \"cs_paren_asm=asm\",\n\n \"cs_define_macro_value=__signed_chars__;1\",\n\n \"cs_define_macro_value=__DATE__;\",\n\n \"cs_define_macro_value=__TIME__;\",\n\n \"cs_define_macro_value=__STDC__;1\",\n\n \"cs_define_macro_value=__STDC_VERSION__;199409L\",\n\n \"cs_define_macro_value=__edg_front_end__;1\",\n\n \"cs_define_macro_value=__EDG_VERSION__;404\",\n\n \"cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long\",\n\n \"cs_define_macro_value=__TI_COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__TMS320C2000__;1\",\n\n \"cs_define_macro_value=_TMS320C2000;1\",\n\n \"cs_define_macro_value=__TMS320C28XX__;1\",\n\n \"cs_define_macro_value=_TMS320C28XX;1\",\n\n \"cs_define_macro_value=__TMS320C28X__;1\",\n\n \"cs_define_macro_value=_TMS320C28X;1\",\n\n \"cs_define_macro_value=__TMS320C28XX_FPU32__;1\",\n\n \"cs_define_macro_value=__LARGE_MODEL__;1\",\n\n \"cs_define_macro_value=__SIZE_T_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__PTRDIFF_T_TYPE__;long\",\n\n \"cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int\",\n\n \"cs_define_macro_value=__little_endian__;1\",\n\n \"cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1\",\n\n \"cs_define_macro_value=__TI_WCHAR_T_BITS__;16\",\n\n \"cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0\",\n\n \"cs_define_macro_value=__TI_STRICT_FP_MODE__;1\",\n\n \"cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1\",\n\n \"cs_set_type_size=int;2\",\n\n \"cs_set_type_size=long;4\",\n\n \"cs_set_type_size=pointer;2\",\n\n \"cs_set_type_size=float;4\",\n\n \"cs_set_type_size=double;4\",\n\n \"cs_plain_char=signed\",\n\n \"cs_plain_bit_field=unsigned\",\n\n \"cs_for_init_scope=outer\",\n\n \"cs_using_std=disable\",\n\n \"gnu_version=40702\"\n\n ],\n\n \"include\": []\n\n }\n\n]", + "ci_ini": ";\n\n;\n\n; PA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[PA]\n\n; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.\n\n; default 값은 N 입니다.\n\nCLEAN_MODE=N\n\n;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.\n\n; default 값은 N 입니다.\n\nAUTO_ENCODING_UTF8=N\n\n\n\n; 프로젝트 DB 에 대한 초기화 쿼리\n\nINIT_QUERY=PRAGMA mmap_size=2147418112;\n\n\n\n; 람다 코드를 CFG에 포함할지 여부입니다. \n\n; 초기 값은 'N' 입니다.\n\nDISABLE_LAMBDA_CFG=N\n\n\n\n\n\n; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성\n\n; 초기 값은 'Y' 입니다.\n\nMAKE_UNIQUE_REFINED_DIR=Y\n\n;\n\n;-------------------------------------------------------------------------\n\n;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.\n\n;default 값은 Y 입니다.\n\n[CI]\n\nREINDEX_MODE=Y\n\n\n\n;\n\n;\n\n; DFA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[DFA]\n\nDFA_ENABLE=Y\n\nSCFG_OUT=N\n\nLIMIT_ITER=N\n\nRESULT_OUT=N\n\nITER_OUT=N\n\nTRANSFER_OUT=N\n\nFYCYC_ITER=40\n\n;\n\n;\n\n; Abstract Interpreter 설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"0\",\n\n \"last_capture_time\": \"2026-01-12T02:26:25.095Z\"\n\n}" +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/artifacts.zip b/.staticdata/.previous/20260113_090354/artifacts.zip new file mode 100644 index 0000000..4d258da Binary files /dev/null and b/.staticdata/.previous/20260113_090354/artifacts.zip differ diff --git a/.staticdata/.previous/20260113_090354/cstrace.json b/.staticdata/.previous/20260113_090354/cstrace.json new file mode 100644 index 0000000..8f88c09 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + } +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/error.json b/.staticdata/.previous/20260113_090354/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/.staticdata/.previous/20260113_090354/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/exclude_project.json b/.staticdata/.previous/20260113_090354/exclude_project.json new file mode 100644 index 0000000..2dba8e4 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "Default", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090354/preinclude/gnu_preinclude.h b/.staticdata/.previous/20260113_090354/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_c.h b/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_cpp.h b/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/.staticdata/.previous/20260113_090354/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090505/.hint b/.staticdata/.previous/20260113_090505/.hint new file mode 100644 index 0000000..f255c84 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/.spec b/.staticdata/.previous/20260113_090505/.spec new file mode 100644 index 0000000..0c6a03b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v005\Source\.spec \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090505/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090505/K2DCU/config/.inf b/.staticdata/.previous/20260113_090505/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/K2DCU/config/ci.ini b/.staticdata/.previous/20260113_090505/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090505/K2DCU/config/csa.exe b/.staticdata/.previous/20260113_090505/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090505/K2DCU/config/csa.exe differ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/config/psionic.ini b/.staticdata/.previous/20260113_090505/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 b/.staticdata/.previous/20260113_090505/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 new file mode 100644 index 0000000..476e6ce --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 @@ -0,0 +1,180 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define PI2 (6.283185f) +#define ADC_FREQ (10000.0f) // 10kHz = 0.0001sec +#define ADC_LPF_COFF_TEMP (0.2f) +#define ADC_LPF_GAIN_TEMP (0.00012566f) //(PI2 * ADC_LPF_COFF_TEMP * (1.0f / ADC_FREQ)) +#define ADC_LPF_COFF (30.0f) +#define ADC_LPF_GAIN (0.01884955f) //(PI2 * ADC_LPF_COFF * (1.0f / ADC_FREQ)) + +#define LONG_KEY_TIME (1000UL) +#define KEY_POWER_MASK (0x00000001UL) + +#define COMM_TIME_OUT_COUNT (30U) + +enum +{ + IDX_ADC_ENGINE_HEATER_I = 0U, // 0 + IDX_ADC_GLOW_PLUG_I, // 1 + IDX_ADC_SOLENOID_I, // 2 + IDX_ADC_FUEL_PUMP_I, // 3 + IDX_ADC_COOLANT_PUMP_I, // 4 + IDX_ADC_FAN1_I, // 5 + IDX_ADC_FAN2_I, // 6 + IDX_ADC_MAX +}; + +typedef enum +{ + IDX_FAULT_CAR_COMM = 0U, // 0 + IDX_FAULT_GCU_COMM, // 1 + IDX_FAULT_ECU_COMM, // 2 + IDX_FAULT_RPM_ERR, // 3 + IDX_FAULT_ENGINE_HEAT_OC, // 4 + IDX_FAULT_GLOW_PLUG_OC, // 5 + IDX_FAULT_SOLENOID_OC, // 6 + IDX_FAULT_FUEL_PUMP_OC, // 7 + IDX_FAULT_COOLANT_PUMP_OC, // 8 + IDX_FAULT_FAN1_OC, // 9 + IDX_FAULT_FAN2_OC, // 10 + IDX_FAULT_ENGINE_HEAT_LINE_OPEN, // 11 + IDX_FAULT_GLOW_PLUG_LINE_OPEN, // 12 + IDX_FAULT_SOLENOID_LINE_OPEN, // 13 + IDX_FAULT_FUEL_PUMP_LINE_OPEN, // 14 + IDX_FAULT_COOLANT_PUMP_LINE_OPEN, // 15 + IDX_FAULT_FAN1_LINE_OPEN, // 16 + IDX_FAULT_FAN2_LINE_OPEN, // 17 + IDX_FAULT_MAX +} ALARM_TYPE; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fOffset; + float32 fLpfValue; + float32 fSampledValue; + float32 fGain; + float32 fSampledSum; + float32 fTempAdcOffset; + int16 iAdcValue; + Uint16 uiSamplingCount; +} CAdcCalcValue; + +typedef union ClassFaultBitValue +{ + Uint32 ulTotal; + struct + { + Uint16 CarCommTimeout : 1; + Uint16 GcuCommTimeout : 1; + Uint16 EcuCommTimeOut : 1; + Uint16 RpmError : 1; + Uint16 EngineHeatOverCurrent : 1; + Uint16 GlowPlugOverCurrent : 1; + Uint16 SolenoidOverCurrent : 1; + Uint16 FuelPumpOverCurrent : 1; + + Uint16 CoolantPumpOverCurrent : 1; + Uint16 Fan1OverCurrent : 1; + Uint16 Fan2OverCurrent : 1; + Uint16 EngineHeatOpen : 1; + Uint16 GlowPlugOpen : 1; + Uint16 SolenoidOpen : 1; + Uint16 FuelPumpOpen : 1; + Uint16 CoolantPumpOpen : 1; + + Uint16 Fan1Open : 1; + Uint16 Fan2Open : 1; + Uint16 rsvd_padding1 : 6; + + Uint16 rsvd_padding2 : 8; + } bit; +} CFaultBitValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // Ѱ + Uint16 uiWarning; // 0: , 1: ߻ + Uint16 uiDetectCount; // ī + Uint16 uiReleaseCount; // ī + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, + IDX_KEY_ARR_UP, + IDX_KEY_ARR_DOWN, + IDX_KEY_ENTER, + IDX_KEY_MENU, + IDX_KEY_ENG_START_STOP, + IDX_KEY_EMERGENCY, + IDX_KEY_MAX +} EKeyIndex; + +typedef struct ClassKeyHandler +{ + EKeyIndex eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef union ClassKeyList +{ + Uint16 uiTotal; + struct + { + Uint16 MainPower : 1; + Uint16 ArrowUp : 1; + Uint16 ArrowDown : 1; + Uint16 Enter : 1; + Uint16 Menu : 1; + Uint16 EngineStartStop : 1; + Uint16 Emergency : 1; + } bit; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; +extern CAdcOperValue AdcOperValue; +extern CFaultBitValue FaultBitValue; +extern CKeyOperValue KeyOperValue; + +#endif /* SOURCE_STATE_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ new file mode 100644 index 0000000..9a06c75 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 b/.staticdata/.previous/20260113_090505/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 new file mode 100644 index 0000000..8eb157e --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 @@ -0,0 +1,1443 @@ +#include "main.h" +#include "CFont.h" + +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +volatile Uint16 CommandBus, DataBus; +const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; +int8 cNumBuffer[7] = { 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; +int8 *pNumBuffer = cNumBuffer; + +COledOperValue OledOperValue; + +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenence(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +Uint16 CStrLen(const int8 *s); +void CInitOledModule(void); +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +void CInitProgress(void); +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len); +void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CLcdWrite(Uint16 Data, Uint16 Command); +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CSetPageAddress(Uint16 Address); +void CSetColumnAddress(Uint16 x); +void COledWrite(Uint16 Data, Uint16 Command); +void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(eApuOperIdx idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); + +static const CPageHandler PageTable[OLED_PAGE_MAX] = +{ + { OLED_PAGE_APU1, CPageApu1 }, + { OLED_PAGE_APU2, CPageApu2 }, + { OLED_PAGE_MENU1, CPageMenu1 }, + { OLED_PAGE_MENU2, CPageMenu2 }, + { OLED_PAGE_TEMP, CPageTemp }, + { OLED_PAGE_SENSOR1, CPageSensor1 }, + { OLED_PAGE_SENSOR2, CPageSensor2 }, + { OLED_PAGE_SENSOR3, CPageSensor3 }, + { OLED_PAGE_SENSOR4, CPageSensor4 }, + { OLED_PAGE_WARNING1, CPageWarning1 }, + { OLED_PAGE_WARNING2, CPageWarning2 }, + { OLED_PAGE_FAULT1, CPageFault1 }, + { OLED_PAGE_FAULT2, CPageFault2 }, + { OLED_PAGE_FAULT3, CPageFault3 }, + { OLED_PAGE_FAULT4, CPageFault4 }, + { OLED_PAGE_FAULT5, CPageFault5 }, + { OLED_PAGE_FAULT6, CPageFault6 }, + { OLED_PAGE_RESET_ALARM, CPageAlarmReset }, + { OLED_PAGE_PASSWORD, CPagePassword }, + { OLED_PAGE_MAINTENENCE, CPageMaintenence }, + { OLED_PAGE_KEY_TEST, CPageKeyTest }, + { OLED_PAGE_SHUTDOWN, CPageShutdown } +}; + +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], title, CStrLen(title)); + CDrawStr(10U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0])); + + CDrawTitleBox(CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0]) * 6U); + + if (pageNumStr != NULL) + { + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], pageNumStr, CStrLen(pageNumStr)); + CDrawStr(100U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen(OledOperValue.cStrBuff[OLED_ROW_0])); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY = 0U; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; // Invalid row + } + + CStrncpy(OledOperValue.cStrBuff[row], label, CStrLen(label)); + + if (valueStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], valueStr, CStrLen(valueStr)); + } + + if (unitStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], unitStr, CStrLen(unitStr)); + } + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + CFloatToString(value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + CDecToString((int16)value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + Uint16 drawY = 0U; + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageApu1(void) +{ + const int8 *cTemp = ""; + float32 fTemp; + + // TITLE + CDrawPageTitle("APU Status", "1/2"); + + // LINE 1 + fTemp = Rx220.GcuData.DcVoltage; + CDrawPageLineFloat(OLED_ROW_1, "DC Voltage ", fTemp, " V"); + + // LINE 2 + fTemp = Rx220.GcuData.DcCurrent; + CDrawPageLineFloat(OLED_ROW_2, "DC Current ", fTemp, " A"); + + // LINE 3 + fTemp = (Rx220.GcuData.DcVoltage * Rx220.GcuData.DcCurrent); + CDrawPageLineFloat(OLED_ROW_3, "Power ", fTemp, " kW"); + + // LINE 4 + cTemp = CGetApuStateString((eApuOperIdx)GeneralOperValue.uiApuState); + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_4], "Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[OLED_ROW_4], cTemp); + CStrncat(OledOperValue.cStrBuff[OLED_ROW_4], cTemp, CStrLen(cTemp)); + CDrawStr(0U, OLED_LINE_4, OledOperValue.cStrBuff[OLED_ROW_4], CStrLen(OledOperValue.cStrBuff[OLED_ROW_4])); +} + +static void CPageApu2(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngineActualRpm(); + CDrawPageLineInt(OLED_ROW_1, "ENG.RPM ", (int32)iTemp, " rpm"); + + // LINE 2 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt(OLED_ROW_2, "Coolant ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx320.EcuData.ActualTorque; + CDrawPageLineInt(OLED_ROW_3, "Torque ", (int32)iTemp, " %"); + + // LINE 4 + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, pNumBuffer); + CDrawPageLine(OLED_ROW_4, "ENG.Hour ", pNumBuffer, " Hr"); +} +static void CPageMenu1(void) +{ + // TITLE + CDrawPageTitle("Menu", "1/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "1. APU Status ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "2. Temperature ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "3. Sensor ", NULL, NULL); + + // LINE 4 + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_4, "4. Warning ", NULL, NULL); +} + +static void CPageMenu2(void) +{ + // TITLE + CDrawPageTitle("Menu", "2/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "5. Fault ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "6. Alarm Reset ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "7. Maintenence ", NULL, NULL); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = Rx221.GcuData.PcbTemperature - 40; + CDrawPageLineInt(OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " "); + + // LINE 2 + iTemp = Rx221.GcuData.FetTemperature - 40; + CDrawPageLineInt(OLED_ROW_2, "FET Temp. ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx221.GcuData.GenTemperature1 - 40; + CDrawPageLineInt(OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " "); + + // LINE4 + iTemp = Rx221.GcuData.GenTemperature2 - 40; + CDrawPageLineInt(OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " "); +} +static void CPageSensor1(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "1/4"); + + // LINE 1 + fTemp = (Adc_EngineHeater_I.fLpfValue < 0.0f) ? 0.0f : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "EngineHeater", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_GlowPlug_I.fLpfValue < 0.0f) ? 0.0f : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "GlowPlug ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Solenoid_I.fLpfValue < 0.0f) ? 0.0f : Adc_Solenoid_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Solenoid ", fTemp, " A"); + + // LINE 4 + fTemp = (Adc_FuelPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_FuelPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_4, "FuelPump ", fTemp, " A"); +} + +static void CPageSensor2(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "2/4"); + + // LINE 1 + fTemp = (Adc_CoolantPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "CoolantPump ", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_Fan1_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan1_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "Fan1 ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Fan2_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan2_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Fan2 ", fTemp, " A"); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = Rx321.EcuData.BarometicPressure; + CDrawPageLineInt(OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = Rx321.EcuData.Fan1Speed; + CDrawPageLineInt(OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = Rx321.EcuData.Fan2Speed; + CDrawPageLineInt(OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = Rx321.EcuData.CoolantPumpSpeed; + CDrawPageLineInt(OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = Rx220.GcuData.Rpm; + CDrawPageLineInt(OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "PCBOT:", Rx210.GcuWarning.bit.PcbOverHeat, "FETOT:", Rx210.GcuWarning.bit.FetOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "GEOT1:", Rx210.GcuWarning.bit.GenOverHeat1, "GEOT2:", Rx210.GcuWarning.bit.GenOverHeat2); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "ENGOT:", Rx310.EcuWarning.bit.EngineOverHeat, "L-OIL:", Rx310.EcuWarning.bit.LowOilLevel); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "INTOT:", Rx310.EcuWarning.bit.IntakeOverHeat, "INTLP:", Rx310.EcuWarning.bit.IntakeLoPressure); +} + +static void CPageWarning2(void) +{ + // TITLE + CDrawPageTitle("Warning", "2/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "ENGLT:", Rx310.EcuWarning.bit.EngineLoTemperature, "ENGSF:", Rx310.EcuWarning.bit.EngineSensor); + + // LINE 2 + CDrawPageLineStatus(OLED_ROW_2, "DEFAC:", Rx310.EcuWarning.bit.DefaltValueActive); +} +static void CPageFault1(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "1/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CARCT:", FaultBitValue.bit.CarCommTimeout, "GCUCT:", FaultBitValue.bit.GcuCommTimeout); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ECUCT:", FaultBitValue.bit.EcuCommTimeOut, "RPMER:", FaultBitValue.bit.RpmError); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "EHLOC:", FaultBitValue.bit.EngineHeatOverCurrent, "GPLOC:", FaultBitValue.bit.GlowPlugOverCurrent); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SOLOC:", FaultBitValue.bit.SolenoidOverCurrent, "FPLOC:", FaultBitValue.bit.FuelPumpOverCurrent); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "2/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CPLOC:", FaultBitValue.bit.CoolantPumpOverCurrent, "F1LOC:", FaultBitValue.bit.Fan1OverCurrent); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "F2LOC:", FaultBitValue.bit.Fan2OverCurrent, "EHLLO:", FaultBitValue.bit.EngineHeatOpen); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GPLLO:", FaultBitValue.bit.GlowPlugOpen, "SOLLO:", FaultBitValue.bit.SolenoidOpen); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "FPLLO:", FaultBitValue.bit.FuelPumpOpen, "CPLLO:", FaultBitValue.bit.CoolantPumpOpen); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "3/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "F1LLO:", FaultBitValue.bit.Fan1Open, "F2LLO:", FaultBitValue.bit.Fan2Open); +} + +static void CPageFault4(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "4/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "HTRIP:", Rx210.GcuFault.bit.HwTrip, "HIGBT:", Rx210.GcuFault.bit.HwIgbt); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "HDCOV:", Rx210.GcuFault.bit.HwDc, "GNOCU:", Rx210.GcuFault.bit.GenOverCurrentU); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GNOCV:", Rx210.GcuFault.bit.GenOverCurrentV, "GNOCW:", Rx210.GcuFault.bit.GenOverCurrentW); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SDCOV:", Rx210.GcuFault.bit.DcOverVoltage, "SDCOC:", Rx210.GcuFault.bit.DcOverCurrent); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "5/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "SMOOC:", Rx210.GcuFault.bit.CrankningOverCurrent, "PCBOT:", Rx210.GcuFault.bit.PcbOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "FETOT:", Rx210.GcuFault.bit.FetOverHeat, "GW1OT:", Rx210.GcuFault.bit.GenTempOverHeat1); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GW2OT:", Rx210.GcuFault.bit.GenTempOverHeat2, "GENOS:", Rx210.GcuFault.bit.GenOverSpeed); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "RSICF:", Rx210.GcuFault.bit.ResolverIC, "RSPRT:", Rx210.GcuFault.bit.ResolverParity); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawPageTitle("Ecu Fault", "6/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "OILMS:", Rx310.EcuFault.bit.OilPressureMissing, "INTOT:", Rx310.EcuFault.bit.IntakeOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ENGOT:", Rx310.EcuFault.bit.EngineOverHeat, "ACTUA:", Rx310.EcuFault.bit.Actuator); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "RPMSG:", Rx310.EcuFault.bit.RpmSignal, "ENGSF:", Rx310.EcuFault.bit.EngineStartFail); +} +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 0U) ? (const int8*)"P" : (const int8*)"F"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l3, 13U); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + + switch(row) + { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine(OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + int16 iTemp[2] = { 0, '\0' }; + + // TITLE + CDrawPageTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case OLED_PASS_DIGIT_1: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case OLED_PASS_DIGIT_2: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case OLED_PASS_DIGIT_3: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CTextAlign(OledOperValue.cAlignBuffer, maskBuffer); + CDrawStr(0U, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageMaintenence(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawPageTitle("Maintenence", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "Switch Test ", NULL, NULL); +} +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + Uint16 y = 0U; + switch(row) { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine(OLED_LINE_TITLE + 2U, "Key input Test"); + + // TITLE2 + CDrawCenteredLine(OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + // " Stat:" + Status + // This is special indentation. + // I can reuse CDrawKeyStatusLine if I pass proper label. + // " Stat:" is 19 chars. + CDrawKeyStatusLine(OLED_ROW_2, " Stat:", GPIO_KEY_START(), NULL, 0, NULL, 0); + + // LINE 3 + // " Up:" + s + " " + "Entr:" + s + " " + "Powr:" + s + CDrawKeyStatusLine(OLED_ROW_3, " Up:", GPIO_KEY_UP(), "Entr:", GPIO_KEY_ENTER(), "Powr:", GPIO_KEY_POWER()); + + // LINE 4 + // "Down:" + s + " " + "Menu:" + s + " " + "Emgc:" + s + CDrawKeyStatusLine(OLED_ROW_4, "Down:", GPIO_KEY_DOWN(), "Menu:", GPIO_KEY_MENU(), "Emgc:", GPIO_KEY_EMERGENCY()); +} +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "Shutting down..."); +} +void CSetPage(Uint16 PageNum) +{ + int16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0; i < OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler + } + } +} + +void COledBufferReset(void) +{ + (void) memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void) memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // + CDrawLine(8U, 10U, 10U, 12U); // 𼭸 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // Ʒ + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 𼭸 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // + + if (OledOperValue.uiPageNum != OLED_PAGE_PASSWORD) + { + // ŸƲ ڽ + CDrawLine(98U, 0U, 98U, 9U); // + CDrawLine(98U, 10U, 100U, 12U); // 𼭸 + CDrawLine(101U, 12U, 118U, 12U); // Ʒ + CDrawLine(119U, 12U, 121U, 10U); // 𼭸 + CDrawLine(121U, 0U, 121U, 9U); // + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = y / 8; j < (y + height) / 8; j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + int16 i; + + CInitOledModule(); + + for(uiPageNum = 0; uiPageNum < 8; uiPageNum++) + { + COledWrite((Uint16)(0xB0 | uiPageNum), MODE_COMMAND); + + for(i = 0; i < OLED_WIDTH; i++) + { + COledWrite(0x00, MODE_DATA); + } + } + + CInitProgress(); +} + +void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, OLED_LINE_TITLE, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void) memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = (TXT_MAX_LEN - 1) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0; + i = 0; + + while (str[i] != '\0') // str int8* ̹Ƿ, int8 Ÿ (0) ã + { + uiLen++; + i++; + } + + if (uiLen >= TXT_MAX_LEN) + { + uiIndent = 0; + } + else + { + uiIndent = ((TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < TXT_MAX_LEN)) // ҽ Һ + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = (int8)' '; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = 0; +} + +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // + CDrawLine(x, (y + 1U), x, (y + h)); // + CDrawLine(x, (y + h), w, (y + h)); // Ʒ + CDrawLine(w, (y + 1U), w, (y + h - 1U)); // +} + +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + if (x2 > OledOperValue.Point.X2) + { + OledOperValue.Point.X2 = x2; + } + if (y2 > OledOperValue.Point.Y2) + { + OledOperValue.Point.Y2 = y2; + } +} + +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 tmp = 0, x = 0, y = 0, dx = 0, dy = 0, swapxy = 0; + Uint16 loop_end = 0; + Uint16 minor_limit = 0; // (y) Ѱ谪 + int16 err = 0, ystep = 0; + + dx = x2 - x1; + + dy = (y1 > y2) ? (y1 - y2) : (y2 - y1); + + if (dy > dx) + { + swapxy = 1; + tmp = dx; dx = dy; dy = tmp; + tmp = x1; x1 = y1; y1 = tmp; + tmp = x2; x2 = y2; y2 = tmp; + + loop_end = OLED_HEIGHT - 1; + minor_limit = OLED_WIDTH - 1; + } + else + { + loop_end = OLED_WIDTH - 1; + minor_limit = OLED_HEIGHT - 1; + } + + if (x2 > loop_end) + { + x2 = loop_end; + } + + err = dx >> 1; + ystep = (y2 > y1) ? 1 : -1; + y = y1; + + if (swapxy == 0) + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } + else + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage = y / 8U; + Uint16 uiOffset = y % 8U; + + if (x >= OLED_WIDTH || y >= OLED_HEIGHT) + { + x = OLED_WIDTH; + y = OLED_HEIGHT; + } + else + { + if (x < OLED_WIDTH) + { + if (Color) + { + OledOperValue.uiBuff[x][uiPage] |= (0x01U << uiOffset); + } + else + { + OledOperValue.uiBuff[x][uiPage] &= (Uint16) ~(0x01U << uiOffset); + } + } + } +} + +void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0), MODE_COMMAND); +} + +void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0F) | 0x10; + LowAddress = x & 0x0F; + + COledWrite(LowAddress, MODE_COMMAND); + COledWrite(HighAddress, MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 1; + XintfRegs.XTIMING6.bit.XWRACTIVE = 13; + XintfRegs.XTIMING6.bit.XWRTRAIL = 1; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 1; + XintfRegs.XTIMING6.bit.XRDACTIVE = 13; + XintfRegs.XTIMING6.bit.XRDTRAIL = 1; + + XintfRegs.XTIMING6.bit.X2TIMING = 1; + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len) +{ + Uint16 i; + + if ((len > 0U) && (len < TXT_MAX_LEN)) // ҽ Һ + { + for(i = 0; i < len; i++) + { + if (str[i] & 0x80) + { + CDrawChar(x, y, (Uint16)((str[i] << 8) | str[i + 1]), TXT_TYPE_ETC); + i++; + x += TXT_ENG_WIDTH * 2U; + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + } + } +} + +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0) // Eng Char + { + uiCharWidth = TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = TXT_ENG_WIDTH * 2U; + ch = (ch == 0xA1C9U) ? 0x00U : ch; + pFontData = EtcFontTable[ch]; + } + + CSetDrawRegion(x, y, (x + TXT_ENG_WIDTH), (y + TXT_ENG_HEIGHT)); + + for(j = 0; j < TXT_ENG_HEIGHT; j++) + { + for(i = 0; i < uiCharWidth; i++) + { + if (pFontData[uiFontIndex / 8] & uiBitMask[uiFontIndex % 8]) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +void CInitOledModule(void) +{ + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + GPIO_OLED_RESET(0U); + DELAY_US(2000L); + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + + COledWrite(0xFD, MODE_COMMAND); // Command Lock + COledWrite(0x12, MODE_COMMAND); // + COledWrite(0xAE, MODE_COMMAND); // oled off + COledWrite(0xA1, MODE_COMMAND); // 1U segment column address high to low + + COledWrite(0xC8, MODE_COMMAND); // COM output scan from high to low + + COledWrite(0x81, MODE_COMMAND); // 1U contrast + COledWrite(0xFF, MODE_COMMAND); + + COledWrite(0xAF, MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = OLED_LOAD_PROGRESS_X + 1; +} + +void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +void CInitOledStructure(void) +{ + (void) memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void) memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +Uint16 CStrLen(const int8 *s) +{ + // ּҸ մϴ. + const int8 *p = s; + + // Ͱ ('\0', ASCII 0) Ű ͸ ŵϴ. + // ڿ ӵ ޸ Ǿ ֽϴ. + while (*p != '\0') + { + p++; + } + + // ּ( ) ּ ̰ ڿ ̰ ˴ϴ. + return (Uint16)(p - s); +} + +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + + for (i = 0; i < Size; i++) + { + pTarget[i] = pSource[i]; + } + pTarget[i] = '\0'; +} + +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + + uiTargetSize = (Uint16)CStrLen(pTarget); + + if ((uiTargetSize + Size) < TXT_MAX_LEN) + { + for (i = 0; i < Size; i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = '\0'; + } +} + +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U, uiSignLocate = 0U, i; + Uint16 x, y; + int32 lData = (int32) Data * 10; + int8 cTmp[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + if (lData < 0) + { + // ǥ ڰ + uiSign = 1U; + lData = -lData; + } + + while (lData > 0U) + { + cTmp[x++] = (lData % 10) + '0'; + lData /= 10U; + } + + if (x == 0) // ġ 0 . + { + y = 3U; + Array[y++] = '0'; + } + else + { + y = 5 - x; // Ǵ . + x = x - 1; // ε . + + if (y < 1) + { + uiSignLocate = 0U; + } + else + { + if ((y >= 1) && (y <= 5)) + { + uiSignLocate = (Uint16)(y - 1); // '-' ȣ ǥ ڸ + } + } + + if (uiSign == 1U) // '-' ȣ ǥ ġ ϱ . + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U)) + { + Array[uiSignLocate] = '-'; + } + } + else + { + Array[uiSignLocate] = ' '; + } + + while (x > 0) + { + Array[y++] = cTmp[x--]; + } + } + Array[y] = '\0'; // End of string. +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 x = 0U, y = 0U, i; + int16 iTemp = (int16)(Data * 10); + int8 cTmp[4] = { 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + while (iTemp > 0U) + { + cTmp[x++] = (iTemp % 10) + '0'; + iTemp /= 10U; + } + + if (x == 0U) // ġ 0.0 . + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = '0'; + } + else + { + if (x == 1U) + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + else + { + y = 5U - x; // Ǵ . + x = x - 1U; // ε . + + while (x > 0U) + { + Array[y++] = cTmp[x--]; + if (x == 0U) + { + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + } + } + } + Array[y] = '\0'; // End of string. +} + +void CInitializePage(void) +{ + if (AdcOperValue.uiOffsetAdjustStart == 0U) + { + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < OLED_LOAD_PROGRESS_W - 3) // -3 α׷ ¿ 1ȼ . + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(OLED_ROW_2, "EHT:", PowerOnCheckValue.EngineHeaterSensor, "GPL:", PowerOnCheckValue.GlowPlugSensor, "SOL:", PowerOnCheckValue.SolenoidSensor); + + // LINE 3 + CDrawPostStatusLine(OLED_ROW_3, "FUP:", PowerOnCheckValue.FuelPumpSensor, "CLP:", PowerOnCheckValue.CoolantPumpSensor, "FN1:", PowerOnCheckValue.Fan1Sensor); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(OLED_ROW_4, "FN2:", PowerOnCheckValue.Fan2Sensor, NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +void CReversString(int8 *str, int16 length) +{ + Uint16 i = 0U; + Uint16 end = length - 1U; + int8 temp; + + while (i < end) + { + temp = str[i]; + str[i] = str[end]; + str[end] = temp; + i++; + end--; + } +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = num; // Է¹ (: 1234567 -> "12345.67") + + // 1. Ҽ ° ڸ (100 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 2. Ҽ ù° ڸ (10 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 3. Ҽ + str[i++] = '.'; + + // 4. ȯ + // Է 0̾ ּ "0" do-while + do + { + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + } + while (temp != 0); + + // 5. ä (ڸ ) + // 5ڸ + 1ڸ + Ҽ2ڸ = 8ڸ + while (i < 8U) + { + str[i++] = ' '; + } + + str[i] = '\0'; // ڿ ˸ + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(eApuOperIdx idx) +{ + // ε 1:1 ĪǴ ڿ 迭 static Ͽ Լ ȣ 迭 ٽ ʵ + static const int8* strTable[] = + { + "BOOT", // 0: APU_OPER_IDX_BOOT + "INIT", // 1: APU_OPER_IDX_INITIAL + "POST", // 2: APU_OPER_IDX_POST + "EMERGENCY", // 3: APU_OPER_IDX_EMERGENCY + "STANDBY", // 4: APU_OPER_IDX_STANDBY + "START_CHECK", // 5: APU_OPER_IDX_START_CHECK + "PREHEAT", // 6: APU_OPER_IDX_ACTIVE_ENG_HEAT + "CRANKING", // 7: APU_OPER_IDX_CRANKING + "WARM_UP", // 8: APU_OPER_IDX_ENG_WARMING_UP + "CHECK_OPER", // 9: APU_OPER_IDX_CHECK_OPERATION + "GENERATING", // 10: APU_OPER_IDX_SET_GCU_GEN_START + "STABLED", // 11: APU_OPER_IDX_ENG_START_DONE + "STOP", // 12: APU_OPER_IDX_ENG_STOP_NORMAL + "COOLDOWN" // 13: APU_OPER_IDX_ENG_STOP_COOLDOWN + }; + + return strTable[idx]; +} diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ new file mode 100644 index 0000000..95dd823 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ new file mode 100644 index 0000000..be86c38 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ new file mode 100644 index 0000000..e2d1e35 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ new file mode 100644 index 0000000..545526b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ new file mode 100644 index 0000000..cfe478f --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ new file mode 100644 index 0000000..4714194 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ new file mode 100644 index 0000000..b5a7be5 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void InitXintf(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 b/.staticdata/.previous/20260113_090505/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 new file mode 100644 index 0000000..a9a4b68 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 @@ -0,0 +1,1143 @@ +#include "main.h" + +CCommCheck CommCheck; + +// Tx +static CTx100 Tx100; +static CTx101 Tx101; +CTx102 Tx102; +CTx103 Tx103; +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx130 Tx130; +static CTx131 Tx131; +static CTx132 Tx132; + +// Rx - GCU +static CRx200 Rx200; +static CRx201 Rx201; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +static CRx300 Rx300; +static CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); + +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // ѹ̶ ŵǾٸ ش ġ Ǿٰ Ǵ. + CommCheck.CarComputer = 0U; // ۽ ŸӾƿ īƮ Ŭ + /* + if (ECanShadow.CANRMP.bit.RMP15 == 1U) + { + ECanShadow.CANRMP.bit.RMP15 = 1U; + } + + if (ECanShadow.CANRMP.bit.RMP16 == 1U) + { + ECanShadow.CANRMP.bit.RMP16 = 1U; + } +*/ + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +void CSendECanDataA(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + Uint16 uiTemp; + + // 10ms + ECanaMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.ApuData.PlayState & 0x7U; + + uiTemp = (Tx101.ApuData.AlarmOccured << 0U) | (Tx101.ApuData.Emergency << 1U) | (Tx101.ApuData.PowerSwitch << 2U); + ECanaMboxes.MBOX1.MDL.byte.BYTE1 = uiTemp; + ECanaMboxes.MBOX1.MDL.byte.BYTE2 = Tx101.ApuData.GcuPlayState & 0x7U; + + uiTemp = (Tx101.ApuData.GcuAlarmOccured << 0U) | (Tx101.ApuData.GcuShutdown << 1U); + ECanaMboxes.MBOX1.MDL.byte.BYTE3 = uiTemp; + + uiTemp = (Tx101.ApuData.EcuAlarmOccured << 0U) | + ((Tx101.ApuData.EcuPlayState & 0x3FU) << 1U) | + (Tx101.ApuData.OverrideActive << 4U) | + (Tx101.ApuData.GlowPlugActive << 5U) | + (Tx101.ApuData.HeaterActive << 6U) | + (Tx101.ApuData.OilPressureMissing); + ECanaMboxes.MBOX1.MDH.byte.BYTE4 = uiTemp; + + ECanaMboxes.MBOX1.MDH.byte.BYTE5 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE6 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE7 = 0; + + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanaMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX2.MDH.all = 0x00000000U; + ECanaMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanaMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX3.MDH.all = 0x00000000U; + ECanaMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanaMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX4.MDH.all = 0x00000000U; + ECanaMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanaMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX6.MDH.all = 0x00000000U; + ECanaMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanaMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX7.MDH.all = 0x00000000U; + ECanaMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanaMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX8.MDH.all = 0x00000000U; + ECanaMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanaMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX9.MDH.all = 0x00000000U; + ECanaMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanaMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX28.MDH.all = 0x00000000U; + ECanaMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanaMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX29.MDH.all = 0x00000000U; + ECanaMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanaMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX30.MDH.all = 0x00000000U; + ECanaMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanaRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanaRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.GcuData.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.GcuData.VersionMajor = (Uint8)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.GcuData.VersionMinor = (Uint8)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.GcuData.VersionPatch = (Uint8)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.GcuData.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + + Rx201.GcuData.AlarmOccured = (Uint16)((uiMBOXMdl >> 16U) & 0x1U); + Rx201.GcuData.Shutdown = (Uint16)((uiMBOXMdl >> 17U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX17 - 210h (Ʈ ʵ ) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx210.GcuWarning.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat1 = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat2 = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + + Rx210.GcuFault.bit.HwTrip = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx210.GcuFault.bit.HwIgbt = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx210.GcuFault.bit.HwDc = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentU = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentV = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentW = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + Rx210.GcuFault.bit.DcOverVoltage = (Uint16)((uiMBOXMdl >> 14U) & 0x1U); + Rx210.GcuFault.bit.DcOverCurrent = (Uint16)((uiMBOXMdl >> 15U) & 0x1U); + + Rx210.GcuFault.bit.CrankningOverCurrent = (Uint16)((uiMBOXMdl >> 0U) & 0x1U); + Rx210.GcuFault.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 1U) & 0x1U); + Rx210.GcuFault.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 2U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat1 = (Uint16)((uiMBOXMdl >> 3U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat2 = (Uint16)((uiMBOXMdl >> 4U) & 0x1U); + Rx210.GcuFault.bit.GenOverSpeed = (Uint16)((uiMBOXMdl >> 5U) & 0x1U); + Rx210.GcuFault.bit.ResolverIC = (Uint16)((uiMBOXMdl >> 6U) & 0x1U); + Rx210.GcuFault.bit.ResolverParity = (Uint16)((uiMBOXMdl >> 7U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.GcuData.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.GcuData.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // MDH Reverse: Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.GcuData.Rpm = uiRpmL | (uiRpmH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.GcuData.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.GcuData.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GcuData.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GcuData.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.EcuData.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.EcuData.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.EcuData.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.OperationInfo.AlarmOccured = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx301.OperationInfo.PlayState = (Uint16)((uiMBOXMdl >> 25U) & 0x7U); // (24 + 1) + Rx301.OperationInfo.OverrideActive = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); // (24 + 4) + Rx301.OperationInfo.GlowPlugActive = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx301.OperationInfo.HeaterActive = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx301.OperationInfo.OilPressureMissing = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx310.EcuWarning.bit.reserved = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx310.EcuWarning.bit.LowOilLevel = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx310.EcuWarning.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx310.EcuWarning.bit.IntakeLoPressure = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx310.EcuWarning.bit.EngineLoTemperature = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx310.EcuWarning.bit.EngineSensor = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx310.EcuWarning.bit.DefaltValueActive = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + + // [Reverse] Byte 2 -> >> 8 + Rx310.EcuFault.bit.OilPressureMissing = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx310.EcuFault.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx310.EcuFault.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx310.EcuFault.bit.Actuator = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx310.EcuFault.bit.RpmSignal = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx310.EcuFault.bit.EngineStartFail = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.EcuData.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.EcuData.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.EcuData.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.EcuData.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.EcuData.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.EcuData.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.EcuData.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.EcuData.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.EcuData.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.EcuData.BarometicPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.EcuData.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.EcuData.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.EcuData.TotalOperTimeL) | ((Uint32)Rx322.EcuData.TotalOperTimeH << 16U); + GeneralOperValue.ulTotalOperationHour = (GeneralOperValue.ulTotalOperationHour > 1000000UL) ? 1000000UL : GeneralOperValue.ulTotalOperationHour; + } + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + // 10ms + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = 0x1; + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = 0x2; + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x3; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x4; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x5; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = 0x6; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = 0x7; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = 0x8; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; // 100h + ECanShadow.CANTRS.bit.TRS4 = 1U; // 110h + ECanShadow.CANTRS.bit.TRS5 = 1U; // 120h + ECanShadow.CANTRS.bit.TRS6 = 1U; // 121h + ECanShadow.CANTRS.bit.TRS7 = 1U; // 130h + ECanShadow.CANTRS.bit.TRS8 = 1U; // 131h + ECanShadow.CANTRS.bit.TRS9 = 1U; // 132h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; // 100h + ECanShadow.CANTA.bit.TA4 = 1U; // 110h + ECanShadow.CANTA.bit.TA5 = 1U; // 120h + ECanShadow.CANTA.bit.TA6 = 1U; // 121h + ECanShadow.CANTA.bit.TA7 = 1U; // 130h + ECanShadow.CANTA.bit.TA8 = 1U; // 131h + ECanShadow.CANTA.bit.TA9 = 1U; // 132h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void) memset(&Tx100, 0, sizeof(CTx100)); + (void) memset(&Tx101, 0, sizeof(CTx101)); + (void) memset(&Tx102, 0, sizeof(CTx102)); + (void) memset(&Tx103, 0, sizeof(CTx103)); + (void) memset(&Tx110, 0, sizeof(CTx110)); + (void) memset(&Tx120, 0, sizeof(CTx120)); + (void) memset(&Tx121, 0, sizeof(CTx121)); + (void) memset(&Tx130, 0, sizeof(CTx130)); + (void) memset(&Tx131, 0, sizeof(CTx131)); + (void) memset(&Tx132, 0, sizeof(CTx132)); + + // Rx - GCU + (void) memset(&Rx200, 0, sizeof(CRx200)); + (void) memset(&Rx201, 0, sizeof(CRx201)); + (void) memset(&Rx210, 0, sizeof(CRx210)); + (void) memset(&Rx220, 0, sizeof(CRx220)); + (void) memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void) memset(&Rx300, 0, sizeof(CRx300)); + (void) memset(&Rx301, 0, sizeof(CRx301)); + (void) memset(&Rx310, 0, sizeof(CRx310)); + (void) memset(&Rx320, 0, sizeof(CRx320)); + (void) memset(&Rx321, 0, sizeof(CRx321)); + (void) memset(&Rx322, 0, sizeof(CRx322)); +} diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 b/.staticdata/.previous/20260113_090505/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 new file mode 100644 index 0000000..e8d04e5 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 @@ -0,0 +1,434 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + struct + { + Uint16 Heartbit : 16; + Uint16 : 8; + Uint16 : 8; + Uint16 : 8; + Uint16 VersionMajor : 8; + Uint16 VersionMinor : 8; + Uint16 VersionPatch : 8; + } ApuData; +} CTx100; + +typedef struct ClassTx101 +{ + struct + { + /* byte 0 */ + Uint16 PlayState : 3; + Uint16 : 5; + + /* byte 1 */ + Uint16 AlarmOccured : 1; + Uint16 Emergency : 1; + Uint16 PowerSwitch : 1; + Uint16 : 5; + + /* byte 2 */ + Uint16 GcuPlayState : 3; + Uint16 : 5; + + /* byte 3 */ + Uint16 GcuAlarmOccured : 1; + Uint16 GcuShutdown : 1; + Uint16 : 6; + + /* byte 4 */ + Uint16 EcuAlarmOccured : 1; + Uint16 EcuPlayState : 3; + Uint16 OverrideActive : 1; + Uint16 GlowPlugActive : 1; + Uint16 HeaterActive : 1; + Uint16 OilPressureMissing : 1; + } ApuData; +} CTx101; + +typedef struct ClassTx102 +{ + struct + { + Uint16 PlayCommand : 4; // 0:3 bit + Uint16 rsvd_padding1 : 4; // 4:7 bit + Uint16 rsvd_padding2 : 8; // 1 byte + Uint16 rsvd_padding3 : 16; // 2:3 byte + Uint16 rsvd_padding4 : 16; // 4:5 byte + Uint16 rsvd_padding5 : 16; // 6:7 byte + } GcuCommand; +} CTx102; + +typedef struct ClassTx103 +{ + struct + { + Uint16 EngineStart : 8; // 0 byte + Uint16 EngineStop : 8; // 1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 RpmSetpoint : 16; // 4:5 byte + Uint16 Override : 8; // 6 byte + Uint16 Emergency : 8; // 7 byte + } EcuCommand; +} CTx103; + +typedef struct ClassTx110 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilLevel : 1; // 1 bit + Uint16 IntakeOverHeat : 1; // 2 bit + Uint16 IntakeLoPressure : 1; // 3 bit + Uint16 EngineLoTemperature : 1; // 4 bit + Uint16 EngineSensor : 1; // 5 bit + Uint16 DefaltValueActive : 1; // 6 bit + Uint16 rsvd_padding : 1; // 16bit е + } bit; + } EcuWarning; + + struct + { + CFaultBitValue ApuFault; + }; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + } GcuFault; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilPressure : 1; // 1 bit + Uint16 Actuator : 1; // 2 bit + Uint16 RpmSignal : 1; // 3 bit + Uint16 EngineStartFail : 1; // 4 bit + Uint16 rsvd_padding : 11; // 16bit е + } bit; + } EcuFault; +} CTx110; + +typedef struct ClassTx120 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx120; + +typedef struct ClassTx121 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx121; + +typedef struct ClassTx130 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CTx130; + +typedef struct ClassTx131 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding1 : 8; // 6 byte + Uint16 rsvd_padding2 : 8; // 7 byte + } EcuData; +} CTx131; + +typedef struct ClassTx132 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } EcuData; +} CTx132; + +typedef struct ClassRx200 +{ + struct + { + Uint16 HeartBit : 16; // 0:1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 rsvd_padding3 : 8; // 4 byte + Uint16 VersionMajor : 8; // 5 byte + Uint16 VersionMinor : 8; // 6 byte + Uint16 VersionPatch : 8; // 7 byte + } GcuData; +} CRx200; + +typedef struct ClassRx201 +{ + struct + { + Uint16 PlayState : 3; // 0:3 bit + Uint16 rsvd_padding1 : 5; // 4:7 bit + + Uint16 AlarmOccured : 1; // 0 bit + Uint16 Shutdown : 1; // 1 bit + Uint16 rsvd_padding2 : 6; // 2:7 bit + } GcuData; +} CRx201; + +typedef struct ClassRx210 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + }GcuFault; +} CRx210; + +typedef struct ClassRx220 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } GcuData; +} CRx220; + +typedef struct ClassRx221 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } GcuData; +} CRx221; + +typedef struct ClassRx300 +{ + struct + { + Uint16 VersionMajor : 8; // 0 byte + Uint16 VersionMinor : 8; // 1 byte + Uint16 VersionPatch : 8; // 2 byte + Uint16 rsvd_padding1 : 8; // 3 byte + Uint16 rsvd_padding2 : 16; // 4:5 byte + Uint16 rsvd_padding3 : 16; // 6:7 byte + } EcuData; +} CRx300; + +typedef struct ClassRx301 +{ + struct + { + Uint16 AlarmOccured : 1; // 0 bit + Uint16 PlayState : 3; // 1:3 bit + Uint16 OverrideActive : 1; // 4 bit + Uint16 GlowPlugActive : 1; // 5 bit + Uint16 HeaterActive : 1; // 6 bit + Uint16 OilPressureMissing : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } OperationInfo; +} CRx301; + +typedef struct ClassRx310 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 reserved : 1; // 1 bit + Uint16 LowOilLevel : 1; // 2 bit + Uint16 IntakeOverHeat : 1; // 3 bit + Uint16 IntakeLoPressure : 1; // 4 bit + Uint16 EngineLoTemperature : 1; // 5 bit + Uint16 EngineSensor : 1; // 6 bit + Uint16 DefaltValueActive : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } bit; + } EcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 OilPressureMissing : 1; // 0 bit + Uint16 IntakeOverHeat : 1; // 1 bit + Uint16 EngineOverHeat : 1; // 2 bit + Uint16 Actuator : 1; // 3 bit + Uint16 RpmSignal : 1; // 4 bit + Uint16 EngineStartFail : 1; // 5 bit + Uint16 rsvd_padding : 10; // 16bit е + } bit; + } EcuFault; +} CRx310; + +typedef struct ClassRx320 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CRx320; + +typedef struct ClassRx321 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } EcuData; +} CRx321; + +typedef struct ClassRx322 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } EcuData; +} CRx322; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CTx102 Tx102; +extern CTx103 Tx103; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +#endif /* SOURCE_COMM_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf b/.staticdata/.previous/20260113_090505/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf new file mode 100644 index 0000000..c4f5352 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf @@ -0,0 +1,214 @@ +#include "main.h" + +void CApuStartReady(void); +void CApuStopProcedure(Uint16 Level); +void CSetEngineActualRpm(Uint16 Rpm); +static void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); +Uint16 CStartSwitchCheck(void); + + +void CApuOperProcedure(void) +{ + if (CApuSystemAlarmCheck() > 0U || KeyOperValue.KeyList.bit.Emergency == 1U) + { + // ˶ ( , ) + CSetApuOperIndex(APU_OPER_IDX_EMERGENCY); + + CActiveChipSelect(0U); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_STANDBY: + { + if (KeyOperValue.KeyList.bit.EngineStartStop == 1U) + { + CSetApuOperIndex(APU_OPER_IDX_START_CHECK); + + CActiveChipSelect(1U); // õŰ ԷµǸ CS ON + + if (CGetEngCoolantTemperature() < -10) // ð µ üũ + { + CSetApuOperIndex(APU_OPER_IDX_ENGINE_PREHEAT); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_CRANKING); + } + } + break; + } + case APU_OPER_IDX_ENGINE_PREHEAT: + { + break; + } + case APU_OPER_IDX_CRANKING: + { + CSetGcuCommand(GCU_OPER_CMD_CRANKING); + + if (CGetGeneratorRpm() > 800) + { + CSetGcuCommand(GCU_OPER_CMD_STOP_CRANKING); + CSetApuOperIndex(APU_OPER_IDX_CHECK_OPERATION); + } + break; + } + case APU_OPER_IDX_CHECK_OPERATION: + { + + } + } + + + } +} + +void CSetApuOperIndex(eApuOperIdx idx) +{ + GeneralOperValue.uiApuState = (Uint16) idx; +} + +eApuOperIdx CGetApuOperIndex(void) +{ + return (eApuOperIdx)GeneralOperValue.uiApuState; +} + +Uint16 CStartSwitchCheck(void) +{ + return KeyOperValue.KeyList.bit.EngineStartStop; +} + + +Uint16 CApuSystemAlarmCheck(void) +{ + return ((FaultBitValue.ulTotal | Rx210.GcuFault.uiTotal | Rx310.EcuFault.uiTotal) > 0) ? 1U : 0U; +} + +void CSetEngineActualRpm(Uint16 Rpm) +{ + float32 fTemp = (float32) Rpm / 0.125f; // 0.125 mean : J1939 Scaling Factor. + + Tx103.EcuCommand.RpmSetpoint = (Uint16) fTemp; +} + +Uint16 CGetEngineActualRpm(void) +{ + float32 fTemp = (float32) Rx320.EcuData.ActualRpm * 0.125f; + + return (Uint16) fTemp; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.GcuData.Rpm; +} + +static void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if (Command == ECU_OPER_CMD_STOP) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(2400U); + } + else if (Command == ECU_OPER_CMD_START) + { + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; + CSetEngineActualRpm(2400U); + } + else + { + // Emergency + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.EcuData.CoolantTemperature - 40; // µ -40 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenence.ManualCranking == 1U) + { + if (CApuSystemAlarmCheck() == 0U) + { + ; // ˶ 츸 ϵ . + } + } + else + { + ; + } + + if (GeneralOperValue.Maintenence.LampTest == 1U) + { + GPIO_CPU_LED_OPERATION(1U); + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + } + else + { + GPIO_CPU_LED_OPERATION(0U); + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + } + + if (GeneralOperValue.Maintenence.KeyTest == 1U) + { + if ((GPIO_KEY_UP() == 1U) && (GPIO_KEY_DOWN() == 1U)) + { + GeneralOperValue.Maintenence.KeyTest = 0U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + } + } +} + +void CLedControlProcedure(void) +{ + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_EMERGENCY: + { + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_STANDBY: + { + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_ENGINE_STABLED: + { + GPIO_CPU_LED_OPERATION(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + break; + } + default: + { + break; + } + } +} diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ new file mode 100644 index 0000000..3d2dc0f --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ new file mode 100644 index 0000000..4d3413d --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ new file mode 100644 index 0000000..ff2d98b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b b/.staticdata/.previous/20260113_090505/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b new file mode 100644 index 0000000..6b72ad5 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b @@ -0,0 +1,151 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +enum +{ + OLED_LINE_TITLE = 0U, + OLED_LINE_1 = 14U, + OLED_LINE_2 = 27U, + OLED_LINE_3 = 40U, + OLED_LINE_4 = 53U +}; + +enum +{ + OLED_ROW_0 = 0U, + OLED_ROW_1, + OLED_ROW_2, + OLED_ROW_3, + OLED_ROW_4 +}; + +enum +{ + OLED_PASS_DIGIT_1 = 0U, + OLED_PASS_DIGIT_2, + OLED_PASS_DIGIT_3, + OLED_PASS_DIGIT_4 +}; + +typedef enum +{ + OLED_PAGE_APU1 = 0U, // 0 + OLED_PAGE_APU2, // 1 + OLED_PAGE_MENU1, // 2 + OLED_PAGE_MENU2, // 3 + OLED_PAGE_TEMP, // 4 + OLED_PAGE_SENSOR1, // 5 + OLED_PAGE_SENSOR2, // 6 + OLED_PAGE_SENSOR3, // 7 + OLED_PAGE_SENSOR4, // 8 + OLED_PAGE_WARNING1, // 9 + OLED_PAGE_WARNING2, // 10 + OLED_PAGE_FAULT1, // 11 + OLED_PAGE_FAULT2, // 12 + OLED_PAGE_FAULT3, // 13 + OLED_PAGE_FAULT4, // 14 + OLED_PAGE_FAULT5, // 15 + OLED_PAGE_FAULT6, // 16 + OLED_PAGE_RESET_ALARM, // 17 + OLED_PAGE_PASSWORD, // 18 + OLED_PAGE_MAINTENENCE, // 19 + OLED_PAGE_KEY_TEST, // 20 + OLED_PAGE_SHUTDOWN, // 21 + OLED_PAGE_MAX +} EOledPage; + +enum +{ + OLED_MENU_APU = 0U, // 0 + OLED_MENU_TEMP, // 1 + OLED_MENU_SENSOR, // 2 + OLED_MENU_WARNING, // 3 + + OLED_MENU_FAULT = 0U, // 0 + OLED_MENU_RESET, // 1 + OLED_MENU_DEBUG // 2 +}; + +enum +{ + OLED_LINE_FOCUS_1 = 0U, + OLED_LINE_FOCUS_2, + OLED_LINE_FOCUS_3, + OLED_LINE_FOCUS_4 +}; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiAlarmPopCheck; + Uint16 uiAlreadyAlarm; + Uint16 uiPrevAlarmPage; + Uint16 uiResetAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X1; + Uint16 Y1; + Uint16 X2; + Uint16 Y2; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe b/.staticdata/.previous/20260113_090505/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe new file mode 100644 index 0000000..fe8e0e0 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe @@ -0,0 +1,47 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef enum +{ + APU_OPER_IDX_BOOT = 0U, // 0 + APU_OPER_IDX_INITIAL, // 1 + APU_OPER_IDX_POST, // 2 + APU_OPER_IDX_EMERGENCY, // 3 + APU_OPER_IDX_STANDBY, // 4 + APU_OPER_IDX_START_CHECK, // 5 + APU_OPER_IDX_ENGINE_PREHEAT, // 6 + APU_OPER_IDX_CRANKING, // 7 + APU_OPER_IDX_ENGINE_WARM_UP, // 8 + APU_OPER_IDX_CHECK_OPERATION, // 9 + APU_OPER_IDX_GENERATING, // 10 + APU_OPER_IDX_ENGINE_STABLED, // 11 + APU_OPER_IDX_ENGINE_STOP, // 12 + APU_OPER_IDX_ENGINE_COOLDOWN // 13 +} eApuOperIdx; + +typedef enum +{ + GCU_OPER_CMD_STOP = 0U, // 0 + GCU_OPER_CMD_CRANKING, // 1 + GCU_OPER_CMD_STOP_CRANKING, // 2 + GCU_OPER_CMD_GENERATING // 3 +} eGcuCmdIdx; + +typedef enum +{ + ECU_OPER_CMD_STOP = 0U, // 0 + ECU_OPER_CMD_START, // 1 + ECU_OPER_CMD_EMERGENCY // 2 +} eEcuCmdIdx; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +Uint16 CApuSystemAlarmCheck(void); +void CSetApuOperIndex(eApuOperIdx idx); +eApuOperIdx CGetApuOperIndex(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); + +#endif /* SOURCE_OPER_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ new file mode 100644 index 0000000..5b0001b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/.staticdata/.previous/20260113_090505/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/.staticdata/.previous/20260113_090505/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/.staticdata/.previous/20260113_090505/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ new file mode 100644 index 0000000..4ce9ce2 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ new file mode 100644 index 0000000..4831619 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ new file mode 100644 index 0000000..4c4b852 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ new file mode 100644 index 0000000..c40164d --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ new file mode 100644 index 0000000..0aa33dc --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ new file mode 100644 index 0000000..6614163 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ new file mode 100644 index 0000000..3b00d75 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 b/.staticdata/.previous/20260113_090505/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 new file mode 100644 index 0000000..19b41d3 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 @@ -0,0 +1,192 @@ +#ifndef CFONT_H +#define CFONT_H + +const Uint16 EngFontTable[96][9] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ! + { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // # + { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $ + { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // % + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // & + { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' + { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // ( + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // ) + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // * + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // , + { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // - + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // . + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // / + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0 + { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1 + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2 + { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3 + { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4 + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5 + { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6 + { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7 + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8 + { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9 + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // : + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ; + { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // < + { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // = + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // > + { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ? + { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @ + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A + { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B + { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D + { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E + { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G + { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J + { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K + { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M + { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S + { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T + { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V + { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W + { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // Y + { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z + { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [ + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON) + { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ] + { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _ + { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ` + { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b + { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c + { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e + { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k + { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l + { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n + { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q + { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r + { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t + { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w + { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z + { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // { + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // | + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // } + { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~ + { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, //  +}; + +const Uint16 EtcFontTable[81][18] = +{ + { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }, // , A1C9 + { 0x00, 0x06, 0x00, 0x78, 0x07, 0xE0, 0x7F, 0x87, 0xFC, 0x7F, 0x87, 0xE0, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00 }, // , A2BA + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x12, 0xA1, 0x2A, 0x24, 0xC2, 0x48, 0x3C, 0xA4, 0x34, 0x40, 0x00, 0x00 }, // , A7A1 + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x68, 0xA5, 0x4A, 0x54, 0xC5, 0x48, 0x54, 0xA5, 0x54, 0x00, 0x00, 0x00 }, // , A7A2 + { 0x00, 0x00, 0x44, 0x04, 0xA0, 0x4A, 0x1C, 0xA2, 0x4A, 0x24, 0xC2, 0x48, 0x25, 0xA1, 0xE4, 0x00, 0x00, 0x00 }, // , A7A3 + { 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0x05, 0x00, 0x50, 0x06, 0x00, 0x40, 0x0D, 0x00, 0x20, 0x00, 0x00, 0x00 }, // , A7A4 + { 0x00, 0x02, 0x04, 0x20, 0xA2, 0x0A, 0x24, 0xA2, 0x8A, 0x30, 0xC3, 0x08, 0x29, 0x52, 0x62, 0x00, 0x00, 0x00 }, // , A7A5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xC2, 0x52, 0x21, 0x02, 0x10, 0x25, 0x21, 0x8C, 0x00, 0x00, 0x00 }, // , A7A6 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x6A, 0x95, 0x56, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7A7 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x36, 0x94, 0xD6, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7A8 + { 0x00, 0x00, 0x04, 0x00, 0x20, 0x04, 0x76, 0x24, 0x94, 0x49, 0x04, 0x90, 0x49, 0x04, 0x90, 0x00, 0x00, 0x00 }, // , A7A9 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x02, 0x4E, 0x95, 0x56, 0x65, 0x45, 0x54, 0x4D, 0x44, 0x54, 0x00, 0x00, 0x00 }, // , A7AA + { 0x00, 0x00, 0x80, 0x10, 0x01, 0x00, 0x3B, 0x41, 0x2A, 0x12, 0xA1, 0x2A, 0x12, 0xA1, 0x2A, 0x00, 0x00, 0x00 }, // , A7AB + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x44, 0xAA, 0x4A, 0xA4, 0xAA, 0x4A, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7AC + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0xA1, 0x55, 0x29, 0x52, 0x95, 0x35, 0x54, 0x15, 0x40, 0x00, 0x00 }, // , A7AD + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xA5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00 }, // , A7AE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x44, 0xAA, 0x42, 0xA4, 0x2A, 0x4A, 0xA3, 0x2A, 0x00, 0x00, 0x00 }, // , A7AF + { 0x00, 0x04, 0x00, 0x40, 0x04, 0x00, 0x4B, 0x45, 0x2A, 0x62, 0xA6, 0x2A, 0x52, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7B0 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x6A, 0xA5, 0x57, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7B1 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x36, 0xA4, 0xD7, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7B2 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x3B, 0x22, 0x4B, 0x24, 0x82, 0x48, 0x24, 0x82, 0x48, 0x00, 0x00, 0x00 }, // , A7B3 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x01, 0x4E, 0xA5, 0x57, 0x65, 0x46, 0x54, 0x55, 0x44, 0xD4, 0x00, 0x00, 0x00 }, // , A7B4 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x38, 0xC2, 0x52, 0x24, 0xE2, 0x52, 0x25, 0x22, 0x4D, 0x00, 0x00, 0x00 }, // , A7B5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xE1, 0x52, 0x29, 0x22, 0x92, 0x34, 0xE4, 0x12, 0x40, 0xC0, 0x00 }, // , A7B6 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xE5, 0x52, 0x55, 0x25, 0x52, 0x54, 0xE5, 0x52, 0x00, 0xC0, 0x00 }, // , A7B7 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x24, 0xE2, 0x92, 0x31, 0x23, 0x12, 0x28, 0xE2, 0x52, 0x00, 0xC0, 0x00 }, // , A7B8 + { 0x00, 0x02, 0x08, 0x20, 0x82, 0x08, 0x25, 0xC2, 0x88, 0x30, 0x83, 0x08, 0x28, 0xA2, 0x44, 0x00, 0x00, 0x00 }, // , A7B9 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x33, 0x14, 0xC9, 0x43, 0x94, 0x49, 0x4C, 0x93, 0x35, 0x00, 0x00, 0x00 }, // , A7BA + { 0x00, 0x04, 0x01, 0x40, 0x14, 0x01, 0x56, 0x96, 0x95, 0x68, 0xD6, 0x95, 0x59, 0x55, 0x6B, 0x00, 0x00, 0x00 }, // , A7BB + { 0x00, 0x00, 0x5C, 0x05, 0x20, 0x52, 0x1D, 0x22, 0x5C, 0x25, 0x22, 0x52, 0x25, 0x21, 0xDC, 0x00, 0x00, 0x00 }, // , A7BC + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x68, 0xE5, 0x59, 0x55, 0x45, 0x52, 0x55, 0x95, 0x56, 0x00, 0x00, 0x00 }, // , A7BD + { 0x00, 0x00, 0x12, 0x01, 0x10, 0x21, 0x6A, 0xE5, 0x73, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7BE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x39, 0x22, 0x0C, 0x20, 0x00, 0x00 }, // , A7BF + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x25, 0x22, 0x4C, 0x00, 0x00, 0x00 }, // , A7C0 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x61, 0x29, 0x24, 0x42, 0x42, 0x3A, 0x94, 0x06, 0x40, 0x00, 0x00 }, // , A7C1 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC5, 0x52, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7C2 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x39, 0x42, 0x54, 0x25, 0x42, 0x48, 0x38, 0x82, 0x08, 0x20, 0x00, 0x00 }, // , A7C3 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x71, 0x44, 0x94, 0x49, 0x44, 0x88, 0x48, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C4 + { 0x00, 0x00, 0x11, 0x01, 0x10, 0x11, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x44, 0x3A, 0x44, 0x04, 0x40, 0x00, 0x00 }, // , A7C5 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x69, 0x45, 0x54, 0x55, 0x45, 0x48, 0x54, 0x85, 0x48, 0x00, 0x00, 0x00 }, // , A7C6 + { 0x00, 0x04, 0x22, 0x42, 0x24, 0x22, 0x49, 0x45, 0x14, 0x61, 0x46, 0x08, 0x50, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C7 + { 0x00, 0x04, 0x51, 0x45, 0x16, 0xD1, 0x6C, 0xA5, 0x4A, 0x54, 0xA5, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00 }, // , A7C8 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0x44, 0xBE, 0x72, 0x24, 0x22, 0x40, 0x00, 0x00 }, // , A7C9 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0xC4, 0xA2, 0x4A, 0x24, 0xA2, 0x00, 0x00, 0x00 }, // , A7CA + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x5F, 0x3B, 0x14, 0x11, 0x40, 0x00, 0x00 }, // , A7CB + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x68, 0xA5, 0x4A, 0x54, 0xA5, 0x5F, 0x55, 0x15, 0x51, 0x00, 0x00, 0x00 }, // , A7CC + { 0x00, 0x02, 0x04, 0x20, 0x42, 0x04, 0x24, 0xA2, 0x8A, 0x30, 0xA3, 0x1F, 0x29, 0x12, 0x51, 0x00, 0x00, 0x00 }, // , A7CD + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x71, 0x44, 0x14, 0x40, 0x00, 0x00 }, // , A7CE + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x49, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7CF + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x15, 0x51, 0x55, 0x29, 0x52, 0x8A, 0x34, 0xA4, 0x0A, 0x40, 0x00, 0x00 }, // , A7D0 + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x69, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x54, 0xA5, 0x4A, 0x00, 0x00, 0x00 }, // , A7D1 + { 0x00, 0x04, 0x2A, 0x42, 0xA4, 0x2A, 0x4A, 0xA5, 0x2A, 0x62, 0xA6, 0x14, 0x51, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7D2 + { 0x00, 0x04, 0x55, 0x45, 0x56, 0xD5, 0x6D, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x44, 0xA4, 0x4A, 0x00, 0x00, 0x00 }, // , A7D3 + { 0x00, 0x02, 0x40, 0x24, 0x02, 0x40, 0x25, 0xE3, 0xC2, 0x24, 0x42, 0x48, 0x25, 0x02, 0x5E, 0x00, 0x00, 0x00 }, // , A7D4 + { 0x00, 0x04, 0x50, 0x45, 0x04, 0x50, 0x55, 0x75, 0x71, 0x65, 0x26, 0x52, 0x55, 0x45, 0x57, 0x00, 0x00, 0x00 }, // , A7D5 + { 0x00, 0x04, 0x48, 0x44, 0x86, 0xC8, 0x6C, 0xF5, 0x79, 0x54, 0xA5, 0x4A, 0x54, 0xC4, 0x4F, 0x00, 0x00, 0x00 }, // , A7D6 + { 0x00, 0x03, 0x28, 0x4A, 0x84, 0xA8, 0x42, 0xF5, 0xB9, 0x4A, 0xA4, 0xAA, 0x4A, 0xC3, 0xAF, 0x00, 0x00, 0x00 }, // , A7D7 + { 0x00, 0x07, 0xE8, 0x12, 0x81, 0x28, 0x12, 0xF1, 0x39, 0x12, 0xA1, 0x2A, 0x12, 0xC1, 0x2F, 0x00, 0x00, 0x00 }, // , A7D8 + { 0x00, 0x00, 0x00, 0x07, 0x00, 0x88, 0x10, 0x41, 0x04, 0x10, 0x40, 0x88, 0x15, 0x41, 0xDC, 0x00, 0x00, 0x00 }, // , A7D9 + { 0x00, 0x04, 0x1C, 0x42, 0x24, 0x22, 0x4A, 0x25, 0x22, 0x61, 0x46, 0x14, 0x51, 0x44, 0xB6, 0x00, 0x00, 0x00 }, // , A7DA + { 0x00, 0x04, 0x4E, 0x45, 0x16, 0xD1, 0x6D, 0x15, 0x51, 0x54, 0xA5, 0x4A, 0x44, 0xA4, 0x5B, 0x00, 0x00, 0x00 }, // , A7DB + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x72, 0x04, 0x20, 0x40, 0x00, 0x00 }, // , A7DC + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x4A, 0x04, 0xA0, 0x00, 0x00, 0x00 }, // , A7DD + { 0x00, 0x00, 0x0F, 0x00, 0x80, 0x08, 0x12, 0x81, 0x2E, 0x24, 0x82, 0x48, 0x3A, 0x84, 0x08, 0x40, 0x00, 0x00 }, // , A7DE + { 0x00, 0x00, 0x02, 0x00, 0x20, 0x02, 0x6B, 0x25, 0x4A, 0x54, 0xA5, 0x4A, 0x54, 0xA5, 0x72, 0x00, 0x00, 0x00 }, // , A7DF + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x31, 0xC4, 0xA4, 0x42, 0x44, 0x24, 0x4A, 0x43, 0x1C, 0x00, 0x00, 0x00 }, // , A7E0 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x56, 0x36, 0x95, 0x47, 0x54, 0x95, 0x49, 0x54, 0x6B, 0x00, 0x00, 0x00 }, // , A7E1 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x54, 0x4E, 0xC0, 0x07, 0x07, 0x87, 0x86, 0x00, 0xC0, 0x02, 0x00, 0xC0, 0x00 }, // , A7E2 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x57, 0x4E, 0xC0, 0x32, 0x1C, 0x16, 0x1A, 0x03, 0x30, 0x08, 0x03, 0x00, 0x00 }, // , A7E3 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xA2, 0x2C, 0x18, 0x80, 0x48, 0x22, 0x81, 0xC8, 0x00, 0x00, 0x00 }, // , A7E4 + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xC2, 0x52, 0x38, 0xE2, 0x12, 0x21, 0x22, 0x0D, 0x00, 0x00, 0x00 }, // , A7E5 + { 0x00, 0x04, 0x60, 0x45, 0x04, 0x50, 0x55, 0xC5, 0x52, 0x66, 0x66, 0x4A, 0x54, 0xA5, 0x47, 0x00, 0x00, 0x00 }, // , A7E6 + { 0x00, 0x04, 0x58, 0x45, 0x46, 0xD4, 0x6D, 0x65, 0x55, 0x55, 0xB5, 0x55, 0x45, 0x54, 0x53, 0x00, 0x00, 0x00 }, // , A7E7 + { 0x00, 0x03, 0x30, 0x4A, 0x84, 0xA8, 0x42, 0xE5, 0xA9, 0x4B, 0x34, 0xA5, 0x4A, 0x53, 0xA3, 0x00, 0x00, 0x00 }, // , A7E8 + { 0x00, 0x05, 0x50, 0x55, 0x05, 0x50, 0x55, 0xC5, 0x52, 0x55, 0x22, 0x92, 0x29, 0x22, 0x9C, 0x00, 0x00, 0x00 }, // , A7E9 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x26, 0x82, 0x54, 0x25, 0x42, 0x54, 0x25, 0x42, 0x54, 0x00, 0x00, 0x00 }, // , A7EA + { 0x00, 0x01, 0x00, 0x10, 0x01, 0x00, 0x14, 0x41, 0x28, 0x11, 0x01, 0x10, 0x12, 0x81, 0x44, 0x00, 0x00, 0x00 }, // , A7EB + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xE3, 0x92, 0x25, 0x22, 0x52, 0x24, 0xE3, 0x82, 0x00, 0x20, 0x00 }, // , A7EC + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x42, 0x25, 0xA2, 0x49, 0x44, 0x94, 0x48, 0x83, 0x08, 0x03, 0x00, 0x00 }, // , A7ED + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x22, 0x21, 0x22, 0x09, 0x44, 0x94, 0x48, 0x83, 0x08, 0x00, 0x00, 0x00 }, // , A7EE + { 0x24, 0x05, 0x60, 0x56, 0x04, 0xA0, 0x4A, 0xB5, 0xAD, 0x2B, 0x51, 0x35, 0x12, 0xB1, 0x2D, 0x00, 0x20, 0x00 } // , A7EF +}; + +extern const Uint16 EngFontTable[96][9]; +extern const Uint16 EtcFontTable[81][18]; +#endif + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ new file mode 100644 index 0000000..ff7633e --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 b/.staticdata/.previous/20260113_090505/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 new file mode 100644 index 0000000..dcd417b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 @@ -0,0 +1,864 @@ +#include "main.h" + +void CInitAlarmOperValue(void); +void CKeyMainPowerProcess(void); +void CKeyArrowUpProcess(void); +void CKeyArrowDownProcess(void); +void CKeyEnterProcess(void); +void CKeyMenuProcess(void); +void CKeyEngineStartStopProcess(void); +void CKeyEmergencyProcess(void); +void CInitAdcStructure(void); +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh); +Uint32 CGetKey(void); +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void MoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; +CAlarmOperValue AlarmOperValue[IDX_FAULT_MAX]; +CFaultBitValue FaultBitValue; +CKeyOperValue KeyOperValue; + +static const CKeyHandler KeyTable[IDX_KEY_MAX] = +{ + { IDX_KEY_MAIN_POWER, CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, CKeyArrowDownProcess }, + { IDX_KEY_ENTER, CKeyEnterProcess }, + { IDX_KEY_MENU, CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, CKeyEmergencyProcess } +}; + +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN2_I]; + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0f); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0f); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0f); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0f); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0f); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0f); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0f); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + Uint64 ullFaultValue = ((Uint64)FaultBitValue.ulTotal & 0x3FFFFUL) | (((Uint64)Rx210.GcuFault.uiTotal & 0xFFFFU) << 19UL) | (((Uint64)Rx310.EcuFault.uiTotal & 0x3FU) << 35UL); + Uint32 ulWarningValue = ((Uint32)Rx210.GcuWarning.uiTotal & 0x7U) | (((Uint32)Rx310.EcuWarning.uiTotal & 0xFU) << 4U); + Uint16 i; + + if (OledOperValue.uiAlarmPopCheck == 0U) + { + if (ulWarningValue > 0U) + { + for (i = 0U; i < 16U; i++) + { + if ((ulWarningValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = ((i / 9U) + OLED_PAGE_WARNING1); + break; + } + } + } + if (ullFaultValue > 0U) + { + for (i = 0U; i < 64U; i++) + { + if ((ullFaultValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = (((i % 64U) / 8U) + OLED_PAGE_FAULT1); + break; + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0U; + + if (CGetApuOperIndex() == APU_OPER_IDX_EMERGENCY) + { + // Ÿ ƿ ߻ Ʈ Ŭ Ѵ. + GeneralOperValue.Conection.CarComputer = (FaultBitValue.bit.CarCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (FaultBitValue.bit.GcuCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (FaultBitValue.bit.EcuCommTimeOut == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + if (GeneralOperValue.uiAlarmReset == 1U) + { + GeneralOperValue.uiAlarmReset = 0U; + + CInitAlarmOperValue(); + } + } + else + { + if (GeneralOperValue.uiApuState > APU_OPER_IDX_EMERGENCY) + { + // Comm Timeout Checks + FaultBitValue.bit.CarCommTimeout = CAlarmCheck(IDX_FAULT_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GcuCommTimeout = CAlarmCheck(IDX_FAULT_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.EcuCommTimeOut = CAlarmCheck(IDX_FAULT_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK); + + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + // RPM Ǿ Ѵ. + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = ABS(iDiffRpm); + FaultBitValue.bit.RpmError = CAlarmCheck(IDX_FAULT_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK); + } + FaultBitValue.bit.EngineHeatOverCurrent = CAlarmCheck(IDX_FAULT_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GlowPlugOverCurrent = CAlarmCheck(IDX_FAULT_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.SolenoidOverCurrent = CAlarmCheck(IDX_FAULT_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.FuelPumpOverCurrent = CAlarmCheck(IDX_FAULT_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.CoolantPumpOverCurrent = CAlarmCheck(IDX_FAULT_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan1OverCurrent = CAlarmCheck(IDX_FAULT_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan2OverCurrent = CAlarmCheck(IDX_FAULT_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK); + + // Fuse ȣ ġ ϴ CS ON ¿ ۵ϹǷ CS HI , Fuse ȣ HI ܼ + if (CGetApuOperIndex() > APU_OPER_IDX_STANDBY) + { + FaultBitValue.bit.EngineHeatOpen = CheckOpenFault(GPIO_ENGINE_HEATER_CS_READ(), GPIO_ENGINE_HEATER_FUSE()); + FaultBitValue.bit.GlowPlugOpen = CheckOpenFault(GPIO_GLOW_PLUG_CS_READ(), GPIO_GLOW_PLUG_FUSE()); + FaultBitValue.bit.SolenoidOpen = CheckOpenFault(GPIO_SOLENOID_CS_READ(), GPIO_SOLENOID_FUSE()); + FaultBitValue.bit.FuelPumpOpen = CheckOpenFault(GPIO_FUEL_PUMP_CS_READ(), GPIO_FUEL_PUMP_FUSE()); + FaultBitValue.bit.CoolantPumpOpen = CheckOpenFault(GPIO_COOLANT_PUMP_CS_READ(), GPIO_COOLANT_PUMP_FUSE()); + FaultBitValue.bit.Fan1Open = CheckOpenFault(GPIO_FAN1_CS_READ(), GPIO_FAN1_FUSE()); + FaultBitValue.bit.Fan2Open = CheckOpenFault(GPIO_FAN2_CS_READ(), GPIO_FAN2_FUSE()); + } + } + } +} + +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh) +{ + // ȣ 1(High) 1(Fault) ȯ + return ((isCsHigh == 1U) && (isFuseHigh == 1U)) ? 1U : 0U; +} + +void CInitAlarmOperValue(void) +{ + int16 i; + + for (i = 0; i < IDX_FAULT_MAX; i++) + { + (void) memset(&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void) memset(&FaultBitValue, 0, sizeof(CFaultBitValue)); + (void) memset(&CommCheck, 0, sizeof(CCommCheck)); + + // ü/GCU/ECU ȣ ܼ ٸ Լ ó + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[IDX_FAULT_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_RPM_ERR].fCheckLimit = 300.0f; // Value + AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_SOLENOID_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN1_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN2_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime = 10U; // Value + +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_I + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_I + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_I + + AdcRegs.ADCMAXCONV.all = IDX_ADC_MAX; // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + CInitAlarmOperValue(); +} + +void CInitAdcStructure(void) +{ + (void) memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + (void) memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_I.fGain = 0.005637f; + Adc_GlowPlug_I.fGain = 0.005637f; + Adc_Solenoid_I.fGain = 0.005637f; + Adc_FuelPump_I.fGain = 0.005637f; + Adc_CoolantPump_I.fGain = 0.005637f; + Adc_Fan1_I.fGain = 0.005637f; + Adc_Fan2_I.fGain = 0.005637f; + + Adc_EngineHeater_I.fOffset = -2.333f; + Adc_GlowPlug_I.fOffset = -2.333f; + Adc_Solenoid_I.fOffset = -2.333f; + Adc_FuelPump_I.fOffset = -2.333f; + Adc_CoolantPump_I.fOffset = -2.333f; + Adc_Fan1_I.fOffset = -2.333f; + Adc_Fan2_I.fOffset = -2.333f; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ +#if 1 + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 100) + { + AdcBuff->uiSamplingCount = 0; + AdcBuff->fSampledSum /= 100; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledSum) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); + AdcBuff->fSampledSum = 0.0f; + } +#else + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledValue) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); +#endif +} + +Uint32 CGetKey(void) +{ + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + Uint16 ucKeyGpioList[7] = { 67, 39, 31, 30, 29, 66, 64}; + + for (i = 0; i < IDX_KEY_MAX; i++) + { + ucDiv = ucKeyGpioList[i] / 32; + ucMod = ucKeyGpioList[i] % 32; + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + static Uint32 ulLongKeyCnt = 0UL; // Ű īƮ + static Uint16 uiLongKeyProcessed = 0U; // Ű ó Ϸ ÷ (ߺ ) + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~KEY_POWER_MASK; // Ű Ű ϵ, Ű(Bit 0) ȭ (& ~KEY_POWER_MASK) + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // ä͸ + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + // Ű Ű POST ܰ谡 Ѿ Ѵ. + if ((KeyOperValue.uiKeyWaitCount == 0U) && (CGetApuOperIndex() > APU_OPER_IDX_POST)) + { + ulPrevKey = (ulPrevKey & KEY_POWER_MASK) | (ulReadKey & ~KEY_POWER_MASK); // ulPrevKey Ʈ ϰ Ʈ + CKeyCheck(ulChangeKey, ulReadKey); // Ϲ Ű + } + } + } + else + { + // ȭ ä͸ ʱȭ (Ϲ Ű) + // , ִ ulPrevKey ʿ + if ((KeyOperValue.uiKeyWait) != 0U && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // Bit 0 ִ Ȯ (1 = ) + if ((ulReadKey & KEY_POWER_MASK) == KEY_POWER_MASK) + { + // ̹ ó ° ƴ϶ īƮ + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 1(1000ms) + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + CKeyCheck(KEY_POWER_MASK, ulReadKey); // Ű (CKeyCheck Ű Ʈ ) + uiLongKeyProcessed = 1U; // ٽ ʵ ÷ + ulLongKeyCnt = LONG_KEY_TIME; // īƮ ÷ο + } + } + } + else + { + // Ű ʱȭ + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey Bit 0 µ 0 ȭ ( 񱳸 ) + ulPrevKey &= ~KEY_POWER_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + Uint16 i; + + for (i = 0U; i < IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +void CKeyArrowUpProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + } +} + +void CKeyArrowDownProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = OLED_PAGE_APU2; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_4) + { + // Bottom of Menu 1 -> Go to Menu 2 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + MoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CChangePasswordDigit(Uint16 direction) +{ + // Ensure the focus digit is within valid range to avoid out-of-bounds access + if (OledOperValue.uiFocusDigit <= OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void MoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + maxLines - 1U) % maxLines; + } + else // DIR_DOWN + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + 1U) % maxLines; + } +} + +void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case OLED_PAGE_MENU1: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_MENU_APU: + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + break; + } + case OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = OLED_PAGE_TEMP; + break; + } + case OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = OLED_PAGE_WARNING1; + } + break; + } + } + break; + } + case OLED_PAGE_MENU2: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = OLED_PAGE_FAULT1; + break; + } + case OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_RESET_ALARM; + break; + } + case OLED_LINE_FOCUS_3: // Maintenence + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + break; + } + default: + break; + } + break; + } + case OLED_PAGE_PASSWORD: + { + if (OledOperValue.uiFocusDigit < OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + // Check password + const Uint16 uiPassword[4] = DEBUG_MENU_PASSWORD; + + if (memcmp(GeneralOperValue.uiPassword, uiPassword, sizeof(uiPassword)) == 0U) + { + GeneralOperValue.uiMaintenence = 1U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + } + } + break; + } + case OLED_PAGE_RESET_ALARM: + { + // Selected "YES" + if (OledOperValue.uiResetAnswer == 1U) + { + if (CApuSystemAlarmCheck() > 0) + { + GeneralOperValue.uiAlarmReset = 1U; + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + break; + } + case OLED_PAGE_MAINTENENCE: + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenence.ManualCranking = GeneralOperValue.Maintenence.ManualCranking ^ 1U; // Toggle + } + else if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenence.LampTest = GeneralOperValue.Maintenence.LampTest ^ 1U; // Toggle + } + else + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenence.KeyTest = GeneralOperValue.Maintenence.KeyTest ^ 1U; // Toggle + OledOperValue.uiPageNum = OLED_PAGE_KEY_TEST; + } + } + break; + } + default: + { + // Handle Fault/Warning page return logic + if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + if (OledOperValue.uiAlarmPopCheck == 1U) + { + OledOperValue.uiAlreadyAlarm = 1U; + OledOperValue.uiPageNum = OledOperValue.uiPrevAlarmPage; + } + } + break; + } + } +} + +void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_MAINTENENCE)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + GeneralOperValue.uiMaintenence = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + } +} + +void CKeyMainPowerProcess(void) +{ + if (CGetApuOperIndex() <= APU_OPER_IDX_STANDBY) + { + // APU ¿ ġ Է + OledOperValue.uiPageNum = OLED_PAGE_SHUTDOWN; + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, TIME_1SEC) == TIME_OVER) + { + GPIO_POWER_HOLD(0); + } + } +} + +void CKeyEngineStartStopProcess(void) +{ + KeyOperValue.KeyList.bit.EngineStartStop = KeyOperValue.KeyList.bit.EngineStartStop ^ 1U; // Toggle +} + +void CKeyEmergencyProcess(void) +{ + // ġ Ŭ ϱ ؼ APU ýۿ ˶ Ѵ. + KeyOperValue.KeyList.bit.Emergency = KeyOperValue.KeyList.bit.Emergency ^ 1U; // Toggle +} diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ new file mode 100644 index 0000000..9ccf069 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ new file mode 100644 index 0000000..a4564ad --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ new file mode 100644 index 0000000..1461873 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/f9a156ec434632a46725fb267c577743_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/f9a156ec434632a46725fb267c577743_ new file mode 100644 index 0000000..e19cb54 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/f9a156ec434632a46725fb267c577743_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef b/.staticdata/.previous/20260113_090505/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef new file mode 100644 index 0000000..71b6378 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef @@ -0,0 +1,545 @@ +#include "main.h" + +CPowerOnCheckValue PowerOnCheckValue; +CGeneralOperValue GeneralOperValue; + +CSoftTimer SoftTimer[TIMER_MAX]; +CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +Uint32 ulSoftClock; + +void CInitSystem(void); +void CInitGeneralOperValue(void); +void CInitGpio(void); +void CSystemConfigure(void); +void CMappingInterrupt(void); +void CProcessSoftTimer(void); +Uint16 CPowerOnCheck(void); +void CSoftTimerWorkProcess(void); +Uint16 CIsStatusSoftTimer(Uint16 ucTimerIndex); +void CReloadSoftTimer(Uint16 ucTimerIndex); +void CInitSoftTimers(void); +void CInitSoftTimer(void); +void CConfigSoftTimer(Uint16 ucTimerIndex, Uint32 ulDelay); +void CStartSoftTimer(Uint16 ucTimerIndex); +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +Uint32 CGetSoftClock(void); +void CSOftWaitCountCancel(Uint16 Index); + +int main(void) +{ + CSetApuOperIndex(APU_OPER_IDX_BOOT); + + CInitSystem(); + + CInitOled(); + + CSetApuOperIndex(APU_OPER_IDX_INITIAL); + + for ( ; ; ) + { + CSoftTimerWorkProcess(); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == TIME_OVER) + { + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_POST); // Adc Ϸ POST + } + } + } + else if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + if (CPowerOnCheck() == 0U) + { + AdcOperValue.uiOffsetAdjustStart = 1U; // offset . + + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + } + } + else + { + if (GeneralOperValue.uiMaintenence == 0U) + { + // 尡 ־ . + //CApuOperProcedure(); + + CLedControlProcedure(); + + GPIO_ENGINE_HEATER_CS(GPIO_USER_MODE_1()); + GPIO_GLOW_PLUG_CS(GPIO_USER_MODE_1()); + GPIO_SOLENOID_CS(GPIO_USER_MODE_1()); + GPIO_FUEL_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_COOLANT_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_FAN1_CS(GPIO_USER_MODE_1()); + GPIO_FAN2_CS(GPIO_USER_MODE_1()); + } + else + { + CDebugModeProcedure(); + } + } + } +} + +void CSoftTimerWorkProcess(void) +{ + static Uint16 RefeshDelay = 0U; + + if (CIsStatusSoftTimer(TIMER_01MS) == SOFTTIMER_TIME_OVER) // Excute Per 1msec + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > APU_OPER_IDX_POST) // ADC Ϸ + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + if (GeneralOperValue.Maintenence.KeyTest == 0U) + { + // (:Ű׽Ʈ) ƴϸ Ű Է . + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (CIsStatusSoftTimer(TIMER_10MS) == SOFTTIMER_TIME_OVER) // Excute Per 10msec + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataA(); + CSendECanDataB(); + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) + { + if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + CDisplayPostFail(); + } + else + { + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + } + + if (CIsStatusSoftTimer(TIMER_100MS) == SOFTTIMER_TIME_OVER) // Excute Per 100msec + { + CReloadSoftTimer(TIMER_100MS); + + // ǻ ѹ̶ Ǿ ŸӾƿ üũ + if (CApuSystemAlarmCheck() == 0U) + { + // ߻ ŸӾƿ üũ ʴ´. + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer < COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : 0U; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : 0U; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : 0U; + } + } + if (CIsStatusSoftTimer(TIMER_1SEC) == SOFTTIMER_TIME_OVER) // Excute Per 1s + { + CReloadSoftTimer(TIMER_1SEC); + + if (OledOperValue.uiAlreadyAlarm == 1U) // ˶ ߻ 1е ٽ ˾ ϱ . + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_POPUP, (TIME_1SEC * 60UL)) == TIME_OVER) + { + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + else + { + CSOftWaitCountCancel(SOFTTIMER_WAIT_POPUP); + } + } +} + +void CSOftWaitCountCancel(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0f, 100.0f); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0U; // GPIO_COOLING_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U; // GPIO_FUEL_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U; // GPIO_COOLING_FAN1_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U; // GPIO_COOLING_FAN2_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U; // GPIO_GLOW_PLUG_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO6 = 0U; // GPIO_ENGINE_HEATER_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U; // GPIO_STOP_SOLENOID_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U; // GPIO_ECU_ON_OFF + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GPIO_POWER_HOLD(1); + + GPIO_CPU_LED_COM_FAULT_N(1); + GPIO_CPU_LED_COM_RUN_N(1); + GPIO_CPU_LED_COM_STA_N(1); + + EDIS; +} + +void CActiveChipSelect(Uint16 Active) +{ + if (Active == 0U) + { + // Ȳ CS OFFѴ. (0 - CS OFF, 1 - CS ON) + GPIO_ENGINE_HEATER_CS(0); + GPIO_GLOW_PLUG_CS(0); + GPIO_SOLENOID_CS(0); + GPIO_FUEL_PUMP_CS(0); + + GPIO_COOLANT_PUMP_CS(0); + GPIO_FAN1_CS(0); + GPIO_FAN2_CS(0); + } + else + { + //  ¿ EcuSignal ¸ Ȯϰ , ۷ο÷, ̵ַ, Ѵ. + // 0 - CS OFF, 1 - CS ON + GPIO_ENGINE_HEATER_CS(GPIO_ENGINE_HEATER()); + GPIO_GLOW_PLUG_CS(GPIO_GLOW_PLUG()); + GPIO_SOLENOID_CS(GPIO_SOLENOID()); + GPIO_FUEL_PUMP_CS(GPIO_FUEL_PUMP()); + + GPIO_COOLANT_PUMP_CS(1); + GPIO_FAN1_CS(1); + GPIO_FAN2_CS(1); + } +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +void CInitGeneralOperValue(void) +{ + (void) memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + (void) memset(&PowerOnCheckValue, 0x1FF, sizeof(CPowerOnCheckValue)); // Set All bit 1 + + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] = 0; +} + +void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = M_INT1 | M_INT9; + + EDIS; +} + +void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + CConfigSoftTimer(TIMER_1SEC, TIME_1SEC); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); + CStartSoftTimer(TIMER_1SEC); +} + +void CStartSoftTimer(Uint16 ucTimerIndex) +{ + if (SoftTimer[ucTimerIndex].iTimer != -1) + { + SoftTimer[ucTimerIndex].iStart = 1; + } +} + +void CInitSoftTimer(void) +{ + Uint16 i; + + (void) memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void) memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +Uint16 CPowerOnCheck(void) +{ + // Ȯ CAN ͷƮ ߻ , üũ + Uint16 retValue = (*(Uint16*)&PowerOnCheckValue) & 0x7FU; + + PowerOnCheckValue.EngineHeaterSensor = ((Adc_EngineHeater_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.GlowPlugSensor = ((Adc_GlowPlug_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.SolenoidSensor = ((Adc_Solenoid_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.FuelPumpSensor = ((Adc_FuelPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.CoolantPumpSensor = ((Adc_CoolantPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan1Sensor = ((Adc_Fan1_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan2Sensor = ((Adc_Fan2_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + + return retValue; // '0' +} diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ new file mode 100644 index 0000000..0df8e48 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ new file mode 100644 index 0000000..712b04b --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 b/.staticdata/.previous/20260113_090505/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 new file mode 100644 index 0000000..376775e --- /dev/null +++ b/.staticdata/.previous/20260113_090505/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 @@ -0,0 +1,220 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +typedef signed char int8; +typedef unsigned char Uint8; + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "DSP2833x_EPwm_defines.h" +#include "DSP2833x_I2c_defines.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (!GpioDataRegs.GPBDAT.bit.GPIO39) +#define GPIO_KEY_DOWN() (!GpioDataRegs.GPADAT.bit.GPIO31) +#define GPIO_KEY_ENTER() (!GpioDataRegs.GPADAT.bit.GPIO30) +#define GPIO_KEY_MENU() (!GpioDataRegs.GPADAT.bit.GPIO29) +#define GPIO_KEY_POWER() (!GpioDataRegs.GPCDAT.bit.GPIO67) +#define GPIO_KEY_START() (!GpioDataRegs.GPCDAT.bit.GPIO66) +#define GPIO_KEY_EMERGENCY() (!GpioDataRegs.GPCDAT.bit.GPIO64) + +// CS ȰǾ FUSE high ߻ (ips Ĩ Ǵ fuse) +#define GPIO_ENGINE_HEATER_FUSE() (GpioDataRegs.GPADAT.bit.GPIO6) +#define GPIO_GLOW_PLUG_FUSE() (GpioDataRegs.GPADAT.bit.GPIO5) +#define GPIO_SOLENOID_FUSE() (GpioDataRegs.GPADAT.bit.GPIO7) +#define GPIO_FUEL_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO2) +#define GPIO_COOLANT_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO1) +#define GPIO_FAN1_FUSE() (GpioDataRegs.GPADAT.bit.GPIO3) +#define GPIO_FAN2_FUSE() (GpioDataRegs.GPADAT.bit.GPIO4) + +#define GPIO_ECU_ON_OFF() (GpioDataRegs.GPADAT.bit.GPIO8) +#define GPIO_FUEL_PUMP() (GpioDataRegs.GPADAT.bit.GPIO9) +#define GPIO_GLOW_PLUG() (GpioDataRegs.GPADAT.bit.GPIO10) +#define GPIO_SOLENOID() (GpioDataRegs.GPADAT.bit.GPIO11) +#define GPIO_ENGINE_HEATER() (GpioDataRegs.GPADAT.bit.GPIO24) +#define GPIO_USER_MODE_1() (!GpioDataRegs.GPCDAT.bit.GPIO81) +#define GPIO_USER_MODE_2() (!GpioDataRegs.GPCDAT.bit.GPIO82) +#define GPIO_USER_MODE_3() (!GpioDataRegs.GPCDAT.bit.GPIO83) + +#define GPIO_ENGINE_HEATER_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO49) +#define GPIO_GLOW_PLUG_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO27) +#define GPIO_SOLENOID_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO48) +#define GPIO_FUEL_PUMP_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO26) +#define GPIO_COOLANT_PUMP_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO52) +#define GPIO_FAN1_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO50) +#define GPIO_FAN2_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO51) + +// ChipSelect Port +#define GPIO_ENGINE_HEATER_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO49 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1)); +#define GPIO_GLOW_PLUG_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO27 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO27 = 1)); +#define GPIO_SOLENOID_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO48 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1)); +#define GPIO_FUEL_PUMP_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO26 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO26 = 1)); +#define GPIO_COOLANT_PUMP_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO52 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1)); +#define GPIO_FAN1_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO50 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1)); +#define GPIO_FAN2_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO51 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1)); + +// Pannel LED Port +#define GPIO_CPU_LED_STOP(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO12 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO12 = 1)); +#define GPIO_CPU_LED_FAULT(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO14 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO14 = 1)); +#define GPIO_CPU_LED_OPERATION(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO13 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO13 = 1)); + +#define GPIO_OLED_RESET(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO37 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1)); + +#define GPIO_FAULT_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO55 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1)); +#define GPIO_EMERGENCY_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO56 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1)); +#define GPIO_STOP_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO57 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1)); +#define GPIO_START_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO58 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1)); + +#define GPIO_POWER_HOLD(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO65 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1)); +#define GPIO_CPU_LED_COM_FAULT_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO68 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1)); +#define GPIO_CPU_LED_COM_RUN_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO69 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1)); +#define GPIO_CPU_LED_COM_STA_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO70 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1)); + +/* Comment Description + * [!] : + * [?] : ʿ + * [*] : Ǻ + */ + +/* Firmware (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // ȣȯ ʴ ȭ , ȭ +#define FIRMWARE_VERSION_MINOR (0) // ȣȯ Ǹ鼭 ο , ǰų +#define FIRMWARE_VERSION_PATCH (5) // ȣȯ Ǹ鼭 , Ȱ ˾ Ҽ + +/* Version History + * [0.0.1] : DCU Ʈ + * [0.0.2] : DCU ߿ ž + * [0.0.3] : OLED XINTF(BUS) ̺ + * [0.0.4] : OLED ǥ ȭ + * [0.0.5] : CAN-B Ȯ + */ + +#define DEBUG_MENU_PASSWORD {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10U) +#define TIME_10MS (100U) +#define TIME_20MS (200U) +#define TIME_50MS (500U) +#define TIME_100MS (1000U) +#define TIME_500MS (5000U) +#define TIME_1SEC (10000U) + +// 0A ذ 450(0.33V), +/- 150 +#define SENSOR_OFFSET_REF 450 +#define SENSOR_TOLERANCE 150 +#define SENSOR_MIN_LIMIT (SENSOR_OFFSET_REF - SENSOR_TOLERANCE) // 300 +#define SENSOR_MAX_LIMIT (SENSOR_OFFSET_REF + SENSOR_TOLERANCE) // 600 + +#define TIME_OVER (1U) + +#define ABS(x) ((x) < 0 ? -(x) : (x)) + +enum +{ + TIMER_01MS = 0, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0, + SOFTTIMER_WAIT_POPUP, + SOFTTIMER_WAIT_APU_STOP, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef struct ClassPowerOnCheckValue +{ + Uint16 EngineHeaterSensor : 1; + Uint16 GlowPlugSensor : 1; + Uint16 SolenoidSensor : 1; + Uint16 FuelPumpSensor : 1; + Uint16 CoolantPumpSensor : 1; + Uint16 Fan1Sensor : 1; + Uint16 Fan2Sensor : 1; +} CPowerOnCheckValue; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiPassword[4]; + Uint16 uiAlarmOccured; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenence; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd : 4; + Uint16 rsvd_padding : 4; + } GcuCommand; + struct + { + Uint16 EngineStart : 1; + Uint16 EngineStop : 1; + Uint16 rsvd : 2; + Uint16 RpmSetPoint : 2; + Uint16 Override : 1; + Uint16 Emergency : 1; + } EcuCommand; + struct + { + Uint16 CarComputer : 1; + Uint16 Gcu : 1; + Uint16 Ecu : 1; + } Conection; + struct + { + Uint16 ManualCranking : 1; + Uint16 LampTest : 1; + Uint16 KeyTest : 1; + } Maintenence; +} CGeneralOperValue; + +Uint16 CSoftWaitCountProcedure(Uint16 ucIndex, Uint32 ulWaitTime); +void CActiveChipSelect(Uint16 Active); + +extern CGeneralOperValue GeneralOperValue; +extern CPowerOnCheckValue PowerOnCheckValue; + +#endif /* SOURCE_MAIN_H_ */ diff --git a/.staticdata/.previous/20260113_090505/K2DCU/fs/fs_hash_map.json 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설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"0\",\n\n \"last_capture_time\": \"2026-01-12T02:26:25.095Z\"\n\n}" +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/artifacts.zip b/.staticdata/.previous/20260113_090505/artifacts.zip new file mode 100644 index 0000000..4d258da Binary files /dev/null and b/.staticdata/.previous/20260113_090505/artifacts.zip differ diff --git a/.staticdata/.previous/20260113_090505/cstrace.json b/.staticdata/.previous/20260113_090505/cstrace.json new file mode 100644 index 0000000..8f88c09 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005\\Source" + ] + } +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/error.json b/.staticdata/.previous/20260113_090505/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/.staticdata/.previous/20260113_090505/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/exclude_project.json b/.staticdata/.previous/20260113_090505/exclude_project.json new file mode 100644 index 0000000..1f5e5dd --- /dev/null +++ b/.staticdata/.previous/20260113_090505/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "K2APU_DCU", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090505/preinclude/gnu_preinclude.h b/.staticdata/.previous/20260113_090505/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_c.h b/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_cpp.h b/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/.staticdata/.previous/20260113_090505/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090633/.hint b/.staticdata/.previous/20260113_090633/.hint new file mode 100644 index 0000000..f255c84 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/.spec b/.staticdata/.previous/20260113_090633/.spec new file mode 100644 index 0000000..5ca53c3 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v005\.spec \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090633/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090633/K2DCU/config/.inf b/.staticdata/.previous/20260113_090633/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/K2DCU/config/ci.ini b/.staticdata/.previous/20260113_090633/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.previous/20260113_090633/K2DCU/config/csa.exe b/.staticdata/.previous/20260113_090633/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.previous/20260113_090633/K2DCU/config/csa.exe differ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/config/psionic.ini b/.staticdata/.previous/20260113_090633/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 b/.staticdata/.previous/20260113_090633/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 new file mode 100644 index 0000000..476e6ce --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 @@ -0,0 +1,180 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define PI2 (6.283185f) +#define ADC_FREQ (10000.0f) // 10kHz = 0.0001sec +#define ADC_LPF_COFF_TEMP (0.2f) +#define ADC_LPF_GAIN_TEMP (0.00012566f) //(PI2 * ADC_LPF_COFF_TEMP * (1.0f / ADC_FREQ)) +#define ADC_LPF_COFF (30.0f) +#define ADC_LPF_GAIN (0.01884955f) //(PI2 * ADC_LPF_COFF * (1.0f / ADC_FREQ)) + +#define LONG_KEY_TIME (1000UL) +#define KEY_POWER_MASK (0x00000001UL) + +#define COMM_TIME_OUT_COUNT (30U) + +enum +{ + IDX_ADC_ENGINE_HEATER_I = 0U, // 0 + IDX_ADC_GLOW_PLUG_I, // 1 + IDX_ADC_SOLENOID_I, // 2 + IDX_ADC_FUEL_PUMP_I, // 3 + IDX_ADC_COOLANT_PUMP_I, // 4 + IDX_ADC_FAN1_I, // 5 + IDX_ADC_FAN2_I, // 6 + IDX_ADC_MAX +}; + +typedef enum +{ + IDX_FAULT_CAR_COMM = 0U, // 0 + IDX_FAULT_GCU_COMM, // 1 + IDX_FAULT_ECU_COMM, // 2 + IDX_FAULT_RPM_ERR, // 3 + IDX_FAULT_ENGINE_HEAT_OC, // 4 + IDX_FAULT_GLOW_PLUG_OC, // 5 + IDX_FAULT_SOLENOID_OC, // 6 + IDX_FAULT_FUEL_PUMP_OC, // 7 + IDX_FAULT_COOLANT_PUMP_OC, // 8 + IDX_FAULT_FAN1_OC, // 9 + IDX_FAULT_FAN2_OC, // 10 + IDX_FAULT_ENGINE_HEAT_LINE_OPEN, // 11 + IDX_FAULT_GLOW_PLUG_LINE_OPEN, // 12 + IDX_FAULT_SOLENOID_LINE_OPEN, // 13 + IDX_FAULT_FUEL_PUMP_LINE_OPEN, // 14 + IDX_FAULT_COOLANT_PUMP_LINE_OPEN, // 15 + IDX_FAULT_FAN1_LINE_OPEN, // 16 + IDX_FAULT_FAN2_LINE_OPEN, // 17 + IDX_FAULT_MAX +} ALARM_TYPE; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fOffset; + float32 fLpfValue; + float32 fSampledValue; + float32 fGain; + float32 fSampledSum; + float32 fTempAdcOffset; + int16 iAdcValue; + Uint16 uiSamplingCount; +} CAdcCalcValue; + +typedef union ClassFaultBitValue +{ + Uint32 ulTotal; + struct + { + Uint16 CarCommTimeout : 1; + Uint16 GcuCommTimeout : 1; + Uint16 EcuCommTimeOut : 1; + Uint16 RpmError : 1; + Uint16 EngineHeatOverCurrent : 1; + Uint16 GlowPlugOverCurrent : 1; + Uint16 SolenoidOverCurrent : 1; + Uint16 FuelPumpOverCurrent : 1; + + Uint16 CoolantPumpOverCurrent : 1; + Uint16 Fan1OverCurrent : 1; + Uint16 Fan2OverCurrent : 1; + Uint16 EngineHeatOpen : 1; + Uint16 GlowPlugOpen : 1; + Uint16 SolenoidOpen : 1; + Uint16 FuelPumpOpen : 1; + Uint16 CoolantPumpOpen : 1; + + Uint16 Fan1Open : 1; + Uint16 Fan2Open : 1; + Uint16 rsvd_padding1 : 6; + + Uint16 rsvd_padding2 : 8; + } bit; +} CFaultBitValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // Ѱ + Uint16 uiWarning; // 0: , 1: ߻ + Uint16 uiDetectCount; // ī + Uint16 uiReleaseCount; // ī + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, + IDX_KEY_ARR_UP, + IDX_KEY_ARR_DOWN, + IDX_KEY_ENTER, + IDX_KEY_MENU, + IDX_KEY_ENG_START_STOP, + IDX_KEY_EMERGENCY, + IDX_KEY_MAX +} EKeyIndex; + +typedef struct ClassKeyHandler +{ + EKeyIndex eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef union ClassKeyList +{ + Uint16 uiTotal; + struct + { + Uint16 MainPower : 1; + Uint16 ArrowUp : 1; + Uint16 ArrowDown : 1; + Uint16 Enter : 1; + Uint16 Menu : 1; + Uint16 EngineStartStop : 1; + Uint16 Emergency : 1; + } bit; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; +extern CAdcOperValue AdcOperValue; +extern CFaultBitValue FaultBitValue; +extern CKeyOperValue KeyOperValue; + +#endif /* SOURCE_STATE_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ new file mode 100644 index 0000000..9a06c75 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 b/.staticdata/.previous/20260113_090633/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 new file mode 100644 index 0000000..8eb157e --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 @@ -0,0 +1,1443 @@ +#include "main.h" +#include "CFont.h" + +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +volatile Uint16 CommandBus, DataBus; +const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; +int8 cNumBuffer[7] = { 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; +int8 *pNumBuffer = cNumBuffer; + +COledOperValue OledOperValue; + +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenence(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +Uint16 CStrLen(const int8 *s); +void CInitOledModule(void); +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +void CInitProgress(void); +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len); +void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CLcdWrite(Uint16 Data, Uint16 Command); +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CSetPageAddress(Uint16 Address); +void CSetColumnAddress(Uint16 x); +void COledWrite(Uint16 Data, Uint16 Command); +void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(eApuOperIdx idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); + +static const CPageHandler PageTable[OLED_PAGE_MAX] = +{ + { OLED_PAGE_APU1, CPageApu1 }, + { OLED_PAGE_APU2, CPageApu2 }, + { OLED_PAGE_MENU1, CPageMenu1 }, + { OLED_PAGE_MENU2, CPageMenu2 }, + { OLED_PAGE_TEMP, CPageTemp }, + { OLED_PAGE_SENSOR1, CPageSensor1 }, + { OLED_PAGE_SENSOR2, CPageSensor2 }, + { OLED_PAGE_SENSOR3, CPageSensor3 }, + { OLED_PAGE_SENSOR4, CPageSensor4 }, + { OLED_PAGE_WARNING1, CPageWarning1 }, + { OLED_PAGE_WARNING2, CPageWarning2 }, + { OLED_PAGE_FAULT1, CPageFault1 }, + { OLED_PAGE_FAULT2, CPageFault2 }, + { OLED_PAGE_FAULT3, CPageFault3 }, + { OLED_PAGE_FAULT4, CPageFault4 }, + { OLED_PAGE_FAULT5, CPageFault5 }, + { OLED_PAGE_FAULT6, CPageFault6 }, + { OLED_PAGE_RESET_ALARM, CPageAlarmReset }, + { OLED_PAGE_PASSWORD, CPagePassword }, + { OLED_PAGE_MAINTENENCE, CPageMaintenence }, + { OLED_PAGE_KEY_TEST, CPageKeyTest }, + { OLED_PAGE_SHUTDOWN, CPageShutdown } +}; + +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], title, CStrLen(title)); + CDrawStr(10U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0])); + + CDrawTitleBox(CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0]) * 6U); + + if (pageNumStr != NULL) + { + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], pageNumStr, CStrLen(pageNumStr)); + CDrawStr(100U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen(OledOperValue.cStrBuff[OLED_ROW_0])); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY = 0U; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; // Invalid row + } + + CStrncpy(OledOperValue.cStrBuff[row], label, CStrLen(label)); + + if (valueStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], valueStr, CStrLen(valueStr)); + } + + if (unitStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], unitStr, CStrLen(unitStr)); + } + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + CFloatToString(value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + CDecToString((int16)value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + Uint16 drawY = 0U; + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageApu1(void) +{ + const int8 *cTemp = ""; + float32 fTemp; + + // TITLE + CDrawPageTitle("APU Status", "1/2"); + + // LINE 1 + fTemp = Rx220.GcuData.DcVoltage; + CDrawPageLineFloat(OLED_ROW_1, "DC Voltage ", fTemp, " V"); + + // LINE 2 + fTemp = Rx220.GcuData.DcCurrent; + CDrawPageLineFloat(OLED_ROW_2, "DC Current ", fTemp, " A"); + + // LINE 3 + fTemp = (Rx220.GcuData.DcVoltage * Rx220.GcuData.DcCurrent); + CDrawPageLineFloat(OLED_ROW_3, "Power ", fTemp, " kW"); + + // LINE 4 + cTemp = CGetApuStateString((eApuOperIdx)GeneralOperValue.uiApuState); + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_4], "Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[OLED_ROW_4], cTemp); + CStrncat(OledOperValue.cStrBuff[OLED_ROW_4], cTemp, CStrLen(cTemp)); + CDrawStr(0U, OLED_LINE_4, OledOperValue.cStrBuff[OLED_ROW_4], CStrLen(OledOperValue.cStrBuff[OLED_ROW_4])); +} + +static void CPageApu2(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngineActualRpm(); + CDrawPageLineInt(OLED_ROW_1, "ENG.RPM ", (int32)iTemp, " rpm"); + + // LINE 2 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt(OLED_ROW_2, "Coolant ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx320.EcuData.ActualTorque; + CDrawPageLineInt(OLED_ROW_3, "Torque ", (int32)iTemp, " %"); + + // LINE 4 + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, pNumBuffer); + CDrawPageLine(OLED_ROW_4, "ENG.Hour ", pNumBuffer, " Hr"); +} +static void CPageMenu1(void) +{ + // TITLE + CDrawPageTitle("Menu", "1/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "1. APU Status ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "2. Temperature ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "3. Sensor ", NULL, NULL); + + // LINE 4 + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_4, "4. Warning ", NULL, NULL); +} + +static void CPageMenu2(void) +{ + // TITLE + CDrawPageTitle("Menu", "2/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "5. Fault ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "6. Alarm Reset ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "7. Maintenence ", NULL, NULL); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = Rx221.GcuData.PcbTemperature - 40; + CDrawPageLineInt(OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " "); + + // LINE 2 + iTemp = Rx221.GcuData.FetTemperature - 40; + CDrawPageLineInt(OLED_ROW_2, "FET Temp. ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx221.GcuData.GenTemperature1 - 40; + CDrawPageLineInt(OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " "); + + // LINE4 + iTemp = Rx221.GcuData.GenTemperature2 - 40; + CDrawPageLineInt(OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " "); +} +static void CPageSensor1(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "1/4"); + + // LINE 1 + fTemp = (Adc_EngineHeater_I.fLpfValue < 0.0f) ? 0.0f : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "EngineHeater", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_GlowPlug_I.fLpfValue < 0.0f) ? 0.0f : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "GlowPlug ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Solenoid_I.fLpfValue < 0.0f) ? 0.0f : Adc_Solenoid_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Solenoid ", fTemp, " A"); + + // LINE 4 + fTemp = (Adc_FuelPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_FuelPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_4, "FuelPump ", fTemp, " A"); +} + +static void CPageSensor2(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "2/4"); + + // LINE 1 + fTemp = (Adc_CoolantPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "CoolantPump ", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_Fan1_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan1_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "Fan1 ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Fan2_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan2_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Fan2 ", fTemp, " A"); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = Rx321.EcuData.BarometicPressure; + CDrawPageLineInt(OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = Rx321.EcuData.Fan1Speed; + CDrawPageLineInt(OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = Rx321.EcuData.Fan2Speed; + CDrawPageLineInt(OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = Rx321.EcuData.CoolantPumpSpeed; + CDrawPageLineInt(OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = Rx220.GcuData.Rpm; + CDrawPageLineInt(OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "PCBOT:", Rx210.GcuWarning.bit.PcbOverHeat, "FETOT:", Rx210.GcuWarning.bit.FetOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "GEOT1:", Rx210.GcuWarning.bit.GenOverHeat1, "GEOT2:", Rx210.GcuWarning.bit.GenOverHeat2); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "ENGOT:", Rx310.EcuWarning.bit.EngineOverHeat, "L-OIL:", Rx310.EcuWarning.bit.LowOilLevel); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "INTOT:", Rx310.EcuWarning.bit.IntakeOverHeat, "INTLP:", Rx310.EcuWarning.bit.IntakeLoPressure); +} + +static void CPageWarning2(void) +{ + // TITLE + CDrawPageTitle("Warning", "2/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "ENGLT:", Rx310.EcuWarning.bit.EngineLoTemperature, "ENGSF:", Rx310.EcuWarning.bit.EngineSensor); + + // LINE 2 + CDrawPageLineStatus(OLED_ROW_2, "DEFAC:", Rx310.EcuWarning.bit.DefaltValueActive); +} +static void CPageFault1(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "1/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CARCT:", FaultBitValue.bit.CarCommTimeout, "GCUCT:", FaultBitValue.bit.GcuCommTimeout); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ECUCT:", FaultBitValue.bit.EcuCommTimeOut, "RPMER:", FaultBitValue.bit.RpmError); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "EHLOC:", FaultBitValue.bit.EngineHeatOverCurrent, "GPLOC:", FaultBitValue.bit.GlowPlugOverCurrent); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SOLOC:", FaultBitValue.bit.SolenoidOverCurrent, "FPLOC:", FaultBitValue.bit.FuelPumpOverCurrent); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "2/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CPLOC:", FaultBitValue.bit.CoolantPumpOverCurrent, "F1LOC:", FaultBitValue.bit.Fan1OverCurrent); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "F2LOC:", FaultBitValue.bit.Fan2OverCurrent, "EHLLO:", FaultBitValue.bit.EngineHeatOpen); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GPLLO:", FaultBitValue.bit.GlowPlugOpen, "SOLLO:", FaultBitValue.bit.SolenoidOpen); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "FPLLO:", FaultBitValue.bit.FuelPumpOpen, "CPLLO:", FaultBitValue.bit.CoolantPumpOpen); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "3/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "F1LLO:", FaultBitValue.bit.Fan1Open, "F2LLO:", FaultBitValue.bit.Fan2Open); +} + +static void CPageFault4(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "4/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "HTRIP:", Rx210.GcuFault.bit.HwTrip, "HIGBT:", Rx210.GcuFault.bit.HwIgbt); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "HDCOV:", Rx210.GcuFault.bit.HwDc, "GNOCU:", Rx210.GcuFault.bit.GenOverCurrentU); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GNOCV:", Rx210.GcuFault.bit.GenOverCurrentV, "GNOCW:", Rx210.GcuFault.bit.GenOverCurrentW); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SDCOV:", Rx210.GcuFault.bit.DcOverVoltage, "SDCOC:", Rx210.GcuFault.bit.DcOverCurrent); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "5/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "SMOOC:", Rx210.GcuFault.bit.CrankningOverCurrent, "PCBOT:", Rx210.GcuFault.bit.PcbOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "FETOT:", Rx210.GcuFault.bit.FetOverHeat, "GW1OT:", Rx210.GcuFault.bit.GenTempOverHeat1); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GW2OT:", Rx210.GcuFault.bit.GenTempOverHeat2, "GENOS:", Rx210.GcuFault.bit.GenOverSpeed); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "RSICF:", Rx210.GcuFault.bit.ResolverIC, "RSPRT:", Rx210.GcuFault.bit.ResolverParity); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawPageTitle("Ecu Fault", "6/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "OILMS:", Rx310.EcuFault.bit.OilPressureMissing, "INTOT:", Rx310.EcuFault.bit.IntakeOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ENGOT:", Rx310.EcuFault.bit.EngineOverHeat, "ACTUA:", Rx310.EcuFault.bit.Actuator); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "RPMSG:", Rx310.EcuFault.bit.RpmSignal, "ENGSF:", Rx310.EcuFault.bit.EngineStartFail); +} +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 0U) ? (const int8*)"P" : (const int8*)"F"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l3, 13U); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + + switch(row) + { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine(OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + int16 iTemp[2] = { 0, '\0' }; + + // TITLE + CDrawPageTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case OLED_PASS_DIGIT_1: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case OLED_PASS_DIGIT_2: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case OLED_PASS_DIGIT_3: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CTextAlign(OledOperValue.cAlignBuffer, maskBuffer); + CDrawStr(0U, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageMaintenence(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawPageTitle("Maintenence", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "Switch Test ", NULL, NULL); +} +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + Uint16 y = 0U; + switch(row) { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine(OLED_LINE_TITLE + 2U, "Key input Test"); + + // TITLE2 + CDrawCenteredLine(OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + // " Stat:" + Status + // This is special indentation. + // I can reuse CDrawKeyStatusLine if I pass proper label. + // " Stat:" is 19 chars. + CDrawKeyStatusLine(OLED_ROW_2, " Stat:", GPIO_KEY_START(), NULL, 0, NULL, 0); + + // LINE 3 + // " Up:" + s + " " + "Entr:" + s + " " + "Powr:" + s + CDrawKeyStatusLine(OLED_ROW_3, " Up:", GPIO_KEY_UP(), "Entr:", GPIO_KEY_ENTER(), "Powr:", GPIO_KEY_POWER()); + + // LINE 4 + // "Down:" + s + " " + "Menu:" + s + " " + "Emgc:" + s + CDrawKeyStatusLine(OLED_ROW_4, "Down:", GPIO_KEY_DOWN(), "Menu:", GPIO_KEY_MENU(), "Emgc:", GPIO_KEY_EMERGENCY()); +} +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "Shutting down..."); +} +void CSetPage(Uint16 PageNum) +{ + int16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0; i < OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler + } + } +} + +void COledBufferReset(void) +{ + (void) memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void) memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // + CDrawLine(8U, 10U, 10U, 12U); // 𼭸 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // Ʒ + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 𼭸 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // + + if (OledOperValue.uiPageNum != OLED_PAGE_PASSWORD) + { + // ŸƲ ڽ + CDrawLine(98U, 0U, 98U, 9U); // + CDrawLine(98U, 10U, 100U, 12U); // 𼭸 + CDrawLine(101U, 12U, 118U, 12U); // Ʒ + CDrawLine(119U, 12U, 121U, 10U); // 𼭸 + CDrawLine(121U, 0U, 121U, 9U); // + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = y / 8; j < (y + height) / 8; j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + int16 i; + + CInitOledModule(); + + for(uiPageNum = 0; uiPageNum < 8; uiPageNum++) + { + COledWrite((Uint16)(0xB0 | uiPageNum), MODE_COMMAND); + + for(i = 0; i < OLED_WIDTH; i++) + { + COledWrite(0x00, MODE_DATA); + } + } + + CInitProgress(); +} + +void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, OLED_LINE_TITLE, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void) memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = (TXT_MAX_LEN - 1) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0; + i = 0; + + while (str[i] != '\0') // str int8* ̹Ƿ, int8 Ÿ (0) ã + { + uiLen++; + i++; + } + + if (uiLen >= TXT_MAX_LEN) + { + uiIndent = 0; + } + else + { + uiIndent = ((TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < TXT_MAX_LEN)) // ҽ Һ + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = (int8)' '; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = 0; +} + +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // + CDrawLine(x, (y + 1U), x, (y + h)); // + CDrawLine(x, (y + h), w, (y + h)); // Ʒ + CDrawLine(w, (y + 1U), w, (y + h - 1U)); // +} + +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + if (x2 > OledOperValue.Point.X2) + { + OledOperValue.Point.X2 = x2; + } + if (y2 > OledOperValue.Point.Y2) + { + OledOperValue.Point.Y2 = y2; + } +} + +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 tmp = 0, x = 0, y = 0, dx = 0, dy = 0, swapxy = 0; + Uint16 loop_end = 0; + Uint16 minor_limit = 0; // (y) Ѱ谪 + int16 err = 0, ystep = 0; + + dx = x2 - x1; + + dy = (y1 > y2) ? (y1 - y2) : (y2 - y1); + + if (dy > dx) + { + swapxy = 1; + tmp = dx; dx = dy; dy = tmp; + tmp = x1; x1 = y1; y1 = tmp; + tmp = x2; x2 = y2; y2 = tmp; + + loop_end = OLED_HEIGHT - 1; + minor_limit = OLED_WIDTH - 1; + } + else + { + loop_end = OLED_WIDTH - 1; + minor_limit = OLED_HEIGHT - 1; + } + + if (x2 > loop_end) + { + x2 = loop_end; + } + + err = dx >> 1; + ystep = (y2 > y1) ? 1 : -1; + y = y1; + + if (swapxy == 0) + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } + else + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage = y / 8U; + Uint16 uiOffset = y % 8U; + + if (x >= OLED_WIDTH || y >= OLED_HEIGHT) + { + x = OLED_WIDTH; + y = OLED_HEIGHT; + } + else + { + if (x < OLED_WIDTH) + { + if (Color) + { + OledOperValue.uiBuff[x][uiPage] |= (0x01U << uiOffset); + } + else + { + OledOperValue.uiBuff[x][uiPage] &= (Uint16) ~(0x01U << uiOffset); + } + } + } +} + +void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0), MODE_COMMAND); +} + +void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0F) | 0x10; + LowAddress = x & 0x0F; + + COledWrite(LowAddress, MODE_COMMAND); + COledWrite(HighAddress, MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 1; + XintfRegs.XTIMING6.bit.XWRACTIVE = 13; + XintfRegs.XTIMING6.bit.XWRTRAIL = 1; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 1; + XintfRegs.XTIMING6.bit.XRDACTIVE = 13; + XintfRegs.XTIMING6.bit.XRDTRAIL = 1; + + XintfRegs.XTIMING6.bit.X2TIMING = 1; + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len) +{ + Uint16 i; + + if ((len > 0U) && (len < TXT_MAX_LEN)) // ҽ Һ + { + for(i = 0; i < len; i++) + { + if (str[i] & 0x80) + { + CDrawChar(x, y, (Uint16)((str[i] << 8) | str[i + 1]), TXT_TYPE_ETC); + i++; + x += TXT_ENG_WIDTH * 2U; + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + } + } +} + +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0) // Eng Char + { + uiCharWidth = TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = TXT_ENG_WIDTH * 2U; + ch = (ch == 0xA1C9U) ? 0x00U : ch; + pFontData = EtcFontTable[ch]; + } + + CSetDrawRegion(x, y, (x + TXT_ENG_WIDTH), (y + TXT_ENG_HEIGHT)); + + for(j = 0; j < TXT_ENG_HEIGHT; j++) + { + for(i = 0; i < uiCharWidth; i++) + { + if (pFontData[uiFontIndex / 8] & uiBitMask[uiFontIndex % 8]) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +void CInitOledModule(void) +{ + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + GPIO_OLED_RESET(0U); + DELAY_US(2000L); + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + + COledWrite(0xFD, MODE_COMMAND); // Command Lock + COledWrite(0x12, MODE_COMMAND); // + COledWrite(0xAE, MODE_COMMAND); // oled off + COledWrite(0xA1, MODE_COMMAND); // 1U segment column address high to low + + COledWrite(0xC8, MODE_COMMAND); // COM output scan from high to low + + COledWrite(0x81, MODE_COMMAND); // 1U contrast + COledWrite(0xFF, MODE_COMMAND); + + COledWrite(0xAF, MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = OLED_LOAD_PROGRESS_X + 1; +} + +void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +void CInitOledStructure(void) +{ + (void) memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void) memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +Uint16 CStrLen(const int8 *s) +{ + // ּҸ մϴ. + const int8 *p = s; + + // Ͱ ('\0', ASCII 0) Ű ͸ ŵϴ. + // ڿ ӵ ޸ Ǿ ֽϴ. + while (*p != '\0') + { + p++; + } + + // ּ( ) ּ ̰ ڿ ̰ ˴ϴ. + return (Uint16)(p - s); +} + +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + + for (i = 0; i < Size; i++) + { + pTarget[i] = pSource[i]; + } + pTarget[i] = '\0'; +} + +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + + uiTargetSize = (Uint16)CStrLen(pTarget); + + if ((uiTargetSize + Size) < TXT_MAX_LEN) + { + for (i = 0; i < Size; i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = '\0'; + } +} + +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U, uiSignLocate = 0U, i; + Uint16 x, y; + int32 lData = (int32) Data * 10; + int8 cTmp[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + if (lData < 0) + { + // ǥ ڰ + uiSign = 1U; + lData = -lData; + } + + while (lData > 0U) + { + cTmp[x++] = (lData % 10) + '0'; + lData /= 10U; + } + + if (x == 0) // ġ 0 . + { + y = 3U; + Array[y++] = '0'; + } + else + { + y = 5 - x; // Ǵ . + x = x - 1; // ε . + + if (y < 1) + { + uiSignLocate = 0U; + } + else + { + if ((y >= 1) && (y <= 5)) + { + uiSignLocate = (Uint16)(y - 1); // '-' ȣ ǥ ڸ + } + } + + if (uiSign == 1U) // '-' ȣ ǥ ġ ϱ . + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U)) + { + Array[uiSignLocate] = '-'; + } + } + else + { + Array[uiSignLocate] = ' '; + } + + while (x > 0) + { + Array[y++] = cTmp[x--]; + } + } + Array[y] = '\0'; // End of string. +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 x = 0U, y = 0U, i; + int16 iTemp = (int16)(Data * 10); + int8 cTmp[4] = { 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + while (iTemp > 0U) + { + cTmp[x++] = (iTemp % 10) + '0'; + iTemp /= 10U; + } + + if (x == 0U) // ġ 0.0 . + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = '0'; + } + else + { + if (x == 1U) + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + else + { + y = 5U - x; // Ǵ . + x = x - 1U; // ε . + + while (x > 0U) + { + Array[y++] = cTmp[x--]; + if (x == 0U) + { + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + } + } + } + Array[y] = '\0'; // End of string. +} + +void CInitializePage(void) +{ + if (AdcOperValue.uiOffsetAdjustStart == 0U) + { + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < OLED_LOAD_PROGRESS_W - 3) // -3 α׷ ¿ 1ȼ . + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(OLED_ROW_2, "EHT:", PowerOnCheckValue.EngineHeaterSensor, "GPL:", PowerOnCheckValue.GlowPlugSensor, "SOL:", PowerOnCheckValue.SolenoidSensor); + + // LINE 3 + CDrawPostStatusLine(OLED_ROW_3, "FUP:", PowerOnCheckValue.FuelPumpSensor, "CLP:", PowerOnCheckValue.CoolantPumpSensor, "FN1:", PowerOnCheckValue.Fan1Sensor); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(OLED_ROW_4, "FN2:", PowerOnCheckValue.Fan2Sensor, NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +void CReversString(int8 *str, int16 length) +{ + Uint16 i = 0U; + Uint16 end = length - 1U; + int8 temp; + + while (i < end) + { + temp = str[i]; + str[i] = str[end]; + str[end] = temp; + i++; + end--; + } +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = num; // Է¹ (: 1234567 -> "12345.67") + + // 1. Ҽ ° ڸ (100 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 2. Ҽ ù° ڸ (10 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 3. Ҽ + str[i++] = '.'; + + // 4. ȯ + // Է 0̾ ּ "0" do-while + do + { + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + } + while (temp != 0); + + // 5. ä (ڸ ) + // 5ڸ + 1ڸ + Ҽ2ڸ = 8ڸ + while (i < 8U) + { + str[i++] = ' '; + } + + str[i] = '\0'; // ڿ ˸ + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(eApuOperIdx idx) +{ + // ε 1:1 ĪǴ ڿ 迭 static Ͽ Լ ȣ 迭 ٽ ʵ + static const int8* strTable[] = + { + "BOOT", // 0: APU_OPER_IDX_BOOT + "INIT", // 1: APU_OPER_IDX_INITIAL + "POST", // 2: APU_OPER_IDX_POST + "EMERGENCY", // 3: APU_OPER_IDX_EMERGENCY + "STANDBY", // 4: APU_OPER_IDX_STANDBY + "START_CHECK", // 5: APU_OPER_IDX_START_CHECK + "PREHEAT", // 6: APU_OPER_IDX_ACTIVE_ENG_HEAT + "CRANKING", // 7: APU_OPER_IDX_CRANKING + "WARM_UP", // 8: APU_OPER_IDX_ENG_WARMING_UP + "CHECK_OPER", // 9: APU_OPER_IDX_CHECK_OPERATION + "GENERATING", // 10: APU_OPER_IDX_SET_GCU_GEN_START + "STABLED", // 11: APU_OPER_IDX_ENG_START_DONE + "STOP", // 12: APU_OPER_IDX_ENG_STOP_NORMAL + "COOLDOWN" // 13: APU_OPER_IDX_ENG_STOP_COOLDOWN + }; + + return strTable[idx]; +} diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ new file mode 100644 index 0000000..95dd823 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ new file mode 100644 index 0000000..be86c38 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ new file mode 100644 index 0000000..e2d1e35 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ new file mode 100644 index 0000000..545526b --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ new file mode 100644 index 0000000..cfe478f --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ new file mode 100644 index 0000000..4714194 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ new file mode 100644 index 0000000..b5a7be5 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void InitXintf(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 b/.staticdata/.previous/20260113_090633/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 new file mode 100644 index 0000000..a9a4b68 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 @@ -0,0 +1,1143 @@ +#include "main.h" + +CCommCheck CommCheck; + +// Tx +static CTx100 Tx100; +static CTx101 Tx101; +CTx102 Tx102; +CTx103 Tx103; +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx130 Tx130; +static CTx131 Tx131; +static CTx132 Tx132; + +// Rx - GCU +static CRx200 Rx200; +static CRx201 Rx201; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +static CRx300 Rx300; +static CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); + +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // ѹ̶ ŵǾٸ ش ġ Ǿٰ Ǵ. + CommCheck.CarComputer = 0U; // ۽ ŸӾƿ īƮ Ŭ + /* + if (ECanShadow.CANRMP.bit.RMP15 == 1U) + { + ECanShadow.CANRMP.bit.RMP15 = 1U; + } + + if (ECanShadow.CANRMP.bit.RMP16 == 1U) + { + ECanShadow.CANRMP.bit.RMP16 = 1U; + } +*/ + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +void CSendECanDataA(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + Uint16 uiTemp; + + // 10ms + ECanaMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.ApuData.PlayState & 0x7U; + + uiTemp = (Tx101.ApuData.AlarmOccured << 0U) | (Tx101.ApuData.Emergency << 1U) | (Tx101.ApuData.PowerSwitch << 2U); + ECanaMboxes.MBOX1.MDL.byte.BYTE1 = uiTemp; + ECanaMboxes.MBOX1.MDL.byte.BYTE2 = Tx101.ApuData.GcuPlayState & 0x7U; + + uiTemp = (Tx101.ApuData.GcuAlarmOccured << 0U) | (Tx101.ApuData.GcuShutdown << 1U); + ECanaMboxes.MBOX1.MDL.byte.BYTE3 = uiTemp; + + uiTemp = (Tx101.ApuData.EcuAlarmOccured << 0U) | + ((Tx101.ApuData.EcuPlayState & 0x3FU) << 1U) | + (Tx101.ApuData.OverrideActive << 4U) | + (Tx101.ApuData.GlowPlugActive << 5U) | + (Tx101.ApuData.HeaterActive << 6U) | + (Tx101.ApuData.OilPressureMissing); + ECanaMboxes.MBOX1.MDH.byte.BYTE4 = uiTemp; + + ECanaMboxes.MBOX1.MDH.byte.BYTE5 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE6 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE7 = 0; + + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanaMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX2.MDH.all = 0x00000000U; + ECanaMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanaMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX3.MDH.all = 0x00000000U; + ECanaMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanaMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX4.MDH.all = 0x00000000U; + ECanaMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanaMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX6.MDH.all = 0x00000000U; + ECanaMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanaMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX7.MDH.all = 0x00000000U; + ECanaMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanaMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX8.MDH.all = 0x00000000U; + ECanaMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanaMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX9.MDH.all = 0x00000000U; + ECanaMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanaMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX28.MDH.all = 0x00000000U; + ECanaMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanaMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX29.MDH.all = 0x00000000U; + ECanaMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanaMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX30.MDH.all = 0x00000000U; + ECanaMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanaRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanaRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.GcuData.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.GcuData.VersionMajor = (Uint8)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.GcuData.VersionMinor = (Uint8)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.GcuData.VersionPatch = (Uint8)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.GcuData.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + + Rx201.GcuData.AlarmOccured = (Uint16)((uiMBOXMdl >> 16U) & 0x1U); + Rx201.GcuData.Shutdown = (Uint16)((uiMBOXMdl >> 17U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX17 - 210h (Ʈ ʵ ) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx210.GcuWarning.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat1 = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat2 = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + + Rx210.GcuFault.bit.HwTrip = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx210.GcuFault.bit.HwIgbt = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx210.GcuFault.bit.HwDc = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentU = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentV = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentW = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + Rx210.GcuFault.bit.DcOverVoltage = (Uint16)((uiMBOXMdl >> 14U) & 0x1U); + Rx210.GcuFault.bit.DcOverCurrent = (Uint16)((uiMBOXMdl >> 15U) & 0x1U); + + Rx210.GcuFault.bit.CrankningOverCurrent = (Uint16)((uiMBOXMdl >> 0U) & 0x1U); + Rx210.GcuFault.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 1U) & 0x1U); + Rx210.GcuFault.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 2U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat1 = (Uint16)((uiMBOXMdl >> 3U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat2 = (Uint16)((uiMBOXMdl >> 4U) & 0x1U); + Rx210.GcuFault.bit.GenOverSpeed = (Uint16)((uiMBOXMdl >> 5U) & 0x1U); + Rx210.GcuFault.bit.ResolverIC = (Uint16)((uiMBOXMdl >> 6U) & 0x1U); + Rx210.GcuFault.bit.ResolverParity = (Uint16)((uiMBOXMdl >> 7U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.GcuData.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.GcuData.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // MDH Reverse: Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.GcuData.Rpm = uiRpmL | (uiRpmH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.GcuData.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.GcuData.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GcuData.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GcuData.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.EcuData.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.EcuData.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.EcuData.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.OperationInfo.AlarmOccured = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx301.OperationInfo.PlayState = (Uint16)((uiMBOXMdl >> 25U) & 0x7U); // (24 + 1) + Rx301.OperationInfo.OverrideActive = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); // (24 + 4) + Rx301.OperationInfo.GlowPlugActive = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx301.OperationInfo.HeaterActive = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx301.OperationInfo.OilPressureMissing = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx310.EcuWarning.bit.reserved = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx310.EcuWarning.bit.LowOilLevel = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx310.EcuWarning.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx310.EcuWarning.bit.IntakeLoPressure = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx310.EcuWarning.bit.EngineLoTemperature = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx310.EcuWarning.bit.EngineSensor = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx310.EcuWarning.bit.DefaltValueActive = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + + // [Reverse] Byte 2 -> >> 8 + Rx310.EcuFault.bit.OilPressureMissing = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx310.EcuFault.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx310.EcuFault.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx310.EcuFault.bit.Actuator = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx310.EcuFault.bit.RpmSignal = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx310.EcuFault.bit.EngineStartFail = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.EcuData.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.EcuData.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.EcuData.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.EcuData.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.EcuData.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.EcuData.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.EcuData.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.EcuData.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.EcuData.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.EcuData.BarometicPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.EcuData.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.EcuData.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.EcuData.TotalOperTimeL) | ((Uint32)Rx322.EcuData.TotalOperTimeH << 16U); + GeneralOperValue.ulTotalOperationHour = (GeneralOperValue.ulTotalOperationHour > 1000000UL) ? 1000000UL : GeneralOperValue.ulTotalOperationHour; + } + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + // 10ms + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = 0x1; + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = 0x2; + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x3; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x4; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x5; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = 0x6; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = 0x7; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = 0x8; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; // 100h + ECanShadow.CANTRS.bit.TRS4 = 1U; // 110h + ECanShadow.CANTRS.bit.TRS5 = 1U; // 120h + ECanShadow.CANTRS.bit.TRS6 = 1U; // 121h + ECanShadow.CANTRS.bit.TRS7 = 1U; // 130h + ECanShadow.CANTRS.bit.TRS8 = 1U; // 131h + ECanShadow.CANTRS.bit.TRS9 = 1U; // 132h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; // 100h + ECanShadow.CANTA.bit.TA4 = 1U; // 110h + ECanShadow.CANTA.bit.TA5 = 1U; // 120h + ECanShadow.CANTA.bit.TA6 = 1U; // 121h + ECanShadow.CANTA.bit.TA7 = 1U; // 130h + ECanShadow.CANTA.bit.TA8 = 1U; // 131h + ECanShadow.CANTA.bit.TA9 = 1U; // 132h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void) memset(&Tx100, 0, sizeof(CTx100)); + (void) memset(&Tx101, 0, sizeof(CTx101)); + (void) memset(&Tx102, 0, sizeof(CTx102)); + (void) memset(&Tx103, 0, sizeof(CTx103)); + (void) memset(&Tx110, 0, sizeof(CTx110)); + (void) memset(&Tx120, 0, sizeof(CTx120)); + (void) memset(&Tx121, 0, sizeof(CTx121)); + (void) memset(&Tx130, 0, sizeof(CTx130)); + (void) memset(&Tx131, 0, sizeof(CTx131)); + (void) memset(&Tx132, 0, sizeof(CTx132)); + + // Rx - GCU + (void) memset(&Rx200, 0, sizeof(CRx200)); + (void) memset(&Rx201, 0, sizeof(CRx201)); + (void) memset(&Rx210, 0, sizeof(CRx210)); + (void) memset(&Rx220, 0, sizeof(CRx220)); + (void) memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void) memset(&Rx300, 0, sizeof(CRx300)); + (void) memset(&Rx301, 0, sizeof(CRx301)); + (void) memset(&Rx310, 0, sizeof(CRx310)); + (void) memset(&Rx320, 0, sizeof(CRx320)); + (void) memset(&Rx321, 0, sizeof(CRx321)); + (void) memset(&Rx322, 0, sizeof(CRx322)); +} diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 b/.staticdata/.previous/20260113_090633/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 new file mode 100644 index 0000000..e8d04e5 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 @@ -0,0 +1,434 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + struct + { + Uint16 Heartbit : 16; + Uint16 : 8; + Uint16 : 8; + Uint16 : 8; + Uint16 VersionMajor : 8; + Uint16 VersionMinor : 8; + Uint16 VersionPatch : 8; + } ApuData; +} CTx100; + +typedef struct ClassTx101 +{ + struct + { + /* byte 0 */ + Uint16 PlayState : 3; + Uint16 : 5; + + /* byte 1 */ + Uint16 AlarmOccured : 1; + Uint16 Emergency : 1; + Uint16 PowerSwitch : 1; + Uint16 : 5; + + /* byte 2 */ + Uint16 GcuPlayState : 3; + Uint16 : 5; + + /* byte 3 */ + Uint16 GcuAlarmOccured : 1; + Uint16 GcuShutdown : 1; + Uint16 : 6; + + /* byte 4 */ + Uint16 EcuAlarmOccured : 1; + Uint16 EcuPlayState : 3; + Uint16 OverrideActive : 1; + Uint16 GlowPlugActive : 1; + Uint16 HeaterActive : 1; + Uint16 OilPressureMissing : 1; + } ApuData; +} CTx101; + +typedef struct ClassTx102 +{ + struct + { + Uint16 PlayCommand : 4; // 0:3 bit + Uint16 rsvd_padding1 : 4; // 4:7 bit + Uint16 rsvd_padding2 : 8; // 1 byte + Uint16 rsvd_padding3 : 16; // 2:3 byte + Uint16 rsvd_padding4 : 16; // 4:5 byte + Uint16 rsvd_padding5 : 16; // 6:7 byte + } GcuCommand; +} CTx102; + +typedef struct ClassTx103 +{ + struct + { + Uint16 EngineStart : 8; // 0 byte + Uint16 EngineStop : 8; // 1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 RpmSetpoint : 16; // 4:5 byte + Uint16 Override : 8; // 6 byte + Uint16 Emergency : 8; // 7 byte + } EcuCommand; +} CTx103; + +typedef struct ClassTx110 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilLevel : 1; // 1 bit + Uint16 IntakeOverHeat : 1; // 2 bit + Uint16 IntakeLoPressure : 1; // 3 bit + Uint16 EngineLoTemperature : 1; // 4 bit + Uint16 EngineSensor : 1; // 5 bit + Uint16 DefaltValueActive : 1; // 6 bit + Uint16 rsvd_padding : 1; // 16bit е + } bit; + } EcuWarning; + + struct + { + CFaultBitValue ApuFault; + }; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + } GcuFault; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilPressure : 1; // 1 bit + Uint16 Actuator : 1; // 2 bit + Uint16 RpmSignal : 1; // 3 bit + Uint16 EngineStartFail : 1; // 4 bit + Uint16 rsvd_padding : 11; // 16bit е + } bit; + } EcuFault; +} CTx110; + +typedef struct ClassTx120 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx120; + +typedef struct ClassTx121 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx121; + +typedef struct ClassTx130 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CTx130; + +typedef struct ClassTx131 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding1 : 8; // 6 byte + Uint16 rsvd_padding2 : 8; // 7 byte + } EcuData; +} CTx131; + +typedef struct ClassTx132 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } EcuData; +} CTx132; + +typedef struct ClassRx200 +{ + struct + { + Uint16 HeartBit : 16; // 0:1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 rsvd_padding3 : 8; // 4 byte + Uint16 VersionMajor : 8; // 5 byte + Uint16 VersionMinor : 8; // 6 byte + Uint16 VersionPatch : 8; // 7 byte + } GcuData; +} CRx200; + +typedef struct ClassRx201 +{ + struct + { + Uint16 PlayState : 3; // 0:3 bit + Uint16 rsvd_padding1 : 5; // 4:7 bit + + Uint16 AlarmOccured : 1; // 0 bit + Uint16 Shutdown : 1; // 1 bit + Uint16 rsvd_padding2 : 6; // 2:7 bit + } GcuData; +} CRx201; + +typedef struct ClassRx210 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + }GcuFault; +} CRx210; + +typedef struct ClassRx220 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } GcuData; +} CRx220; + +typedef struct ClassRx221 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } GcuData; +} CRx221; + +typedef struct ClassRx300 +{ + struct + { + Uint16 VersionMajor : 8; // 0 byte + Uint16 VersionMinor : 8; // 1 byte + Uint16 VersionPatch : 8; // 2 byte + Uint16 rsvd_padding1 : 8; // 3 byte + Uint16 rsvd_padding2 : 16; // 4:5 byte + Uint16 rsvd_padding3 : 16; // 6:7 byte + } EcuData; +} CRx300; + +typedef struct ClassRx301 +{ + struct + { + Uint16 AlarmOccured : 1; // 0 bit + Uint16 PlayState : 3; // 1:3 bit + Uint16 OverrideActive : 1; // 4 bit + Uint16 GlowPlugActive : 1; // 5 bit + Uint16 HeaterActive : 1; // 6 bit + Uint16 OilPressureMissing : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } OperationInfo; +} CRx301; + +typedef struct ClassRx310 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 reserved : 1; // 1 bit + Uint16 LowOilLevel : 1; // 2 bit + Uint16 IntakeOverHeat : 1; // 3 bit + Uint16 IntakeLoPressure : 1; // 4 bit + Uint16 EngineLoTemperature : 1; // 5 bit + Uint16 EngineSensor : 1; // 6 bit + Uint16 DefaltValueActive : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } bit; + } EcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 OilPressureMissing : 1; // 0 bit + Uint16 IntakeOverHeat : 1; // 1 bit + Uint16 EngineOverHeat : 1; // 2 bit + Uint16 Actuator : 1; // 3 bit + Uint16 RpmSignal : 1; // 4 bit + Uint16 EngineStartFail : 1; // 5 bit + Uint16 rsvd_padding : 10; // 16bit е + } bit; + } EcuFault; +} CRx310; + +typedef struct ClassRx320 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CRx320; + +typedef struct ClassRx321 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } EcuData; +} CRx321; + +typedef struct ClassRx322 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } EcuData; +} CRx322; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CTx102 Tx102; +extern CTx103 Tx103; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +#endif /* SOURCE_COMM_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf b/.staticdata/.previous/20260113_090633/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf new file mode 100644 index 0000000..c4f5352 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf @@ -0,0 +1,214 @@ +#include "main.h" + +void CApuStartReady(void); +void CApuStopProcedure(Uint16 Level); +void CSetEngineActualRpm(Uint16 Rpm); +static void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); +Uint16 CStartSwitchCheck(void); + + +void CApuOperProcedure(void) +{ + if (CApuSystemAlarmCheck() > 0U || KeyOperValue.KeyList.bit.Emergency == 1U) + { + // ˶ ( , ) + CSetApuOperIndex(APU_OPER_IDX_EMERGENCY); + + CActiveChipSelect(0U); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_STANDBY: + { + if (KeyOperValue.KeyList.bit.EngineStartStop == 1U) + { + CSetApuOperIndex(APU_OPER_IDX_START_CHECK); + + CActiveChipSelect(1U); // õŰ ԷµǸ CS ON + + if (CGetEngCoolantTemperature() < -10) // ð µ üũ + { + CSetApuOperIndex(APU_OPER_IDX_ENGINE_PREHEAT); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_CRANKING); + } + } + break; + } + case APU_OPER_IDX_ENGINE_PREHEAT: + { + break; + } + case APU_OPER_IDX_CRANKING: + { + CSetGcuCommand(GCU_OPER_CMD_CRANKING); + + if (CGetGeneratorRpm() > 800) + { + CSetGcuCommand(GCU_OPER_CMD_STOP_CRANKING); + CSetApuOperIndex(APU_OPER_IDX_CHECK_OPERATION); + } + break; + } + case APU_OPER_IDX_CHECK_OPERATION: + { + + } + } + + + } +} + +void CSetApuOperIndex(eApuOperIdx idx) +{ + GeneralOperValue.uiApuState = (Uint16) idx; +} + +eApuOperIdx CGetApuOperIndex(void) +{ + return (eApuOperIdx)GeneralOperValue.uiApuState; +} + +Uint16 CStartSwitchCheck(void) +{ + return KeyOperValue.KeyList.bit.EngineStartStop; +} + + +Uint16 CApuSystemAlarmCheck(void) +{ + return ((FaultBitValue.ulTotal | Rx210.GcuFault.uiTotal | Rx310.EcuFault.uiTotal) > 0) ? 1U : 0U; +} + +void CSetEngineActualRpm(Uint16 Rpm) +{ + float32 fTemp = (float32) Rpm / 0.125f; // 0.125 mean : J1939 Scaling Factor. + + Tx103.EcuCommand.RpmSetpoint = (Uint16) fTemp; +} + +Uint16 CGetEngineActualRpm(void) +{ + float32 fTemp = (float32) Rx320.EcuData.ActualRpm * 0.125f; + + return (Uint16) fTemp; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.GcuData.Rpm; +} + +static void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if (Command == ECU_OPER_CMD_STOP) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(2400U); + } + else if (Command == ECU_OPER_CMD_START) + { + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; + CSetEngineActualRpm(2400U); + } + else + { + // Emergency + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.EcuData.CoolantTemperature - 40; // µ -40 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenence.ManualCranking == 1U) + { + if (CApuSystemAlarmCheck() == 0U) + { + ; // ˶ 츸 ϵ . + } + } + else + { + ; + } + + if (GeneralOperValue.Maintenence.LampTest == 1U) + { + GPIO_CPU_LED_OPERATION(1U); + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + } + else + { + GPIO_CPU_LED_OPERATION(0U); + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + } + + if (GeneralOperValue.Maintenence.KeyTest == 1U) + { + if ((GPIO_KEY_UP() == 1U) && (GPIO_KEY_DOWN() == 1U)) + { + GeneralOperValue.Maintenence.KeyTest = 0U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + } + } +} + +void CLedControlProcedure(void) +{ + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_EMERGENCY: + { + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_STANDBY: + { + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_ENGINE_STABLED: + { + GPIO_CPU_LED_OPERATION(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + break; + } + default: + { + break; + } + } +} diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ new file mode 100644 index 0000000..3d2dc0f --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ new file mode 100644 index 0000000..4d3413d --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ new file mode 100644 index 0000000..ff2d98b --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b b/.staticdata/.previous/20260113_090633/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b new file mode 100644 index 0000000..6b72ad5 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b @@ -0,0 +1,151 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +enum +{ + OLED_LINE_TITLE = 0U, + OLED_LINE_1 = 14U, + OLED_LINE_2 = 27U, + OLED_LINE_3 = 40U, + OLED_LINE_4 = 53U +}; + +enum +{ + OLED_ROW_0 = 0U, + OLED_ROW_1, + OLED_ROW_2, + OLED_ROW_3, + OLED_ROW_4 +}; + +enum +{ + OLED_PASS_DIGIT_1 = 0U, + OLED_PASS_DIGIT_2, + OLED_PASS_DIGIT_3, + OLED_PASS_DIGIT_4 +}; + +typedef enum +{ + OLED_PAGE_APU1 = 0U, // 0 + OLED_PAGE_APU2, // 1 + OLED_PAGE_MENU1, // 2 + OLED_PAGE_MENU2, // 3 + OLED_PAGE_TEMP, // 4 + OLED_PAGE_SENSOR1, // 5 + OLED_PAGE_SENSOR2, // 6 + OLED_PAGE_SENSOR3, // 7 + OLED_PAGE_SENSOR4, // 8 + OLED_PAGE_WARNING1, // 9 + OLED_PAGE_WARNING2, // 10 + OLED_PAGE_FAULT1, // 11 + OLED_PAGE_FAULT2, // 12 + OLED_PAGE_FAULT3, // 13 + OLED_PAGE_FAULT4, // 14 + OLED_PAGE_FAULT5, // 15 + OLED_PAGE_FAULT6, // 16 + OLED_PAGE_RESET_ALARM, // 17 + OLED_PAGE_PASSWORD, // 18 + OLED_PAGE_MAINTENENCE, // 19 + OLED_PAGE_KEY_TEST, // 20 + OLED_PAGE_SHUTDOWN, // 21 + OLED_PAGE_MAX +} EOledPage; + +enum +{ + OLED_MENU_APU = 0U, // 0 + OLED_MENU_TEMP, // 1 + OLED_MENU_SENSOR, // 2 + OLED_MENU_WARNING, // 3 + + OLED_MENU_FAULT = 0U, // 0 + OLED_MENU_RESET, // 1 + OLED_MENU_DEBUG // 2 +}; + +enum +{ + OLED_LINE_FOCUS_1 = 0U, + OLED_LINE_FOCUS_2, + OLED_LINE_FOCUS_3, + OLED_LINE_FOCUS_4 +}; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiAlarmPopCheck; + Uint16 uiAlreadyAlarm; + Uint16 uiPrevAlarmPage; + Uint16 uiResetAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X1; + Uint16 Y1; + Uint16 X2; + Uint16 Y2; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe b/.staticdata/.previous/20260113_090633/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe new file mode 100644 index 0000000..fe8e0e0 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe @@ -0,0 +1,47 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef enum +{ + APU_OPER_IDX_BOOT = 0U, // 0 + APU_OPER_IDX_INITIAL, // 1 + APU_OPER_IDX_POST, // 2 + APU_OPER_IDX_EMERGENCY, // 3 + APU_OPER_IDX_STANDBY, // 4 + APU_OPER_IDX_START_CHECK, // 5 + APU_OPER_IDX_ENGINE_PREHEAT, // 6 + APU_OPER_IDX_CRANKING, // 7 + APU_OPER_IDX_ENGINE_WARM_UP, // 8 + APU_OPER_IDX_CHECK_OPERATION, // 9 + APU_OPER_IDX_GENERATING, // 10 + APU_OPER_IDX_ENGINE_STABLED, // 11 + APU_OPER_IDX_ENGINE_STOP, // 12 + APU_OPER_IDX_ENGINE_COOLDOWN // 13 +} eApuOperIdx; + +typedef enum +{ + GCU_OPER_CMD_STOP = 0U, // 0 + GCU_OPER_CMD_CRANKING, // 1 + GCU_OPER_CMD_STOP_CRANKING, // 2 + GCU_OPER_CMD_GENERATING // 3 +} eGcuCmdIdx; + +typedef enum +{ + ECU_OPER_CMD_STOP = 0U, // 0 + ECU_OPER_CMD_START, // 1 + ECU_OPER_CMD_EMERGENCY // 2 +} eEcuCmdIdx; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +Uint16 CApuSystemAlarmCheck(void); +void CSetApuOperIndex(eApuOperIdx idx); +eApuOperIdx CGetApuOperIndex(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); + +#endif /* SOURCE_OPER_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ new file mode 100644 index 0000000..5b0001b --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/.staticdata/.previous/20260113_090633/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/.staticdata/.previous/20260113_090633/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/.staticdata/.previous/20260113_090633/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ new file mode 100644 index 0000000..4ce9ce2 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ new file mode 100644 index 0000000..4831619 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ new file mode 100644 index 0000000..4c4b852 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ new file mode 100644 index 0000000..c40164d --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ new file mode 100644 index 0000000..0aa33dc --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ new file mode 100644 index 0000000..6614163 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ new file mode 100644 index 0000000..3b00d75 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 b/.staticdata/.previous/20260113_090633/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 new file mode 100644 index 0000000..19b41d3 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 @@ -0,0 +1,192 @@ +#ifndef CFONT_H +#define CFONT_H + +const Uint16 EngFontTable[96][9] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ! + { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // # + { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $ + { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // % + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // & + { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' + { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // ( + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // ) + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // * + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // , + { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // - + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // . + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // / + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0 + { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1 + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2 + { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3 + { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4 + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5 + { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6 + { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7 + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8 + { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9 + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // : + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ; + { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // < + { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // = + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // > + { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ? + { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @ + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A + { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B + { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D + { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E + { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G + { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J + { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K + { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M + { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S + { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T + { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V + { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W + { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // Y + { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z + { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [ + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON) + { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ] + { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _ + { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ` + { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b + { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c + { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e + { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k + { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l + { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n + { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q + { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r + { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t + { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w + { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z + { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // { + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // | + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // } + { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~ + { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, //  +}; + +const Uint16 EtcFontTable[81][18] = +{ + { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }, // , A1C9 + { 0x00, 0x06, 0x00, 0x78, 0x07, 0xE0, 0x7F, 0x87, 0xFC, 0x7F, 0x87, 0xE0, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00 }, // , A2BA + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x12, 0xA1, 0x2A, 0x24, 0xC2, 0x48, 0x3C, 0xA4, 0x34, 0x40, 0x00, 0x00 }, // , A7A1 + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x68, 0xA5, 0x4A, 0x54, 0xC5, 0x48, 0x54, 0xA5, 0x54, 0x00, 0x00, 0x00 }, // , A7A2 + { 0x00, 0x00, 0x44, 0x04, 0xA0, 0x4A, 0x1C, 0xA2, 0x4A, 0x24, 0xC2, 0x48, 0x25, 0xA1, 0xE4, 0x00, 0x00, 0x00 }, // , A7A3 + { 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0x05, 0x00, 0x50, 0x06, 0x00, 0x40, 0x0D, 0x00, 0x20, 0x00, 0x00, 0x00 }, // , A7A4 + { 0x00, 0x02, 0x04, 0x20, 0xA2, 0x0A, 0x24, 0xA2, 0x8A, 0x30, 0xC3, 0x08, 0x29, 0x52, 0x62, 0x00, 0x00, 0x00 }, // , A7A5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xC2, 0x52, 0x21, 0x02, 0x10, 0x25, 0x21, 0x8C, 0x00, 0x00, 0x00 }, // , A7A6 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x6A, 0x95, 0x56, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7A7 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x36, 0x94, 0xD6, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7A8 + { 0x00, 0x00, 0x04, 0x00, 0x20, 0x04, 0x76, 0x24, 0x94, 0x49, 0x04, 0x90, 0x49, 0x04, 0x90, 0x00, 0x00, 0x00 }, // , A7A9 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x02, 0x4E, 0x95, 0x56, 0x65, 0x45, 0x54, 0x4D, 0x44, 0x54, 0x00, 0x00, 0x00 }, // , A7AA + { 0x00, 0x00, 0x80, 0x10, 0x01, 0x00, 0x3B, 0x41, 0x2A, 0x12, 0xA1, 0x2A, 0x12, 0xA1, 0x2A, 0x00, 0x00, 0x00 }, // , A7AB + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x44, 0xAA, 0x4A, 0xA4, 0xAA, 0x4A, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7AC + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0xA1, 0x55, 0x29, 0x52, 0x95, 0x35, 0x54, 0x15, 0x40, 0x00, 0x00 }, // , A7AD + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xA5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00 }, // , A7AE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x44, 0xAA, 0x42, 0xA4, 0x2A, 0x4A, 0xA3, 0x2A, 0x00, 0x00, 0x00 }, // , A7AF + { 0x00, 0x04, 0x00, 0x40, 0x04, 0x00, 0x4B, 0x45, 0x2A, 0x62, 0xA6, 0x2A, 0x52, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7B0 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x6A, 0xA5, 0x57, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7B1 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x36, 0xA4, 0xD7, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7B2 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x3B, 0x22, 0x4B, 0x24, 0x82, 0x48, 0x24, 0x82, 0x48, 0x00, 0x00, 0x00 }, // , A7B3 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x01, 0x4E, 0xA5, 0x57, 0x65, 0x46, 0x54, 0x55, 0x44, 0xD4, 0x00, 0x00, 0x00 }, // , A7B4 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x38, 0xC2, 0x52, 0x24, 0xE2, 0x52, 0x25, 0x22, 0x4D, 0x00, 0x00, 0x00 }, // , A7B5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xE1, 0x52, 0x29, 0x22, 0x92, 0x34, 0xE4, 0x12, 0x40, 0xC0, 0x00 }, // , A7B6 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xE5, 0x52, 0x55, 0x25, 0x52, 0x54, 0xE5, 0x52, 0x00, 0xC0, 0x00 }, // , A7B7 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x24, 0xE2, 0x92, 0x31, 0x23, 0x12, 0x28, 0xE2, 0x52, 0x00, 0xC0, 0x00 }, // , A7B8 + { 0x00, 0x02, 0x08, 0x20, 0x82, 0x08, 0x25, 0xC2, 0x88, 0x30, 0x83, 0x08, 0x28, 0xA2, 0x44, 0x00, 0x00, 0x00 }, // , A7B9 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x33, 0x14, 0xC9, 0x43, 0x94, 0x49, 0x4C, 0x93, 0x35, 0x00, 0x00, 0x00 }, // , A7BA + { 0x00, 0x04, 0x01, 0x40, 0x14, 0x01, 0x56, 0x96, 0x95, 0x68, 0xD6, 0x95, 0x59, 0x55, 0x6B, 0x00, 0x00, 0x00 }, // , A7BB + { 0x00, 0x00, 0x5C, 0x05, 0x20, 0x52, 0x1D, 0x22, 0x5C, 0x25, 0x22, 0x52, 0x25, 0x21, 0xDC, 0x00, 0x00, 0x00 }, // , A7BC + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x68, 0xE5, 0x59, 0x55, 0x45, 0x52, 0x55, 0x95, 0x56, 0x00, 0x00, 0x00 }, // , A7BD + { 0x00, 0x00, 0x12, 0x01, 0x10, 0x21, 0x6A, 0xE5, 0x73, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7BE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x39, 0x22, 0x0C, 0x20, 0x00, 0x00 }, // , A7BF + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x25, 0x22, 0x4C, 0x00, 0x00, 0x00 }, // , A7C0 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x61, 0x29, 0x24, 0x42, 0x42, 0x3A, 0x94, 0x06, 0x40, 0x00, 0x00 }, // , A7C1 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC5, 0x52, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7C2 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x39, 0x42, 0x54, 0x25, 0x42, 0x48, 0x38, 0x82, 0x08, 0x20, 0x00, 0x00 }, // , A7C3 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x71, 0x44, 0x94, 0x49, 0x44, 0x88, 0x48, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C4 + { 0x00, 0x00, 0x11, 0x01, 0x10, 0x11, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x44, 0x3A, 0x44, 0x04, 0x40, 0x00, 0x00 }, // , A7C5 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x69, 0x45, 0x54, 0x55, 0x45, 0x48, 0x54, 0x85, 0x48, 0x00, 0x00, 0x00 }, // , A7C6 + { 0x00, 0x04, 0x22, 0x42, 0x24, 0x22, 0x49, 0x45, 0x14, 0x61, 0x46, 0x08, 0x50, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C7 + { 0x00, 0x04, 0x51, 0x45, 0x16, 0xD1, 0x6C, 0xA5, 0x4A, 0x54, 0xA5, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00 }, // , A7C8 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0x44, 0xBE, 0x72, 0x24, 0x22, 0x40, 0x00, 0x00 }, // , A7C9 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0xC4, 0xA2, 0x4A, 0x24, 0xA2, 0x00, 0x00, 0x00 }, // , A7CA + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x5F, 0x3B, 0x14, 0x11, 0x40, 0x00, 0x00 }, // , A7CB + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x68, 0xA5, 0x4A, 0x54, 0xA5, 0x5F, 0x55, 0x15, 0x51, 0x00, 0x00, 0x00 }, // , A7CC + { 0x00, 0x02, 0x04, 0x20, 0x42, 0x04, 0x24, 0xA2, 0x8A, 0x30, 0xA3, 0x1F, 0x29, 0x12, 0x51, 0x00, 0x00, 0x00 }, // , A7CD + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x71, 0x44, 0x14, 0x40, 0x00, 0x00 }, // , A7CE + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x49, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7CF + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x15, 0x51, 0x55, 0x29, 0x52, 0x8A, 0x34, 0xA4, 0x0A, 0x40, 0x00, 0x00 }, // , A7D0 + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x69, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x54, 0xA5, 0x4A, 0x00, 0x00, 0x00 }, // , A7D1 + { 0x00, 0x04, 0x2A, 0x42, 0xA4, 0x2A, 0x4A, 0xA5, 0x2A, 0x62, 0xA6, 0x14, 0x51, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7D2 + { 0x00, 0x04, 0x55, 0x45, 0x56, 0xD5, 0x6D, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x44, 0xA4, 0x4A, 0x00, 0x00, 0x00 }, // , A7D3 + { 0x00, 0x02, 0x40, 0x24, 0x02, 0x40, 0x25, 0xE3, 0xC2, 0x24, 0x42, 0x48, 0x25, 0x02, 0x5E, 0x00, 0x00, 0x00 }, // , A7D4 + { 0x00, 0x04, 0x50, 0x45, 0x04, 0x50, 0x55, 0x75, 0x71, 0x65, 0x26, 0x52, 0x55, 0x45, 0x57, 0x00, 0x00, 0x00 }, // , A7D5 + { 0x00, 0x04, 0x48, 0x44, 0x86, 0xC8, 0x6C, 0xF5, 0x79, 0x54, 0xA5, 0x4A, 0x54, 0xC4, 0x4F, 0x00, 0x00, 0x00 }, // , A7D6 + { 0x00, 0x03, 0x28, 0x4A, 0x84, 0xA8, 0x42, 0xF5, 0xB9, 0x4A, 0xA4, 0xAA, 0x4A, 0xC3, 0xAF, 0x00, 0x00, 0x00 }, // , A7D7 + { 0x00, 0x07, 0xE8, 0x12, 0x81, 0x28, 0x12, 0xF1, 0x39, 0x12, 0xA1, 0x2A, 0x12, 0xC1, 0x2F, 0x00, 0x00, 0x00 }, // , A7D8 + { 0x00, 0x00, 0x00, 0x07, 0x00, 0x88, 0x10, 0x41, 0x04, 0x10, 0x40, 0x88, 0x15, 0x41, 0xDC, 0x00, 0x00, 0x00 }, // , A7D9 + { 0x00, 0x04, 0x1C, 0x42, 0x24, 0x22, 0x4A, 0x25, 0x22, 0x61, 0x46, 0x14, 0x51, 0x44, 0xB6, 0x00, 0x00, 0x00 }, // , A7DA + { 0x00, 0x04, 0x4E, 0x45, 0x16, 0xD1, 0x6D, 0x15, 0x51, 0x54, 0xA5, 0x4A, 0x44, 0xA4, 0x5B, 0x00, 0x00, 0x00 }, // , A7DB + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x72, 0x04, 0x20, 0x40, 0x00, 0x00 }, // , A7DC + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x4A, 0x04, 0xA0, 0x00, 0x00, 0x00 }, // , A7DD + { 0x00, 0x00, 0x0F, 0x00, 0x80, 0x08, 0x12, 0x81, 0x2E, 0x24, 0x82, 0x48, 0x3A, 0x84, 0x08, 0x40, 0x00, 0x00 }, // , A7DE + { 0x00, 0x00, 0x02, 0x00, 0x20, 0x02, 0x6B, 0x25, 0x4A, 0x54, 0xA5, 0x4A, 0x54, 0xA5, 0x72, 0x00, 0x00, 0x00 }, // , A7DF + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x31, 0xC4, 0xA4, 0x42, 0x44, 0x24, 0x4A, 0x43, 0x1C, 0x00, 0x00, 0x00 }, // , A7E0 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x56, 0x36, 0x95, 0x47, 0x54, 0x95, 0x49, 0x54, 0x6B, 0x00, 0x00, 0x00 }, // , A7E1 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x54, 0x4E, 0xC0, 0x07, 0x07, 0x87, 0x86, 0x00, 0xC0, 0x02, 0x00, 0xC0, 0x00 }, // , A7E2 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x57, 0x4E, 0xC0, 0x32, 0x1C, 0x16, 0x1A, 0x03, 0x30, 0x08, 0x03, 0x00, 0x00 }, // , A7E3 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xA2, 0x2C, 0x18, 0x80, 0x48, 0x22, 0x81, 0xC8, 0x00, 0x00, 0x00 }, // , A7E4 + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xC2, 0x52, 0x38, 0xE2, 0x12, 0x21, 0x22, 0x0D, 0x00, 0x00, 0x00 }, // , A7E5 + { 0x00, 0x04, 0x60, 0x45, 0x04, 0x50, 0x55, 0xC5, 0x52, 0x66, 0x66, 0x4A, 0x54, 0xA5, 0x47, 0x00, 0x00, 0x00 }, // , A7E6 + { 0x00, 0x04, 0x58, 0x45, 0x46, 0xD4, 0x6D, 0x65, 0x55, 0x55, 0xB5, 0x55, 0x45, 0x54, 0x53, 0x00, 0x00, 0x00 }, // , A7E7 + { 0x00, 0x03, 0x30, 0x4A, 0x84, 0xA8, 0x42, 0xE5, 0xA9, 0x4B, 0x34, 0xA5, 0x4A, 0x53, 0xA3, 0x00, 0x00, 0x00 }, // , A7E8 + { 0x00, 0x05, 0x50, 0x55, 0x05, 0x50, 0x55, 0xC5, 0x52, 0x55, 0x22, 0x92, 0x29, 0x22, 0x9C, 0x00, 0x00, 0x00 }, // , A7E9 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x26, 0x82, 0x54, 0x25, 0x42, 0x54, 0x25, 0x42, 0x54, 0x00, 0x00, 0x00 }, // , A7EA + { 0x00, 0x01, 0x00, 0x10, 0x01, 0x00, 0x14, 0x41, 0x28, 0x11, 0x01, 0x10, 0x12, 0x81, 0x44, 0x00, 0x00, 0x00 }, // , A7EB + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xE3, 0x92, 0x25, 0x22, 0x52, 0x24, 0xE3, 0x82, 0x00, 0x20, 0x00 }, // , A7EC + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x42, 0x25, 0xA2, 0x49, 0x44, 0x94, 0x48, 0x83, 0x08, 0x03, 0x00, 0x00 }, // , A7ED + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x22, 0x21, 0x22, 0x09, 0x44, 0x94, 0x48, 0x83, 0x08, 0x00, 0x00, 0x00 }, // , A7EE + { 0x24, 0x05, 0x60, 0x56, 0x04, 0xA0, 0x4A, 0xB5, 0xAD, 0x2B, 0x51, 0x35, 0x12, 0xB1, 0x2D, 0x00, 0x20, 0x00 } // , A7EF +}; + +extern const Uint16 EngFontTable[96][9]; +extern const Uint16 EtcFontTable[81][18]; +#endif + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ new file mode 100644 index 0000000..ff7633e --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 b/.staticdata/.previous/20260113_090633/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 new file mode 100644 index 0000000..dcd417b --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 @@ -0,0 +1,864 @@ +#include "main.h" + +void CInitAlarmOperValue(void); +void CKeyMainPowerProcess(void); +void CKeyArrowUpProcess(void); +void CKeyArrowDownProcess(void); +void CKeyEnterProcess(void); +void CKeyMenuProcess(void); +void CKeyEngineStartStopProcess(void); +void CKeyEmergencyProcess(void); +void CInitAdcStructure(void); +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh); +Uint32 CGetKey(void); +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void MoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; +CAlarmOperValue AlarmOperValue[IDX_FAULT_MAX]; +CFaultBitValue FaultBitValue; +CKeyOperValue KeyOperValue; + +static const CKeyHandler KeyTable[IDX_KEY_MAX] = +{ + { IDX_KEY_MAIN_POWER, CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, CKeyArrowDownProcess }, + { IDX_KEY_ENTER, CKeyEnterProcess }, + { IDX_KEY_MENU, CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, CKeyEmergencyProcess } +}; + +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN2_I]; + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0f); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0f); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0f); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0f); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0f); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0f); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0f); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + Uint64 ullFaultValue = ((Uint64)FaultBitValue.ulTotal & 0x3FFFFUL) | (((Uint64)Rx210.GcuFault.uiTotal & 0xFFFFU) << 19UL) | (((Uint64)Rx310.EcuFault.uiTotal & 0x3FU) << 35UL); + Uint32 ulWarningValue = ((Uint32)Rx210.GcuWarning.uiTotal & 0x7U) | (((Uint32)Rx310.EcuWarning.uiTotal & 0xFU) << 4U); + Uint16 i; + + if (OledOperValue.uiAlarmPopCheck == 0U) + { + if (ulWarningValue > 0U) + { + for (i = 0U; i < 16U; i++) + { + if ((ulWarningValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = ((i / 9U) + OLED_PAGE_WARNING1); + break; + } + } + } + if (ullFaultValue > 0U) + { + for (i = 0U; i < 64U; i++) + { + if ((ullFaultValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = (((i % 64U) / 8U) + OLED_PAGE_FAULT1); + break; + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0U; + + if (CGetApuOperIndex() == APU_OPER_IDX_EMERGENCY) + { + // Ÿ ƿ ߻ Ʈ Ŭ Ѵ. + GeneralOperValue.Conection.CarComputer = (FaultBitValue.bit.CarCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (FaultBitValue.bit.GcuCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (FaultBitValue.bit.EcuCommTimeOut == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + if (GeneralOperValue.uiAlarmReset == 1U) + { + GeneralOperValue.uiAlarmReset = 0U; + + CInitAlarmOperValue(); + } + } + else + { + if (GeneralOperValue.uiApuState > APU_OPER_IDX_EMERGENCY) + { + // Comm Timeout Checks + FaultBitValue.bit.CarCommTimeout = CAlarmCheck(IDX_FAULT_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GcuCommTimeout = CAlarmCheck(IDX_FAULT_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.EcuCommTimeOut = CAlarmCheck(IDX_FAULT_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK); + + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + // RPM Ǿ Ѵ. + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = ABS(iDiffRpm); + FaultBitValue.bit.RpmError = CAlarmCheck(IDX_FAULT_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK); + } + FaultBitValue.bit.EngineHeatOverCurrent = CAlarmCheck(IDX_FAULT_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GlowPlugOverCurrent = CAlarmCheck(IDX_FAULT_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.SolenoidOverCurrent = CAlarmCheck(IDX_FAULT_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.FuelPumpOverCurrent = CAlarmCheck(IDX_FAULT_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.CoolantPumpOverCurrent = CAlarmCheck(IDX_FAULT_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan1OverCurrent = CAlarmCheck(IDX_FAULT_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan2OverCurrent = CAlarmCheck(IDX_FAULT_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK); + + // Fuse ȣ ġ ϴ CS ON ¿ ۵ϹǷ CS HI , Fuse ȣ HI ܼ + if (CGetApuOperIndex() > APU_OPER_IDX_STANDBY) + { + FaultBitValue.bit.EngineHeatOpen = CheckOpenFault(GPIO_ENGINE_HEATER_CS_READ(), GPIO_ENGINE_HEATER_FUSE()); + FaultBitValue.bit.GlowPlugOpen = CheckOpenFault(GPIO_GLOW_PLUG_CS_READ(), GPIO_GLOW_PLUG_FUSE()); + FaultBitValue.bit.SolenoidOpen = CheckOpenFault(GPIO_SOLENOID_CS_READ(), GPIO_SOLENOID_FUSE()); + FaultBitValue.bit.FuelPumpOpen = CheckOpenFault(GPIO_FUEL_PUMP_CS_READ(), GPIO_FUEL_PUMP_FUSE()); + FaultBitValue.bit.CoolantPumpOpen = CheckOpenFault(GPIO_COOLANT_PUMP_CS_READ(), GPIO_COOLANT_PUMP_FUSE()); + FaultBitValue.bit.Fan1Open = CheckOpenFault(GPIO_FAN1_CS_READ(), GPIO_FAN1_FUSE()); + FaultBitValue.bit.Fan2Open = CheckOpenFault(GPIO_FAN2_CS_READ(), GPIO_FAN2_FUSE()); + } + } + } +} + +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh) +{ + // ȣ 1(High) 1(Fault) ȯ + return ((isCsHigh == 1U) && (isFuseHigh == 1U)) ? 1U : 0U; +} + +void CInitAlarmOperValue(void) +{ + int16 i; + + for (i = 0; i < IDX_FAULT_MAX; i++) + { + (void) memset(&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void) memset(&FaultBitValue, 0, sizeof(CFaultBitValue)); + (void) memset(&CommCheck, 0, sizeof(CCommCheck)); + + // ü/GCU/ECU ȣ ܼ ٸ Լ ó + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[IDX_FAULT_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_RPM_ERR].fCheckLimit = 300.0f; // Value + AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_SOLENOID_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN1_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN2_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime = 10U; // Value + +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_I + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_I + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_I + + AdcRegs.ADCMAXCONV.all = IDX_ADC_MAX; // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + CInitAlarmOperValue(); +} + +void CInitAdcStructure(void) +{ + (void) memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + (void) memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_I.fGain = 0.005637f; + Adc_GlowPlug_I.fGain = 0.005637f; + Adc_Solenoid_I.fGain = 0.005637f; + Adc_FuelPump_I.fGain = 0.005637f; + Adc_CoolantPump_I.fGain = 0.005637f; + Adc_Fan1_I.fGain = 0.005637f; + Adc_Fan2_I.fGain = 0.005637f; + + Adc_EngineHeater_I.fOffset = -2.333f; + Adc_GlowPlug_I.fOffset = -2.333f; + Adc_Solenoid_I.fOffset = -2.333f; + Adc_FuelPump_I.fOffset = -2.333f; + Adc_CoolantPump_I.fOffset = -2.333f; + Adc_Fan1_I.fOffset = -2.333f; + Adc_Fan2_I.fOffset = -2.333f; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ +#if 1 + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 100) + { + AdcBuff->uiSamplingCount = 0; + AdcBuff->fSampledSum /= 100; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledSum) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); + AdcBuff->fSampledSum = 0.0f; + } +#else + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledValue) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); +#endif +} + +Uint32 CGetKey(void) +{ + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + Uint16 ucKeyGpioList[7] = { 67, 39, 31, 30, 29, 66, 64}; + + for (i = 0; i < IDX_KEY_MAX; i++) + { + ucDiv = ucKeyGpioList[i] / 32; + ucMod = ucKeyGpioList[i] % 32; + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + static Uint32 ulLongKeyCnt = 0UL; // Ű īƮ + static Uint16 uiLongKeyProcessed = 0U; // Ű ó Ϸ ÷ (ߺ ) + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~KEY_POWER_MASK; // Ű Ű ϵ, Ű(Bit 0) ȭ (& ~KEY_POWER_MASK) + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // ä͸ + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + // Ű Ű POST ܰ谡 Ѿ Ѵ. + if ((KeyOperValue.uiKeyWaitCount == 0U) && (CGetApuOperIndex() > APU_OPER_IDX_POST)) + { + ulPrevKey = (ulPrevKey & KEY_POWER_MASK) | (ulReadKey & ~KEY_POWER_MASK); // ulPrevKey Ʈ ϰ Ʈ + CKeyCheck(ulChangeKey, ulReadKey); // Ϲ Ű + } + } + } + else + { + // ȭ ä͸ ʱȭ (Ϲ Ű) + // , ִ ulPrevKey ʿ + if ((KeyOperValue.uiKeyWait) != 0U && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // Bit 0 ִ Ȯ (1 = ) + if ((ulReadKey & KEY_POWER_MASK) == KEY_POWER_MASK) + { + // ̹ ó ° ƴ϶ īƮ + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 1(1000ms) + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + CKeyCheck(KEY_POWER_MASK, ulReadKey); // Ű (CKeyCheck Ű Ʈ ) + uiLongKeyProcessed = 1U; // ٽ ʵ ÷ + ulLongKeyCnt = LONG_KEY_TIME; // īƮ ÷ο + } + } + } + else + { + // Ű ʱȭ + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey Bit 0 µ 0 ȭ ( 񱳸 ) + ulPrevKey &= ~KEY_POWER_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + Uint16 i; + + for (i = 0U; i < IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +void CKeyArrowUpProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + } +} + +void CKeyArrowDownProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = OLED_PAGE_APU2; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_4) + { + // Bottom of Menu 1 -> Go to Menu 2 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + MoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CChangePasswordDigit(Uint16 direction) +{ + // Ensure the focus digit is within valid range to avoid out-of-bounds access + if (OledOperValue.uiFocusDigit <= OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void MoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + maxLines - 1U) % maxLines; + } + else // DIR_DOWN + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + 1U) % maxLines; + } +} + +void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case OLED_PAGE_MENU1: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_MENU_APU: + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + break; + } + case OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = OLED_PAGE_TEMP; + break; + } + case OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = OLED_PAGE_WARNING1; + } + break; + } + } + break; + } + case OLED_PAGE_MENU2: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = OLED_PAGE_FAULT1; + break; + } + case OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_RESET_ALARM; + break; + } + case OLED_LINE_FOCUS_3: // Maintenence + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + break; + } + default: + break; + } + break; + } + case OLED_PAGE_PASSWORD: + { + if (OledOperValue.uiFocusDigit < OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + // Check password + const Uint16 uiPassword[4] = DEBUG_MENU_PASSWORD; + + if (memcmp(GeneralOperValue.uiPassword, uiPassword, sizeof(uiPassword)) == 0U) + { + GeneralOperValue.uiMaintenence = 1U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + } + } + break; + } + case OLED_PAGE_RESET_ALARM: + { + // Selected "YES" + if (OledOperValue.uiResetAnswer == 1U) + { + if (CApuSystemAlarmCheck() > 0) + { + GeneralOperValue.uiAlarmReset = 1U; + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + break; + } + case OLED_PAGE_MAINTENENCE: + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenence.ManualCranking = GeneralOperValue.Maintenence.ManualCranking ^ 1U; // Toggle + } + else if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenence.LampTest = GeneralOperValue.Maintenence.LampTest ^ 1U; // Toggle + } + else + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenence.KeyTest = GeneralOperValue.Maintenence.KeyTest ^ 1U; // Toggle + OledOperValue.uiPageNum = OLED_PAGE_KEY_TEST; + } + } + break; + } + default: + { + // Handle Fault/Warning page return logic + if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + if (OledOperValue.uiAlarmPopCheck == 1U) + { + OledOperValue.uiAlreadyAlarm = 1U; + OledOperValue.uiPageNum = OledOperValue.uiPrevAlarmPage; + } + } + break; + } + } +} + +void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_MAINTENENCE)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + GeneralOperValue.uiMaintenence = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + } +} + +void CKeyMainPowerProcess(void) +{ + if (CGetApuOperIndex() <= APU_OPER_IDX_STANDBY) + { + // APU ¿ ġ Է + OledOperValue.uiPageNum = OLED_PAGE_SHUTDOWN; + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, TIME_1SEC) == TIME_OVER) + { + GPIO_POWER_HOLD(0); + } + } +} + +void CKeyEngineStartStopProcess(void) +{ + KeyOperValue.KeyList.bit.EngineStartStop = KeyOperValue.KeyList.bit.EngineStartStop ^ 1U; // Toggle +} + +void CKeyEmergencyProcess(void) +{ + // ġ Ŭ ϱ ؼ APU ýۿ ˶ Ѵ. + KeyOperValue.KeyList.bit.Emergency = KeyOperValue.KeyList.bit.Emergency ^ 1U; // Toggle +} diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ new file mode 100644 index 0000000..9ccf069 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ new file mode 100644 index 0000000..a4564ad --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ new file mode 100644 index 0000000..1461873 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/f9a156ec434632a46725fb267c577743_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/f9a156ec434632a46725fb267c577743_ new file mode 100644 index 0000000..e19cb54 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/f9a156ec434632a46725fb267c577743_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef b/.staticdata/.previous/20260113_090633/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef new file mode 100644 index 0000000..71b6378 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef @@ -0,0 +1,545 @@ +#include "main.h" + +CPowerOnCheckValue PowerOnCheckValue; +CGeneralOperValue GeneralOperValue; + +CSoftTimer SoftTimer[TIMER_MAX]; +CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +Uint32 ulSoftClock; + +void CInitSystem(void); +void CInitGeneralOperValue(void); +void CInitGpio(void); +void CSystemConfigure(void); +void CMappingInterrupt(void); +void CProcessSoftTimer(void); +Uint16 CPowerOnCheck(void); +void CSoftTimerWorkProcess(void); +Uint16 CIsStatusSoftTimer(Uint16 ucTimerIndex); +void CReloadSoftTimer(Uint16 ucTimerIndex); +void CInitSoftTimers(void); +void CInitSoftTimer(void); +void CConfigSoftTimer(Uint16 ucTimerIndex, Uint32 ulDelay); +void CStartSoftTimer(Uint16 ucTimerIndex); +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +Uint32 CGetSoftClock(void); +void CSOftWaitCountCancel(Uint16 Index); + +int main(void) +{ + CSetApuOperIndex(APU_OPER_IDX_BOOT); + + CInitSystem(); + + CInitOled(); + + CSetApuOperIndex(APU_OPER_IDX_INITIAL); + + for ( ; ; ) + { + CSoftTimerWorkProcess(); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == TIME_OVER) + { + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_POST); // Adc Ϸ POST + } + } + } + else if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + if (CPowerOnCheck() == 0U) + { + AdcOperValue.uiOffsetAdjustStart = 1U; // offset . + + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + } + } + else + { + if (GeneralOperValue.uiMaintenence == 0U) + { + // 尡 ־ . + //CApuOperProcedure(); + + CLedControlProcedure(); + + GPIO_ENGINE_HEATER_CS(GPIO_USER_MODE_1()); + GPIO_GLOW_PLUG_CS(GPIO_USER_MODE_1()); + GPIO_SOLENOID_CS(GPIO_USER_MODE_1()); + GPIO_FUEL_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_COOLANT_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_FAN1_CS(GPIO_USER_MODE_1()); + GPIO_FAN2_CS(GPIO_USER_MODE_1()); + } + else + { + CDebugModeProcedure(); + } + } + } +} + +void CSoftTimerWorkProcess(void) +{ + static Uint16 RefeshDelay = 0U; + + if (CIsStatusSoftTimer(TIMER_01MS) == SOFTTIMER_TIME_OVER) // Excute Per 1msec + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > APU_OPER_IDX_POST) // ADC Ϸ + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + if (GeneralOperValue.Maintenence.KeyTest == 0U) + { + // (:Ű׽Ʈ) ƴϸ Ű Է . + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (CIsStatusSoftTimer(TIMER_10MS) == SOFTTIMER_TIME_OVER) // Excute Per 10msec + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataA(); + CSendECanDataB(); + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) + { + if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + CDisplayPostFail(); + } + else + { + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + } + + if (CIsStatusSoftTimer(TIMER_100MS) == SOFTTIMER_TIME_OVER) // Excute Per 100msec + { + CReloadSoftTimer(TIMER_100MS); + + // ǻ ѹ̶ Ǿ ŸӾƿ üũ + if (CApuSystemAlarmCheck() == 0U) + { + // ߻ ŸӾƿ üũ ʴ´. + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer < COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : 0U; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : 0U; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : 0U; + } + } + if (CIsStatusSoftTimer(TIMER_1SEC) == SOFTTIMER_TIME_OVER) // Excute Per 1s + { + CReloadSoftTimer(TIMER_1SEC); + + if (OledOperValue.uiAlreadyAlarm == 1U) // ˶ ߻ 1е ٽ ˾ ϱ . + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_POPUP, (TIME_1SEC * 60UL)) == TIME_OVER) + { + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + else + { + CSOftWaitCountCancel(SOFTTIMER_WAIT_POPUP); + } + } +} + +void CSOftWaitCountCancel(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0f, 100.0f); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0U; // GPIO_COOLING_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U; // GPIO_FUEL_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U; // GPIO_COOLING_FAN1_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U; // GPIO_COOLING_FAN2_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U; // GPIO_GLOW_PLUG_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO6 = 0U; // GPIO_ENGINE_HEATER_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U; // GPIO_STOP_SOLENOID_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U; // GPIO_ECU_ON_OFF + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GPIO_POWER_HOLD(1); + + GPIO_CPU_LED_COM_FAULT_N(1); + GPIO_CPU_LED_COM_RUN_N(1); + GPIO_CPU_LED_COM_STA_N(1); + + EDIS; +} + +void CActiveChipSelect(Uint16 Active) +{ + if (Active == 0U) + { + // Ȳ CS OFFѴ. (0 - CS OFF, 1 - CS ON) + GPIO_ENGINE_HEATER_CS(0); + GPIO_GLOW_PLUG_CS(0); + GPIO_SOLENOID_CS(0); + GPIO_FUEL_PUMP_CS(0); + + GPIO_COOLANT_PUMP_CS(0); + GPIO_FAN1_CS(0); + GPIO_FAN2_CS(0); + } + else + { + //  ¿ EcuSignal ¸ Ȯϰ , ۷ο÷, ̵ַ, Ѵ. + // 0 - CS OFF, 1 - CS ON + GPIO_ENGINE_HEATER_CS(GPIO_ENGINE_HEATER()); + GPIO_GLOW_PLUG_CS(GPIO_GLOW_PLUG()); + GPIO_SOLENOID_CS(GPIO_SOLENOID()); + GPIO_FUEL_PUMP_CS(GPIO_FUEL_PUMP()); + + GPIO_COOLANT_PUMP_CS(1); + GPIO_FAN1_CS(1); + GPIO_FAN2_CS(1); + } +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +void CInitGeneralOperValue(void) +{ + (void) memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + (void) memset(&PowerOnCheckValue, 0x1FF, sizeof(CPowerOnCheckValue)); // Set All bit 1 + + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] = 0; +} + +void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = M_INT1 | M_INT9; + + EDIS; +} + +void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + CConfigSoftTimer(TIMER_1SEC, TIME_1SEC); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); + CStartSoftTimer(TIMER_1SEC); +} + +void CStartSoftTimer(Uint16 ucTimerIndex) +{ + if (SoftTimer[ucTimerIndex].iTimer != -1) + { + SoftTimer[ucTimerIndex].iStart = 1; + } +} + +void CInitSoftTimer(void) +{ + Uint16 i; + + (void) memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void) memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +Uint16 CPowerOnCheck(void) +{ + // Ȯ CAN ͷƮ ߻ , üũ + Uint16 retValue = (*(Uint16*)&PowerOnCheckValue) & 0x7FU; + + PowerOnCheckValue.EngineHeaterSensor = ((Adc_EngineHeater_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.GlowPlugSensor = ((Adc_GlowPlug_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.SolenoidSensor = ((Adc_Solenoid_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.FuelPumpSensor = ((Adc_FuelPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.CoolantPumpSensor = ((Adc_CoolantPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan1Sensor = ((Adc_Fan1_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan2Sensor = ((Adc_Fan2_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + + return retValue; // '0' +} diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ new file mode 100644 index 0000000..0df8e48 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ new file mode 100644 index 0000000..712b04b --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 b/.staticdata/.previous/20260113_090633/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 new file mode 100644 index 0000000..376775e --- /dev/null +++ b/.staticdata/.previous/20260113_090633/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 @@ -0,0 +1,220 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +typedef signed char int8; +typedef unsigned char Uint8; + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "DSP2833x_EPwm_defines.h" +#include "DSP2833x_I2c_defines.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (!GpioDataRegs.GPBDAT.bit.GPIO39) +#define GPIO_KEY_DOWN() (!GpioDataRegs.GPADAT.bit.GPIO31) +#define GPIO_KEY_ENTER() (!GpioDataRegs.GPADAT.bit.GPIO30) +#define GPIO_KEY_MENU() (!GpioDataRegs.GPADAT.bit.GPIO29) +#define GPIO_KEY_POWER() (!GpioDataRegs.GPCDAT.bit.GPIO67) +#define GPIO_KEY_START() (!GpioDataRegs.GPCDAT.bit.GPIO66) +#define GPIO_KEY_EMERGENCY() (!GpioDataRegs.GPCDAT.bit.GPIO64) + +// CS ȰǾ FUSE high ߻ (ips Ĩ Ǵ fuse) +#define GPIO_ENGINE_HEATER_FUSE() (GpioDataRegs.GPADAT.bit.GPIO6) +#define GPIO_GLOW_PLUG_FUSE() (GpioDataRegs.GPADAT.bit.GPIO5) +#define GPIO_SOLENOID_FUSE() (GpioDataRegs.GPADAT.bit.GPIO7) +#define GPIO_FUEL_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO2) +#define GPIO_COOLANT_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO1) +#define GPIO_FAN1_FUSE() (GpioDataRegs.GPADAT.bit.GPIO3) +#define GPIO_FAN2_FUSE() (GpioDataRegs.GPADAT.bit.GPIO4) + +#define GPIO_ECU_ON_OFF() (GpioDataRegs.GPADAT.bit.GPIO8) +#define GPIO_FUEL_PUMP() (GpioDataRegs.GPADAT.bit.GPIO9) +#define GPIO_GLOW_PLUG() (GpioDataRegs.GPADAT.bit.GPIO10) +#define GPIO_SOLENOID() (GpioDataRegs.GPADAT.bit.GPIO11) +#define GPIO_ENGINE_HEATER() (GpioDataRegs.GPADAT.bit.GPIO24) +#define GPIO_USER_MODE_1() (!GpioDataRegs.GPCDAT.bit.GPIO81) +#define GPIO_USER_MODE_2() (!GpioDataRegs.GPCDAT.bit.GPIO82) +#define GPIO_USER_MODE_3() (!GpioDataRegs.GPCDAT.bit.GPIO83) + +#define GPIO_ENGINE_HEATER_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO49) +#define GPIO_GLOW_PLUG_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO27) +#define GPIO_SOLENOID_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO48) +#define GPIO_FUEL_PUMP_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO26) +#define GPIO_COOLANT_PUMP_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO52) +#define GPIO_FAN1_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO50) +#define GPIO_FAN2_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO51) + +// ChipSelect Port +#define GPIO_ENGINE_HEATER_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO49 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1)); +#define GPIO_GLOW_PLUG_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO27 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO27 = 1)); +#define GPIO_SOLENOID_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO48 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1)); +#define GPIO_FUEL_PUMP_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO26 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO26 = 1)); +#define GPIO_COOLANT_PUMP_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO52 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1)); +#define GPIO_FAN1_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO50 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1)); +#define GPIO_FAN2_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO51 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1)); + +// Pannel LED Port +#define GPIO_CPU_LED_STOP(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO12 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO12 = 1)); +#define GPIO_CPU_LED_FAULT(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO14 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO14 = 1)); +#define GPIO_CPU_LED_OPERATION(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO13 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO13 = 1)); + +#define GPIO_OLED_RESET(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO37 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1)); + +#define GPIO_FAULT_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO55 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1)); +#define GPIO_EMERGENCY_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO56 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1)); +#define GPIO_STOP_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO57 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1)); +#define GPIO_START_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO58 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1)); + +#define GPIO_POWER_HOLD(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO65 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1)); +#define GPIO_CPU_LED_COM_FAULT_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO68 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1)); +#define GPIO_CPU_LED_COM_RUN_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO69 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1)); +#define GPIO_CPU_LED_COM_STA_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO70 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1)); + +/* Comment Description + * [!] : + * [?] : ʿ + * [*] : Ǻ + */ + +/* Firmware (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // ȣȯ ʴ ȭ , ȭ +#define FIRMWARE_VERSION_MINOR (0) // ȣȯ Ǹ鼭 ο , ǰų +#define FIRMWARE_VERSION_PATCH (5) // ȣȯ Ǹ鼭 , Ȱ ˾ Ҽ + +/* Version History + * [0.0.1] : DCU Ʈ + * [0.0.2] : DCU ߿ ž + * [0.0.3] : OLED XINTF(BUS) ̺ + * [0.0.4] : OLED ǥ ȭ + * [0.0.5] : CAN-B Ȯ + */ + +#define DEBUG_MENU_PASSWORD {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10U) +#define TIME_10MS (100U) +#define TIME_20MS (200U) +#define TIME_50MS (500U) +#define TIME_100MS (1000U) +#define TIME_500MS (5000U) +#define TIME_1SEC (10000U) + +// 0A ذ 450(0.33V), +/- 150 +#define SENSOR_OFFSET_REF 450 +#define SENSOR_TOLERANCE 150 +#define SENSOR_MIN_LIMIT (SENSOR_OFFSET_REF - SENSOR_TOLERANCE) // 300 +#define SENSOR_MAX_LIMIT (SENSOR_OFFSET_REF + SENSOR_TOLERANCE) // 600 + +#define TIME_OVER (1U) + +#define ABS(x) ((x) < 0 ? -(x) : (x)) + +enum +{ + TIMER_01MS = 0, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0, + SOFTTIMER_WAIT_POPUP, + SOFTTIMER_WAIT_APU_STOP, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef struct ClassPowerOnCheckValue +{ + Uint16 EngineHeaterSensor : 1; + Uint16 GlowPlugSensor : 1; + Uint16 SolenoidSensor : 1; + Uint16 FuelPumpSensor : 1; + Uint16 CoolantPumpSensor : 1; + Uint16 Fan1Sensor : 1; + Uint16 Fan2Sensor : 1; +} CPowerOnCheckValue; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiPassword[4]; + Uint16 uiAlarmOccured; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenence; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd : 4; + Uint16 rsvd_padding : 4; + } GcuCommand; + struct + { + Uint16 EngineStart : 1; + Uint16 EngineStop : 1; + Uint16 rsvd : 2; + Uint16 RpmSetPoint : 2; + Uint16 Override : 1; + Uint16 Emergency : 1; + } EcuCommand; + struct + { + Uint16 CarComputer : 1; + Uint16 Gcu : 1; + Uint16 Ecu : 1; + } Conection; + struct + { + Uint16 ManualCranking : 1; + Uint16 LampTest : 1; + Uint16 KeyTest : 1; + } Maintenence; +} CGeneralOperValue; + +Uint16 CSoftWaitCountProcedure(Uint16 ucIndex, Uint32 ulWaitTime); +void CActiveChipSelect(Uint16 Active); + +extern CGeneralOperValue GeneralOperValue; +extern CPowerOnCheckValue PowerOnCheckValue; + +#endif /* SOURCE_MAIN_H_ */ diff --git a/.staticdata/.previous/20260113_090633/K2DCU/fs/fs_hash_map.json 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\"cs_paren_asm=__asm\",\n\n \"cs_paren_asm=asm\",\n\n \"cs_define_macro_value=__signed_chars__;1\",\n\n \"cs_define_macro_value=__DATE__;\",\n\n \"cs_define_macro_value=__TIME__;\",\n\n \"cs_define_macro_value=__STDC__;1\",\n\n \"cs_define_macro_value=__STDC_VERSION__;199409L\",\n\n \"cs_define_macro_value=__edg_front_end__;1\",\n\n \"cs_define_macro_value=__EDG_VERSION__;404\",\n\n \"cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long\",\n\n \"cs_define_macro_value=__TI_COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__TMS320C2000__;1\",\n\n \"cs_define_macro_value=_TMS320C2000;1\",\n\n \"cs_define_macro_value=__TMS320C28XX__;1\",\n\n \"cs_define_macro_value=_TMS320C28XX;1\",\n\n \"cs_define_macro_value=__TMS320C28X__;1\",\n\n \"cs_define_macro_value=_TMS320C28X;1\",\n\n \"cs_define_macro_value=__TMS320C28XX_FPU32__;1\",\n\n \"cs_define_macro_value=__LARGE_MODEL__;1\",\n\n \"cs_define_macro_value=__SIZE_T_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__PTRDIFF_T_TYPE__;long\",\n\n \"cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int\",\n\n \"cs_define_macro_value=__little_endian__;1\",\n\n \"cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1\",\n\n \"cs_define_macro_value=__TI_WCHAR_T_BITS__;16\",\n\n \"cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0\",\n\n \"cs_define_macro_value=__TI_STRICT_FP_MODE__;1\",\n\n \"cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1\",\n\n \"cs_set_type_size=int;2\",\n\n \"cs_set_type_size=long;4\",\n\n \"cs_set_type_size=pointer;2\",\n\n \"cs_set_type_size=float;4\",\n\n \"cs_set_type_size=double;4\",\n\n \"cs_plain_char=signed\",\n\n \"cs_plain_bit_field=unsigned\",\n\n \"cs_for_init_scope=outer\",\n\n \"cs_using_std=disable\",\n\n \"gnu_version=40702\"\n\n ],\n\n \"include\": []\n\n }\n\n]", + "ci_ini": ";\n\n;\n\n; PA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[PA]\n\n; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.\n\n; default 값은 N 입니다.\n\nCLEAN_MODE=N\n\n;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.\n\n; default 값은 N 입니다.\n\nAUTO_ENCODING_UTF8=N\n\n\n\n; 프로젝트 DB 에 대한 초기화 쿼리\n\nINIT_QUERY=PRAGMA mmap_size=2147418112;\n\n\n\n; 람다 코드를 CFG에 포함할지 여부입니다. \n\n; 초기 값은 'N' 입니다.\n\nDISABLE_LAMBDA_CFG=N\n\n\n\n\n\n; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성\n\n; 초기 값은 'Y' 입니다.\n\nMAKE_UNIQUE_REFINED_DIR=Y\n\n;\n\n;-------------------------------------------------------------------------\n\n;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.\n\n;default 값은 Y 입니다.\n\n[CI]\n\nREINDEX_MODE=Y\n\n\n\n;\n\n;\n\n; DFA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[DFA]\n\nDFA_ENABLE=Y\n\nSCFG_OUT=N\n\nLIMIT_ITER=N\n\nRESULT_OUT=N\n\nITER_OUT=N\n\nTRANSFER_OUT=N\n\nFYCYC_ITER=40\n\n;\n\n;\n\n; Abstract Interpreter 설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"0\",\n\n \"last_capture_time\": \"2026-01-12T02:26:25.095Z\"\n\n}" +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/artifacts.zip b/.staticdata/.previous/20260113_090633/artifacts.zip new file mode 100644 index 0000000..4d258da Binary files /dev/null and b/.staticdata/.previous/20260113_090633/artifacts.zip differ diff --git a/.staticdata/.previous/20260113_090633/cstrace.json b/.staticdata/.previous/20260113_090633/cstrace.json new file mode 100644 index 0000000..2f745f4 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + } +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/error.json b/.staticdata/.previous/20260113_090633/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/.staticdata/.previous/20260113_090633/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/exclude_project.json b/.staticdata/.previous/20260113_090633/exclude_project.json new file mode 100644 index 0000000..1f5e5dd --- /dev/null +++ b/.staticdata/.previous/20260113_090633/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "K2APU_DCU", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/.staticdata/.previous/20260113_090633/preinclude/gnu_preinclude.h b/.staticdata/.previous/20260113_090633/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_c.h b/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_cpp.h b/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/.staticdata/.previous/20260113_090633/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/.spec b/.staticdata/.spec new file mode 100644 index 0000000..5ca53c3 --- /dev/null +++ b/.staticdata/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v005\.spec \ No newline at end of file diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/K2DCU/config/.inf b/.staticdata/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/.staticdata/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/.staticdata/K2DCU/config/ci.ini b/.staticdata/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/.staticdata/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/.staticdata/K2DCU/config/csa.exe b/.staticdata/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/.staticdata/K2DCU/config/csa.exe differ diff --git a/.staticdata/K2DCU/config/psionic.ini b/.staticdata/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/.staticdata/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/.staticdata/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 b/.staticdata/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 new file mode 100644 index 0000000..476e6ce --- /dev/null +++ b/.staticdata/K2DCU/fs/04be57c6b3426465d39a97a8ea69ad75 @@ -0,0 +1,180 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define PI2 (6.283185f) +#define ADC_FREQ (10000.0f) // 10kHz = 0.0001sec +#define ADC_LPF_COFF_TEMP (0.2f) +#define ADC_LPF_GAIN_TEMP (0.00012566f) //(PI2 * ADC_LPF_COFF_TEMP * (1.0f / ADC_FREQ)) +#define ADC_LPF_COFF (30.0f) +#define ADC_LPF_GAIN (0.01884955f) //(PI2 * ADC_LPF_COFF * (1.0f / ADC_FREQ)) + +#define LONG_KEY_TIME (1000UL) +#define KEY_POWER_MASK (0x00000001UL) + +#define COMM_TIME_OUT_COUNT (30U) + +enum +{ + IDX_ADC_ENGINE_HEATER_I = 0U, // 0 + IDX_ADC_GLOW_PLUG_I, // 1 + IDX_ADC_SOLENOID_I, // 2 + IDX_ADC_FUEL_PUMP_I, // 3 + IDX_ADC_COOLANT_PUMP_I, // 4 + IDX_ADC_FAN1_I, // 5 + IDX_ADC_FAN2_I, // 6 + IDX_ADC_MAX +}; + +typedef enum +{ + IDX_FAULT_CAR_COMM = 0U, // 0 + IDX_FAULT_GCU_COMM, // 1 + IDX_FAULT_ECU_COMM, // 2 + IDX_FAULT_RPM_ERR, // 3 + IDX_FAULT_ENGINE_HEAT_OC, // 4 + IDX_FAULT_GLOW_PLUG_OC, // 5 + IDX_FAULT_SOLENOID_OC, // 6 + IDX_FAULT_FUEL_PUMP_OC, // 7 + IDX_FAULT_COOLANT_PUMP_OC, // 8 + IDX_FAULT_FAN1_OC, // 9 + IDX_FAULT_FAN2_OC, // 10 + IDX_FAULT_ENGINE_HEAT_LINE_OPEN, // 11 + IDX_FAULT_GLOW_PLUG_LINE_OPEN, // 12 + IDX_FAULT_SOLENOID_LINE_OPEN, // 13 + IDX_FAULT_FUEL_PUMP_LINE_OPEN, // 14 + IDX_FAULT_COOLANT_PUMP_LINE_OPEN, // 15 + IDX_FAULT_FAN1_LINE_OPEN, // 16 + IDX_FAULT_FAN2_LINE_OPEN, // 17 + IDX_FAULT_MAX +} ALARM_TYPE; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fOffset; + float32 fLpfValue; + float32 fSampledValue; + float32 fGain; + float32 fSampledSum; + float32 fTempAdcOffset; + int16 iAdcValue; + Uint16 uiSamplingCount; +} CAdcCalcValue; + +typedef union ClassFaultBitValue +{ + Uint32 ulTotal; + struct + { + Uint16 CarCommTimeout : 1; + Uint16 GcuCommTimeout : 1; + Uint16 EcuCommTimeOut : 1; + Uint16 RpmError : 1; + Uint16 EngineHeatOverCurrent : 1; + Uint16 GlowPlugOverCurrent : 1; + Uint16 SolenoidOverCurrent : 1; + Uint16 FuelPumpOverCurrent : 1; + + Uint16 CoolantPumpOverCurrent : 1; + Uint16 Fan1OverCurrent : 1; + Uint16 Fan2OverCurrent : 1; + Uint16 EngineHeatOpen : 1; + Uint16 GlowPlugOpen : 1; + Uint16 SolenoidOpen : 1; + Uint16 FuelPumpOpen : 1; + Uint16 CoolantPumpOpen : 1; + + Uint16 Fan1Open : 1; + Uint16 Fan2Open : 1; + Uint16 rsvd_padding1 : 6; + + Uint16 rsvd_padding2 : 8; + } bit; +} CFaultBitValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // Ѱ + Uint16 uiWarning; // 0: , 1: ߻ + Uint16 uiDetectCount; // ī + Uint16 uiReleaseCount; // ī + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, + IDX_KEY_ARR_UP, + IDX_KEY_ARR_DOWN, + IDX_KEY_ENTER, + IDX_KEY_MENU, + IDX_KEY_ENG_START_STOP, + IDX_KEY_EMERGENCY, + IDX_KEY_MAX +} EKeyIndex; + +typedef struct ClassKeyHandler +{ + EKeyIndex eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef union ClassKeyList +{ + Uint16 uiTotal; + struct + { + Uint16 MainPower : 1; + Uint16 ArrowUp : 1; + Uint16 ArrowDown : 1; + Uint16 Enter : 1; + Uint16 Menu : 1; + Uint16 EngineStartStop : 1; + Uint16 Emergency : 1; + } bit; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; +extern CAdcOperValue AdcOperValue; +extern CFaultBitValue FaultBitValue; +extern CKeyOperValue KeyOperValue; + +#endif /* SOURCE_STATE_H_ */ diff --git a/.staticdata/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ b/.staticdata/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ new file mode 100644 index 0000000..9a06c75 --- /dev/null +++ b/.staticdata/K2DCU/fs/050d143fc3dd8b7275578ab2d4e9c342_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 b/.staticdata/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 new file mode 100644 index 0000000..8eb157e --- /dev/null +++ b/.staticdata/K2DCU/fs/0774309b5590755c2cd745aa7b91cb35 @@ -0,0 +1,1443 @@ +#include "main.h" +#include "CFont.h" + +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +volatile Uint16 CommandBus, DataBus; +const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; +int8 cNumBuffer[7] = { 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; +int8 *pNumBuffer = cNumBuffer; + +COledOperValue OledOperValue; + +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenence(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +Uint16 CStrLen(const int8 *s); +void CInitOledModule(void); +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +void CInitProgress(void); +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len); +void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CLcdWrite(Uint16 Data, Uint16 Command); +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +void CSetPageAddress(Uint16 Address); +void CSetColumnAddress(Uint16 x); +void COledWrite(Uint16 Data, Uint16 Command); +void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(eApuOperIdx idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); + +static const CPageHandler PageTable[OLED_PAGE_MAX] = +{ + { OLED_PAGE_APU1, CPageApu1 }, + { OLED_PAGE_APU2, CPageApu2 }, + { OLED_PAGE_MENU1, CPageMenu1 }, + { OLED_PAGE_MENU2, CPageMenu2 }, + { OLED_PAGE_TEMP, CPageTemp }, + { OLED_PAGE_SENSOR1, CPageSensor1 }, + { OLED_PAGE_SENSOR2, CPageSensor2 }, + { OLED_PAGE_SENSOR3, CPageSensor3 }, + { OLED_PAGE_SENSOR4, CPageSensor4 }, + { OLED_PAGE_WARNING1, CPageWarning1 }, + { OLED_PAGE_WARNING2, CPageWarning2 }, + { OLED_PAGE_FAULT1, CPageFault1 }, + { OLED_PAGE_FAULT2, CPageFault2 }, + { OLED_PAGE_FAULT3, CPageFault3 }, + { OLED_PAGE_FAULT4, CPageFault4 }, + { OLED_PAGE_FAULT5, CPageFault5 }, + { OLED_PAGE_FAULT6, CPageFault6 }, + { OLED_PAGE_RESET_ALARM, CPageAlarmReset }, + { OLED_PAGE_PASSWORD, CPagePassword }, + { OLED_PAGE_MAINTENENCE, CPageMaintenence }, + { OLED_PAGE_KEY_TEST, CPageKeyTest }, + { OLED_PAGE_SHUTDOWN, CPageShutdown } +}; + +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], title, CStrLen(title)); + CDrawStr(10U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0])); + + CDrawTitleBox(CStrLen((const int8*)OledOperValue.cStrBuff[OLED_ROW_0]) * 6U); + + if (pageNumStr != NULL) + { + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], pageNumStr, CStrLen(pageNumStr)); + CDrawStr(100U, OLED_LINE_TITLE, OledOperValue.cStrBuff[OLED_ROW_0], CStrLen(OledOperValue.cStrBuff[OLED_ROW_0])); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY = 0U; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; // Invalid row + } + + CStrncpy(OledOperValue.cStrBuff[row], label, CStrLen(label)); + + if (valueStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], valueStr, CStrLen(valueStr)); + } + + if (unitStr != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], unitStr, CStrLen(unitStr)); + } + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + CFloatToString(value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + CDecToString((int16)value, pNumBuffer, sizeof(cNumBuffer)); + CDrawPageLine(row, label, pNumBuffer, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + Uint16 drawY = 0U; + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + switch(row) + { + case OLED_ROW_1: drawY = OLED_LINE_1; break; + case OLED_ROW_2: drawY = OLED_LINE_2; break; + case OLED_ROW_3: drawY = OLED_LINE_3; break; + case OLED_ROW_4: drawY = OLED_LINE_4; break; + default: return; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawStr(0U, drawY, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageApu1(void) +{ + const int8 *cTemp = ""; + float32 fTemp; + + // TITLE + CDrawPageTitle("APU Status", "1/2"); + + // LINE 1 + fTemp = Rx220.GcuData.DcVoltage; + CDrawPageLineFloat(OLED_ROW_1, "DC Voltage ", fTemp, " V"); + + // LINE 2 + fTemp = Rx220.GcuData.DcCurrent; + CDrawPageLineFloat(OLED_ROW_2, "DC Current ", fTemp, " A"); + + // LINE 3 + fTemp = (Rx220.GcuData.DcVoltage * Rx220.GcuData.DcCurrent); + CDrawPageLineFloat(OLED_ROW_3, "Power ", fTemp, " kW"); + + // LINE 4 + cTemp = CGetApuStateString((eApuOperIdx)GeneralOperValue.uiApuState); + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_4], "Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[OLED_ROW_4], cTemp); + CStrncat(OledOperValue.cStrBuff[OLED_ROW_4], cTemp, CStrLen(cTemp)); + CDrawStr(0U, OLED_LINE_4, OledOperValue.cStrBuff[OLED_ROW_4], CStrLen(OledOperValue.cStrBuff[OLED_ROW_4])); +} + +static void CPageApu2(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngineActualRpm(); + CDrawPageLineInt(OLED_ROW_1, "ENG.RPM ", (int32)iTemp, " rpm"); + + // LINE 2 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt(OLED_ROW_2, "Coolant ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx320.EcuData.ActualTorque; + CDrawPageLineInt(OLED_ROW_3, "Torque ", (int32)iTemp, " %"); + + // LINE 4 + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, pNumBuffer); + CDrawPageLine(OLED_ROW_4, "ENG.Hour ", pNumBuffer, " Hr"); +} +static void CPageMenu1(void) +{ + // TITLE + CDrawPageTitle("Menu", "1/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "1. APU Status ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "2. Temperature ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "3. Sensor ", NULL, NULL); + + // LINE 4 + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_4, "4. Warning ", NULL, NULL); +} + +static void CPageMenu2(void) +{ + // TITLE + CDrawPageTitle("Menu", "2/2"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_1, "5. Fault ", NULL, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_2, "6. Alarm Reset ", NULL, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "7. Maintenence ", NULL, NULL); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = Rx221.GcuData.PcbTemperature - 40; + CDrawPageLineInt(OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " "); + + // LINE 2 + iTemp = Rx221.GcuData.FetTemperature - 40; + CDrawPageLineInt(OLED_ROW_2, "FET Temp. ", (int32)iTemp, " "); + + // LINE 3 + iTemp = Rx221.GcuData.GenTemperature1 - 40; + CDrawPageLineInt(OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " "); + + // LINE4 + iTemp = Rx221.GcuData.GenTemperature2 - 40; + CDrawPageLineInt(OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " "); +} +static void CPageSensor1(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "1/4"); + + // LINE 1 + fTemp = (Adc_EngineHeater_I.fLpfValue < 0.0f) ? 0.0f : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "EngineHeater", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_GlowPlug_I.fLpfValue < 0.0f) ? 0.0f : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "GlowPlug ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Solenoid_I.fLpfValue < 0.0f) ? 0.0f : Adc_Solenoid_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Solenoid ", fTemp, " A"); + + // LINE 4 + fTemp = (Adc_FuelPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_FuelPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_4, "FuelPump ", fTemp, " A"); +} + +static void CPageSensor2(void) +{ + float32 fTemp; + + // TITLE + CDrawPageTitle("Apu Sensor", "2/4"); + + // LINE 1 + fTemp = (Adc_CoolantPump_I.fLpfValue < 0.0f) ? 0.0f : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_1, "CoolantPump ", fTemp, " A"); + + // LINE 2 + fTemp = (Adc_Fan1_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan1_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_2, "Fan1 ", fTemp, " A"); + + // LINE 3 + fTemp = (Adc_Fan2_I.fLpfValue < 0.0f) ? 0.0f : Adc_Fan2_I.fLpfValue; + CDrawPageLineFloat(OLED_ROW_3, "Fan2 ", fTemp, " A"); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = Rx321.EcuData.BarometicPressure; + CDrawPageLineInt(OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = Rx321.EcuData.Fan1Speed; + CDrawPageLineInt(OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = Rx321.EcuData.Fan2Speed; + CDrawPageLineInt(OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = Rx321.EcuData.CoolantPumpSpeed; + CDrawPageLineInt(OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawPageTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = Rx220.GcuData.Rpm; + CDrawPageLineInt(OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "PCBOT:", Rx210.GcuWarning.bit.PcbOverHeat, "FETOT:", Rx210.GcuWarning.bit.FetOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "GEOT1:", Rx210.GcuWarning.bit.GenOverHeat1, "GEOT2:", Rx210.GcuWarning.bit.GenOverHeat2); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "ENGOT:", Rx310.EcuWarning.bit.EngineOverHeat, "L-OIL:", Rx310.EcuWarning.bit.LowOilLevel); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "INTOT:", Rx310.EcuWarning.bit.IntakeOverHeat, "INTLP:", Rx310.EcuWarning.bit.IntakeLoPressure); +} + +static void CPageWarning2(void) +{ + // TITLE + CDrawPageTitle("Warning", "2/2"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "ENGLT:", Rx310.EcuWarning.bit.EngineLoTemperature, "ENGSF:", Rx310.EcuWarning.bit.EngineSensor); + + // LINE 2 + CDrawPageLineStatus(OLED_ROW_2, "DEFAC:", Rx310.EcuWarning.bit.DefaltValueActive); +} +static void CPageFault1(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "1/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CARCT:", FaultBitValue.bit.CarCommTimeout, "GCUCT:", FaultBitValue.bit.GcuCommTimeout); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ECUCT:", FaultBitValue.bit.EcuCommTimeOut, "RPMER:", FaultBitValue.bit.RpmError); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "EHLOC:", FaultBitValue.bit.EngineHeatOverCurrent, "GPLOC:", FaultBitValue.bit.GlowPlugOverCurrent); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SOLOC:", FaultBitValue.bit.SolenoidOverCurrent, "FPLOC:", FaultBitValue.bit.FuelPumpOverCurrent); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "2/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "CPLOC:", FaultBitValue.bit.CoolantPumpOverCurrent, "F1LOC:", FaultBitValue.bit.Fan1OverCurrent); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "F2LOC:", FaultBitValue.bit.Fan2OverCurrent, "EHLLO:", FaultBitValue.bit.EngineHeatOpen); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GPLLO:", FaultBitValue.bit.GlowPlugOpen, "SOLLO:", FaultBitValue.bit.SolenoidOpen); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "FPLLO:", FaultBitValue.bit.FuelPumpOpen, "CPLLO:", FaultBitValue.bit.CoolantPumpOpen); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawPageTitle("Apu Fault", "3/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "F1LLO:", FaultBitValue.bit.Fan1Open, "F2LLO:", FaultBitValue.bit.Fan2Open); +} + +static void CPageFault4(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "4/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "HTRIP:", Rx210.GcuFault.bit.HwTrip, "HIGBT:", Rx210.GcuFault.bit.HwIgbt); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "HDCOV:", Rx210.GcuFault.bit.HwDc, "GNOCU:", Rx210.GcuFault.bit.GenOverCurrentU); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GNOCV:", Rx210.GcuFault.bit.GenOverCurrentV, "GNOCW:", Rx210.GcuFault.bit.GenOverCurrentW); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "SDCOV:", Rx210.GcuFault.bit.DcOverVoltage, "SDCOC:", Rx210.GcuFault.bit.DcOverCurrent); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawPageTitle("Gcu Fault", "5/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "SMOOC:", Rx210.GcuFault.bit.CrankningOverCurrent, "PCBOT:", Rx210.GcuFault.bit.PcbOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "FETOT:", Rx210.GcuFault.bit.FetOverHeat, "GW1OT:", Rx210.GcuFault.bit.GenTempOverHeat1); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "GW2OT:", Rx210.GcuFault.bit.GenTempOverHeat2, "GENOS:", Rx210.GcuFault.bit.GenOverSpeed); + + // LINE 4 + CDrawTwoStatusLine(OLED_ROW_4, "RSICF:", Rx210.GcuFault.bit.ResolverIC, "RSPRT:", Rx210.GcuFault.bit.ResolverParity); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawPageTitle("Ecu Fault", "6/6"); + + // LINE 1 + CDrawTwoStatusLine(OLED_ROW_1, "OILMS:", Rx310.EcuFault.bit.OilPressureMissing, "INTOT:", Rx310.EcuFault.bit.IntakeOverHeat); + + // LINE 2 + CDrawTwoStatusLine(OLED_ROW_2, "ENGOT:", Rx310.EcuFault.bit.EngineOverHeat, "ACTUA:", Rx310.EcuFault.bit.Actuator); + + // LINE 3 + CDrawTwoStatusLine(OLED_ROW_3, "RPMSG:", Rx310.EcuFault.bit.RpmSignal, "ENGSF:", Rx310.EcuFault.bit.EngineStartFail); +} +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 0U) ? (const int8*)"P" : (const int8*)"F"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 2U); + CStrncat(OledOperValue.cStrBuff[row], l3, 13U); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + + switch(row) + { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine(OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + int16 iTemp[2] = { 0, '\0' }; + + // TITLE + CDrawPageTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case OLED_PASS_DIGIT_1: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case OLED_PASS_DIGIT_2: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case OLED_PASS_DIGIT_3: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + iTemp[0] = GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] + '0'; + cTemp = (int8*)iTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CTextAlign(OledOperValue.cAlignBuffer, maskBuffer); + CDrawStr(0U, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} +static void CPageMaintenence(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawPageTitle("Maintenence", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenence.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(OLED_ROW_3, "Switch Test ", NULL, NULL); +} +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + Uint16 y = 0U; + switch(row) { + case OLED_ROW_2: y = OLED_LINE_2; break; + case OLED_ROW_3: y = OLED_LINE_3; break; + case OLED_ROW_4: y = OLED_LINE_4; break; + default: break; + } + CDrawStr(0U, y, OledOperValue.cStrBuff[row], CStrLen(OledOperValue.cStrBuff[row])); +} +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine(OLED_LINE_TITLE + 2U, "Key input Test"); + + // TITLE2 + CDrawCenteredLine(OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + // " Stat:" + Status + // This is special indentation. + // I can reuse CDrawKeyStatusLine if I pass proper label. + // " Stat:" is 19 chars. + CDrawKeyStatusLine(OLED_ROW_2, " Stat:", GPIO_KEY_START(), NULL, 0, NULL, 0); + + // LINE 3 + // " Up:" + s + " " + "Entr:" + s + " " + "Powr:" + s + CDrawKeyStatusLine(OLED_ROW_3, " Up:", GPIO_KEY_UP(), "Entr:", GPIO_KEY_ENTER(), "Powr:", GPIO_KEY_POWER()); + + // LINE 4 + // "Down:" + s + " " + "Menu:" + s + " " + "Emgc:" + s + CDrawKeyStatusLine(OLED_ROW_4, "Down:", GPIO_KEY_DOWN(), "Menu:", GPIO_KEY_MENU(), "Emgc:", GPIO_KEY_EMERGENCY()); +} +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine(OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine(OLED_LINE_2, "Shutting down..."); +} +void CSetPage(Uint16 PageNum) +{ + int16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0; i < OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler + } + } +} + +void COledBufferReset(void) +{ + (void) memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void) memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // + CDrawLine(8U, 10U, 10U, 12U); // 𼭸 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // Ʒ + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 𼭸 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // + + if (OledOperValue.uiPageNum != OLED_PAGE_PASSWORD) + { + // ŸƲ ڽ + CDrawLine(98U, 0U, 98U, 9U); // + CDrawLine(98U, 10U, 100U, 12U); // 𼭸 + CDrawLine(101U, 12U, 118U, 12U); // Ʒ + CDrawLine(119U, 12U, 121U, 10U); // 𼭸 + CDrawLine(121U, 0U, 121U, 9U); // + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = y / 8; j < (y + height) / 8; j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + int16 i; + + CInitOledModule(); + + for(uiPageNum = 0; uiPageNum < 8; uiPageNum++) + { + COledWrite((Uint16)(0xB0 | uiPageNum), MODE_COMMAND); + + for(i = 0; i < OLED_WIDTH; i++) + { + COledWrite(0x00, MODE_DATA); + } + } + + CInitProgress(); +} + +void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, OLED_LINE_TITLE, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void) memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, OLED_LINE_2, OledOperValue.cAlignBuffer, CStrLen(OledOperValue.cAlignBuffer)); +} + +void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = (TXT_MAX_LEN - 1) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0; + i = 0; + + while (str[i] != '\0') // str int8* ̹Ƿ, int8 Ÿ (0) ã + { + uiLen++; + i++; + } + + if (uiLen >= TXT_MAX_LEN) + { + uiIndent = 0; + } + else + { + uiIndent = ((TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < TXT_MAX_LEN)) // ҽ Һ + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = (int8)' '; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = 0; +} + +void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // + CDrawLine(x, (y + 1U), x, (y + h)); // + CDrawLine(x, (y + h), w, (y + h)); // Ʒ + CDrawLine(w, (y + 1U), w, (y + h - 1U)); // +} + +void CSetDrawRegion(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + if (x2 > OledOperValue.Point.X2) + { + OledOperValue.Point.X2 = x2; + } + if (y2 > OledOperValue.Point.Y2) + { + OledOperValue.Point.Y2 = y2; + } +} + +void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 tmp = 0, x = 0, y = 0, dx = 0, dy = 0, swapxy = 0; + Uint16 loop_end = 0; + Uint16 minor_limit = 0; // (y) Ѱ谪 + int16 err = 0, ystep = 0; + + dx = x2 - x1; + + dy = (y1 > y2) ? (y1 - y2) : (y2 - y1); + + if (dy > dx) + { + swapxy = 1; + tmp = dx; dx = dy; dy = tmp; + tmp = x1; x1 = y1; y1 = tmp; + tmp = x2; x2 = y2; y2 = tmp; + + loop_end = OLED_HEIGHT - 1; + minor_limit = OLED_WIDTH - 1; + } + else + { + loop_end = OLED_WIDTH - 1; + minor_limit = OLED_HEIGHT - 1; + } + + if (x2 > loop_end) + { + x2 = loop_end; + } + + err = dx >> 1; + ystep = (y2 > y1) ? 1 : -1; + y = y1; + + if (swapxy == 0) + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } + else + { + for(x = x1; x <= x2; x++) + { + if (y > minor_limit) break; + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err -= (Uint16) dy; + if ( err < 0 ) + { + y += (Uint16) ystep; + err += (Uint16) dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage = y / 8U; + Uint16 uiOffset = y % 8U; + + if (x >= OLED_WIDTH || y >= OLED_HEIGHT) + { + x = OLED_WIDTH; + y = OLED_HEIGHT; + } + else + { + if (x < OLED_WIDTH) + { + if (Color) + { + OledOperValue.uiBuff[x][uiPage] |= (0x01U << uiOffset); + } + else + { + OledOperValue.uiBuff[x][uiPage] &= (Uint16) ~(0x01U << uiOffset); + } + } + } +} + +void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0), MODE_COMMAND); +} + +void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0F) | 0x10; + LowAddress = x & 0x0F; + + COledWrite(LowAddress, MODE_COMMAND); + COledWrite(HighAddress, MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 1; + XintfRegs.XTIMING6.bit.XWRACTIVE = 13; + XintfRegs.XTIMING6.bit.XWRTRAIL = 1; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 1; + XintfRegs.XTIMING6.bit.XRDACTIVE = 13; + XintfRegs.XTIMING6.bit.XRDTRAIL = 1; + + XintfRegs.XTIMING6.bit.X2TIMING = 1; + XintfRegs.XTIMING6.bit.USEREADY = 1; + XintfRegs.XTIMING6.bit.READYMODE = 1; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +void CDrawStr(Uint16 x, Uint16 y, int8* str, Uint16 len) +{ + Uint16 i; + + if ((len > 0U) && (len < TXT_MAX_LEN)) // ҽ Һ + { + for(i = 0; i < len; i++) + { + if (str[i] & 0x80) + { + CDrawChar(x, y, (Uint16)((str[i] << 8) | str[i + 1]), TXT_TYPE_ETC); + i++; + x += TXT_ENG_WIDTH * 2U; + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + } + } +} + +void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0) // Eng Char + { + uiCharWidth = TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = TXT_ENG_WIDTH * 2U; + ch = (ch == 0xA1C9U) ? 0x00U : ch; + pFontData = EtcFontTable[ch]; + } + + CSetDrawRegion(x, y, (x + TXT_ENG_WIDTH), (y + TXT_ENG_HEIGHT)); + + for(j = 0; j < TXT_ENG_HEIGHT; j++) + { + for(i = 0; i < uiCharWidth; i++) + { + if (pFontData[uiFontIndex / 8] & uiBitMask[uiFontIndex % 8]) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +void CInitOledModule(void) +{ + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + GPIO_OLED_RESET(0U); + DELAY_US(2000L); + GPIO_OLED_RESET(1U); + DELAY_US(2000L); + + COledWrite(0xFD, MODE_COMMAND); // Command Lock + COledWrite(0x12, MODE_COMMAND); // + COledWrite(0xAE, MODE_COMMAND); // oled off + COledWrite(0xA1, MODE_COMMAND); // 1U segment column address high to low + + COledWrite(0xC8, MODE_COMMAND); // COM output scan from high to low + + COledWrite(0x81, MODE_COMMAND); // 1U contrast + COledWrite(0xFF, MODE_COMMAND); + + COledWrite(0xAF, MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = OLED_LOAD_PROGRESS_X + 1; +} + +void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +void CInitOledStructure(void) +{ + (void) memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void) memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +Uint16 CStrLen(const int8 *s) +{ + // ּҸ մϴ. + const int8 *p = s; + + // Ͱ ('\0', ASCII 0) Ű ͸ ŵϴ. + // ڿ ӵ ޸ Ǿ ֽϴ. + while (*p != '\0') + { + p++; + } + + // ּ( ) ּ ̰ ڿ ̰ ˴ϴ. + return (Uint16)(p - s); +} + +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + + for (i = 0; i < Size; i++) + { + pTarget[i] = pSource[i]; + } + pTarget[i] = '\0'; +} + +void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + + uiTargetSize = (Uint16)CStrLen(pTarget); + + if ((uiTargetSize + Size) < TXT_MAX_LEN) + { + for (i = 0; i < Size; i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = '\0'; + } +} + +void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U, uiSignLocate = 0U, i; + Uint16 x, y; + int32 lData = (int32) Data * 10; + int8 cTmp[5] = { 0x00, 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + if (lData < 0) + { + // ǥ ڰ + uiSign = 1U; + lData = -lData; + } + + while (lData > 0U) + { + cTmp[x++] = (lData % 10) + '0'; + lData /= 10U; + } + + if (x == 0) // ġ 0 . + { + y = 3U; + Array[y++] = '0'; + } + else + { + y = 5 - x; // Ǵ . + x = x - 1; // ε . + + if (y < 1) + { + uiSignLocate = 0U; + } + else + { + if ((y >= 1) && (y <= 5)) + { + uiSignLocate = (Uint16)(y - 1); // '-' ȣ ǥ ڸ + } + } + + if (uiSign == 1U) // '-' ȣ ǥ ġ ϱ . + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U)) + { + Array[uiSignLocate] = '-'; + } + } + else + { + Array[uiSignLocate] = ' '; + } + + while (x > 0) + { + Array[y++] = cTmp[x--]; + } + } + Array[y] = '\0'; // End of string. +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 x = 0U, y = 0U, i; + int16 iTemp = (int16)(Data * 10); + int8 cTmp[4] = { 0x00, 0x00, 0x00, 0x00 }; + + for (i = 0; i < ArrayLen; i++) + { + Array[i] = ' '; + } + + while (iTemp > 0U) + { + cTmp[x++] = (iTemp % 10) + '0'; + iTemp /= 10U; + } + + if (x == 0U) // ġ 0.0 . + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = '0'; + } + else + { + if (x == 1U) + { + y = 3U; + Array[y++] = '0'; + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + else + { + y = 5U - x; // Ǵ . + x = x - 1U; // ε . + + while (x > 0U) + { + Array[y++] = cTmp[x--]; + if (x == 0U) + { + Array[y++] = '.'; + Array[y++] = cTmp[0]; + } + } + } + } + Array[y] = '\0'; // End of string. +} + +void CInitializePage(void) +{ + if (AdcOperValue.uiOffsetAdjustStart == 0U) + { + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < OLED_LOAD_PROGRESS_W - 3) // -3 α׷ ¿ 1ȼ . + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(OLED_ROW_2, "EHT:", PowerOnCheckValue.EngineHeaterSensor, "GPL:", PowerOnCheckValue.GlowPlugSensor, "SOL:", PowerOnCheckValue.SolenoidSensor); + + // LINE 3 + CDrawPostStatusLine(OLED_ROW_3, "FUP:", PowerOnCheckValue.FuelPumpSensor, "CLP:", PowerOnCheckValue.CoolantPumpSensor, "FN1:", PowerOnCheckValue.Fan1Sensor); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(OLED_ROW_4, "FN2:", PowerOnCheckValue.Fan2Sensor, NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +void CReversString(int8 *str, int16 length) +{ + Uint16 i = 0U; + Uint16 end = length - 1U; + int8 temp; + + while (i < end) + { + temp = str[i]; + str[i] = str[end]; + str[end] = temp; + i++; + end--; + } +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = num; // Է¹ (: 1234567 -> "12345.67") + + // 1. Ҽ ° ڸ (100 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 2. Ҽ ù° ڸ (10 1) + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + + // 3. Ҽ + str[i++] = '.'; + + // 4. ȯ + // Է 0̾ ּ "0" do-while + do + { + str[i++] = (temp % 10) + '0'; + temp = temp / 10; + } + while (temp != 0); + + // 5. ä (ڸ ) + // 5ڸ + 1ڸ + Ҽ2ڸ = 8ڸ + while (i < 8U) + { + str[i++] = ' '; + } + + str[i] = '\0'; // ڿ ˸ + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(eApuOperIdx idx) +{ + // ε 1:1 ĪǴ ڿ 迭 static Ͽ Լ ȣ 迭 ٽ ʵ + static const int8* strTable[] = + { + "BOOT", // 0: APU_OPER_IDX_BOOT + "INIT", // 1: APU_OPER_IDX_INITIAL + "POST", // 2: APU_OPER_IDX_POST + "EMERGENCY", // 3: APU_OPER_IDX_EMERGENCY + "STANDBY", // 4: APU_OPER_IDX_STANDBY + "START_CHECK", // 5: APU_OPER_IDX_START_CHECK + "PREHEAT", // 6: APU_OPER_IDX_ACTIVE_ENG_HEAT + "CRANKING", // 7: APU_OPER_IDX_CRANKING + "WARM_UP", // 8: APU_OPER_IDX_ENG_WARMING_UP + "CHECK_OPER", // 9: APU_OPER_IDX_CHECK_OPERATION + "GENERATING", // 10: APU_OPER_IDX_SET_GCU_GEN_START + "STABLED", // 11: APU_OPER_IDX_ENG_START_DONE + "STOP", // 12: APU_OPER_IDX_ENG_STOP_NORMAL + "COOLDOWN" // 13: APU_OPER_IDX_ENG_STOP_COOLDOWN + }; + + return strTable[idx]; +} diff --git a/.staticdata/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ b/.staticdata/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ new file mode 100644 index 0000000..95dd823 --- /dev/null +++ b/.staticdata/K2DCU/fs/097c5d30e5c4f5179d798d6384e5d533_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ b/.staticdata/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ new file mode 100644 index 0000000..be86c38 --- /dev/null +++ b/.staticdata/K2DCU/fs/099f1495609d00be6b7bdd755088b145_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ b/.staticdata/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ new file mode 100644 index 0000000..e2d1e35 --- /dev/null +++ b/.staticdata/K2DCU/fs/10379b93480c99dabdc6f3c5212aa3a5_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ b/.staticdata/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ new file mode 100644 index 0000000..545526b --- /dev/null +++ b/.staticdata/K2DCU/fs/137d3ee8b66473080b3864ed4dc8756b_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/.staticdata/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ b/.staticdata/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ new file mode 100644 index 0000000..cfe478f --- /dev/null +++ b/.staticdata/K2DCU/fs/1932874082b3682e20a28c3a31f9536f_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ b/.staticdata/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ new file mode 100644 index 0000000..4714194 --- /dev/null +++ b/.staticdata/K2DCU/fs/4700c78dff5138e13229ae565ce380d0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ b/.staticdata/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ new file mode 100644 index 0000000..b5a7be5 --- /dev/null +++ b/.staticdata/K2DCU/fs/5eca537fc54f1f67c31755b83e2d05af_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void InitXintf(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 b/.staticdata/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 new file mode 100644 index 0000000..a9a4b68 --- /dev/null +++ b/.staticdata/K2DCU/fs/66eb412efa1ddcd9688b0b9090ae3484 @@ -0,0 +1,1143 @@ +#include "main.h" + +CCommCheck CommCheck; + +// Tx +static CTx100 Tx100; +static CTx101 Tx101; +CTx102 Tx102; +CTx103 Tx103; +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx130 Tx130; +static CTx131 Tx131; +static CTx132 Tx132; + +// Rx - GCU +static CRx200 Rx200; +static CRx201 Rx201; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +static CRx300 Rx300; +static CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); + +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // ѹ̶ ŵǾٸ ش ġ Ǿٰ Ǵ. + CommCheck.CarComputer = 0U; // ۽ ŸӾƿ īƮ Ŭ + /* + if (ECanShadow.CANRMP.bit.RMP15 == 1U) + { + ECanShadow.CANRMP.bit.RMP15 = 1U; + } + + if (ECanShadow.CANRMP.bit.RMP16 == 1U) + { + ECanShadow.CANRMP.bit.RMP16 = 1U; + } +*/ + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +void CSendECanDataA(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + Uint16 uiTemp; + + // 10ms + ECanaMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.ApuData.PlayState & 0x7U; + + uiTemp = (Tx101.ApuData.AlarmOccured << 0U) | (Tx101.ApuData.Emergency << 1U) | (Tx101.ApuData.PowerSwitch << 2U); + ECanaMboxes.MBOX1.MDL.byte.BYTE1 = uiTemp; + ECanaMboxes.MBOX1.MDL.byte.BYTE2 = Tx101.ApuData.GcuPlayState & 0x7U; + + uiTemp = (Tx101.ApuData.GcuAlarmOccured << 0U) | (Tx101.ApuData.GcuShutdown << 1U); + ECanaMboxes.MBOX1.MDL.byte.BYTE3 = uiTemp; + + uiTemp = (Tx101.ApuData.EcuAlarmOccured << 0U) | + ((Tx101.ApuData.EcuPlayState & 0x3FU) << 1U) | + (Tx101.ApuData.OverrideActive << 4U) | + (Tx101.ApuData.GlowPlugActive << 5U) | + (Tx101.ApuData.HeaterActive << 6U) | + (Tx101.ApuData.OilPressureMissing); + ECanaMboxes.MBOX1.MDH.byte.BYTE4 = uiTemp; + + ECanaMboxes.MBOX1.MDH.byte.BYTE5 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE6 = 0; + ECanaMboxes.MBOX1.MDH.byte.BYTE7 = 0; + + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanaRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanaRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanaRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; + ECanaRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanaMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX2.MDH.all = 0x00000000U; + ECanaMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanaMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX3.MDH.all = 0x00000000U; + ECanaMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanaMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX4.MDH.all = 0x00000000U; + ECanaMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanaMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX6.MDH.all = 0x00000000U; + ECanaMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanaMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX7.MDH.all = 0x00000000U; + ECanaMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanaMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX8.MDH.all = 0x00000000U; + ECanaMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanaMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX9.MDH.all = 0x00000000U; + ECanaMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanaMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX28.MDH.all = 0x00000000U; + ECanaMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanaMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX29.MDH.all = 0x00000000U; + ECanaMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanaMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX30.MDH.all = 0x00000000U; + ECanaMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanaRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanaRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.GcuData.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.GcuData.VersionMajor = (Uint8)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.GcuData.VersionMinor = (Uint8)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.GcuData.VersionPatch = (Uint8)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.GcuData.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + + Rx201.GcuData.AlarmOccured = (Uint16)((uiMBOXMdl >> 16U) & 0x1U); + Rx201.GcuData.Shutdown = (Uint16)((uiMBOXMdl >> 17U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX17 - 210h (Ʈ ʵ ) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx210.GcuWarning.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat1 = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx210.GcuWarning.bit.GenOverHeat2 = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + + Rx210.GcuFault.bit.HwTrip = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx210.GcuFault.bit.HwIgbt = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx210.GcuFault.bit.HwDc = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentU = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentV = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx210.GcuFault.bit.GenOverCurrentW = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + Rx210.GcuFault.bit.DcOverVoltage = (Uint16)((uiMBOXMdl >> 14U) & 0x1U); + Rx210.GcuFault.bit.DcOverCurrent = (Uint16)((uiMBOXMdl >> 15U) & 0x1U); + + Rx210.GcuFault.bit.CrankningOverCurrent = (Uint16)((uiMBOXMdl >> 0U) & 0x1U); + Rx210.GcuFault.bit.PcbOverHeat = (Uint16)((uiMBOXMdl >> 1U) & 0x1U); + Rx210.GcuFault.bit.FetOverHeat = (Uint16)((uiMBOXMdl >> 2U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat1 = (Uint16)((uiMBOXMdl >> 3U) & 0x1U); + Rx210.GcuFault.bit.GenTempOverHeat2 = (Uint16)((uiMBOXMdl >> 4U) & 0x1U); + Rx210.GcuFault.bit.GenOverSpeed = (Uint16)((uiMBOXMdl >> 5U) & 0x1U); + Rx210.GcuFault.bit.ResolverIC = (Uint16)((uiMBOXMdl >> 6U) & 0x1U); + Rx210.GcuFault.bit.ResolverParity = (Uint16)((uiMBOXMdl >> 7U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.GcuData.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.GcuData.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // MDH Reverse: Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.GcuData.Rpm = uiRpmL | (uiRpmH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.GcuData.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.GcuData.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GcuData.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GcuData.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.EcuData.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.EcuData.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.EcuData.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.OperationInfo.AlarmOccured = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx301.OperationInfo.PlayState = (Uint16)((uiMBOXMdl >> 25U) & 0x7U); // (24 + 1) + Rx301.OperationInfo.OverrideActive = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); // (24 + 4) + Rx301.OperationInfo.GlowPlugActive = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx301.OperationInfo.HeaterActive = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx301.OperationInfo.OilPressureMissing = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx310.EcuWarning.bit.reserved = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx310.EcuWarning.bit.LowOilLevel = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx310.EcuWarning.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx310.EcuWarning.bit.IntakeLoPressure = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx310.EcuWarning.bit.EngineLoTemperature = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx310.EcuWarning.bit.EngineSensor = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx310.EcuWarning.bit.DefaltValueActive = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + + // [Reverse] Byte 2 -> >> 8 + Rx310.EcuFault.bit.OilPressureMissing = (Uint16)((uiMBOXMdl >> 8U) & 0x1U); + Rx310.EcuFault.bit.IntakeOverHeat = (Uint16)((uiMBOXMdl >> 9U) & 0x1U); + Rx310.EcuFault.bit.EngineOverHeat = (Uint16)((uiMBOXMdl >> 10U) & 0x1U); + Rx310.EcuFault.bit.Actuator = (Uint16)((uiMBOXMdl >> 11U) & 0x1U); + Rx310.EcuFault.bit.RpmSignal = (Uint16)((uiMBOXMdl >> 12U) & 0x1U); + Rx310.EcuFault.bit.EngineStartFail = (Uint16)((uiMBOXMdl >> 13U) & 0x1U); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.EcuData.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.EcuData.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.EcuData.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.EcuData.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.EcuData.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.EcuData.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.EcuData.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.EcuData.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.EcuData.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.EcuData.BarometicPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.EcuData.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.EcuData.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.EcuData.TotalOperTimeL) | ((Uint32)Rx322.EcuData.TotalOperTimeH << 16U); + GeneralOperValue.ulTotalOperationHour = (GeneralOperValue.ulTotalOperationHour > 1000000UL) ? 1000000UL : GeneralOperValue.ulTotalOperationHour; + } + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiSendPer100ms = 0U; + + // 10ms + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = 0x1; + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = 0x2; + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x3; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x4; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x5; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = 0x6; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = 0x7; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = 0x8; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + // 100ms + if(uiSendPer100ms == 0U) + { + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS0 = 1U; // 100h + ECanShadow.CANTRS.bit.TRS4 = 1U; // 110h + ECanShadow.CANTRS.bit.TRS5 = 1U; // 120h + ECanShadow.CANTRS.bit.TRS6 = 1U; // 121h + ECanShadow.CANTRS.bit.TRS7 = 1U; // 130h + ECanShadow.CANTRS.bit.TRS8 = 1U; // 131h + ECanShadow.CANTRS.bit.TRS9 = 1U; // 132h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA0 = 1U; // 100h + ECanShadow.CANTA.bit.TA4 = 1U; // 110h + ECanShadow.CANTA.bit.TA5 = 1U; // 120h + ECanShadow.CANTA.bit.TA6 = 1U; // 121h + ECanShadow.CANTA.bit.TA7 = 1U; // 130h + ECanShadow.CANTA.bit.TA8 = 1U; // 131h + ECanShadow.CANTA.bit.TA9 = 1U; // 132h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + } + uiSendPer100ms = (uiSendPer100ms + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID EAa ϨI '0' - 11bit ID ce + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x130U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x131U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x132U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; + + // Transe, Receive aA, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.bit.MD0 = 0U; + ECanShadow.CANMD.bit.MD1 = 0U; + ECanShadow.CANMD.bit.MD2 = 0U; + ECanShadow.CANMD.bit.MD3 = 0U; + ECanShadow.CANMD.bit.MD4 = 0U; + ECanShadow.CANMD.bit.MD5 = 0U; + ECanShadow.CANMD.bit.MD6 = 0U; + ECanShadow.CANMD.bit.MD7 = 0U; + ECanShadow.CANMD.bit.MD8 = 0U; + ECanShadow.CANMD.bit.MD9 = 0U; + ECanShadow.CANMD.bit.MD15 = 1U; + ECanShadow.CANMD.bit.MD16 = 1U; + ECanShadow.CANMD.bit.MD17 = 1U; + ECanShadow.CANMD.bit.MD18 = 1U; + ECanShadow.CANMD.bit.MD19 = 1U; + ECanShadow.CANMD.bit.MD25 = 1U; + ECanShadow.CANMD.bit.MD26 = 1U; + ECanShadow.CANMD.bit.MD27 = 1U; + ECanShadow.CANMD.bit.MD28 = 1U; + ECanShadow.CANMD.bit.MD29 = 1U; + ECanShadow.CANMD.bit.MD30 = 1U; + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.bit.ME0 = 1U; + ECanShadow.CANME.bit.ME1 = 1U; + ECanShadow.CANME.bit.ME2 = 1U; + ECanShadow.CANME.bit.ME3 = 1U; + ECanShadow.CANME.bit.ME4 = 1U; + ECanShadow.CANME.bit.ME5 = 1U; + ECanShadow.CANME.bit.ME6 = 1U; + ECanShadow.CANME.bit.ME7 = 1U; + ECanShadow.CANME.bit.ME8 = 1U; + ECanShadow.CANME.bit.ME9 = 1U; + ECanShadow.CANME.bit.ME15 = 1U; + ECanShadow.CANME.bit.ME16 = 1U; + ECanShadow.CANME.bit.ME17 = 1U; + ECanShadow.CANME.bit.ME18 = 1U; + ECanShadow.CANME.bit.ME19 = 1U; + ECanShadow.CANME.bit.ME25 = 1U; + ECanShadow.CANME.bit.ME26 = 1U; + ECanShadow.CANME.bit.ME27 = 1U; + ECanShadow.CANME.bit.ME28 = 1U; + ECanShadow.CANME.bit.ME29 = 1U; + ECanShadow.CANME.bit.ME30 = 1U; + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode A + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void) memset(&Tx100, 0, sizeof(CTx100)); + (void) memset(&Tx101, 0, sizeof(CTx101)); + (void) memset(&Tx102, 0, sizeof(CTx102)); + (void) memset(&Tx103, 0, sizeof(CTx103)); + (void) memset(&Tx110, 0, sizeof(CTx110)); + (void) memset(&Tx120, 0, sizeof(CTx120)); + (void) memset(&Tx121, 0, sizeof(CTx121)); + (void) memset(&Tx130, 0, sizeof(CTx130)); + (void) memset(&Tx131, 0, sizeof(CTx131)); + (void) memset(&Tx132, 0, sizeof(CTx132)); + + // Rx - GCU + (void) memset(&Rx200, 0, sizeof(CRx200)); + (void) memset(&Rx201, 0, sizeof(CRx201)); + (void) memset(&Rx210, 0, sizeof(CRx210)); + (void) memset(&Rx220, 0, sizeof(CRx220)); + (void) memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void) memset(&Rx300, 0, sizeof(CRx300)); + (void) memset(&Rx301, 0, sizeof(CRx301)); + (void) memset(&Rx310, 0, sizeof(CRx310)); + (void) memset(&Rx320, 0, sizeof(CRx320)); + (void) memset(&Rx321, 0, sizeof(CRx321)); + (void) memset(&Rx322, 0, sizeof(CRx322)); +} diff --git a/.staticdata/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 b/.staticdata/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 new file mode 100644 index 0000000..e8d04e5 --- /dev/null +++ b/.staticdata/K2DCU/fs/86bbc0e43411eb6e023b191bbd4ec467 @@ -0,0 +1,434 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + struct + { + Uint16 Heartbit : 16; + Uint16 : 8; + Uint16 : 8; + Uint16 : 8; + Uint16 VersionMajor : 8; + Uint16 VersionMinor : 8; + Uint16 VersionPatch : 8; + } ApuData; +} CTx100; + +typedef struct ClassTx101 +{ + struct + { + /* byte 0 */ + Uint16 PlayState : 3; + Uint16 : 5; + + /* byte 1 */ + Uint16 AlarmOccured : 1; + Uint16 Emergency : 1; + Uint16 PowerSwitch : 1; + Uint16 : 5; + + /* byte 2 */ + Uint16 GcuPlayState : 3; + Uint16 : 5; + + /* byte 3 */ + Uint16 GcuAlarmOccured : 1; + Uint16 GcuShutdown : 1; + Uint16 : 6; + + /* byte 4 */ + Uint16 EcuAlarmOccured : 1; + Uint16 EcuPlayState : 3; + Uint16 OverrideActive : 1; + Uint16 GlowPlugActive : 1; + Uint16 HeaterActive : 1; + Uint16 OilPressureMissing : 1; + } ApuData; +} CTx101; + +typedef struct ClassTx102 +{ + struct + { + Uint16 PlayCommand : 4; // 0:3 bit + Uint16 rsvd_padding1 : 4; // 4:7 bit + Uint16 rsvd_padding2 : 8; // 1 byte + Uint16 rsvd_padding3 : 16; // 2:3 byte + Uint16 rsvd_padding4 : 16; // 4:5 byte + Uint16 rsvd_padding5 : 16; // 6:7 byte + } GcuCommand; +} CTx102; + +typedef struct ClassTx103 +{ + struct + { + Uint16 EngineStart : 8; // 0 byte + Uint16 EngineStop : 8; // 1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 RpmSetpoint : 16; // 4:5 byte + Uint16 Override : 8; // 6 byte + Uint16 Emergency : 8; // 7 byte + } EcuCommand; +} CTx103; + +typedef struct ClassTx110 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilLevel : 1; // 1 bit + Uint16 IntakeOverHeat : 1; // 2 bit + Uint16 IntakeLoPressure : 1; // 3 bit + Uint16 EngineLoTemperature : 1; // 4 bit + Uint16 EngineSensor : 1; // 5 bit + Uint16 DefaltValueActive : 1; // 6 bit + Uint16 rsvd_padding : 1; // 16bit е + } bit; + } EcuWarning; + + struct + { + CFaultBitValue ApuFault; + }; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + } GcuFault; + + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 LowOilPressure : 1; // 1 bit + Uint16 Actuator : 1; // 2 bit + Uint16 RpmSignal : 1; // 3 bit + Uint16 EngineStartFail : 1; // 4 bit + Uint16 rsvd_padding : 11; // 16bit е + } bit; + } EcuFault; +} CTx110; + +typedef struct ClassTx120 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx120; + +typedef struct ClassTx121 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } GcuData; +} CTx121; + +typedef struct ClassTx130 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CTx130; + +typedef struct ClassTx131 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding1 : 8; // 6 byte + Uint16 rsvd_padding2 : 8; // 7 byte + } EcuData; +} CTx131; + +typedef struct ClassTx132 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 8; // 4 byte + Uint16 rsvd_padding2 : 8; // 5 byte + Uint16 rsvd_padding3 : 8; // 6 byte + Uint16 rsvd_padding4 : 8; // 7 byte + } EcuData; +} CTx132; + +typedef struct ClassRx200 +{ + struct + { + Uint16 HeartBit : 16; // 0:1 byte + Uint16 rsvd_padding1 : 8; // 2 byte + Uint16 rsvd_padding2 : 8; // 3 byte + Uint16 rsvd_padding3 : 8; // 4 byte + Uint16 VersionMajor : 8; // 5 byte + Uint16 VersionMinor : 8; // 6 byte + Uint16 VersionPatch : 8; // 7 byte + } GcuData; +} CRx200; + +typedef struct ClassRx201 +{ + struct + { + Uint16 PlayState : 3; // 0:3 bit + Uint16 rsvd_padding1 : 5; // 4:7 bit + + Uint16 AlarmOccured : 1; // 0 bit + Uint16 Shutdown : 1; // 1 bit + Uint16 rsvd_padding2 : 6; // 2:7 bit + } GcuData; +} CRx201; + +typedef struct ClassRx210 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 PcbOverHeat : 1; // 0 bit + Uint16 FetOverHeat : 1; // 1 bit + Uint16 GenOverHeat1 : 1; // 2 bit + Uint16 GenOverHeat2 : 1; // 3 bit + Uint16 rsvd_padding : 12; // 16bit е + } bit; + } GcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 HwTrip : 1; // 0 bit + Uint16 HwIgbt : 1; // 1 bit + Uint16 HwDc : 1; // 2 bit + Uint16 GenOverCurrentU : 1; // 3 bit + Uint16 GenOverCurrentV : 1; // 4 bit + Uint16 GenOverCurrentW : 1; // 5 bit + Uint16 DcOverVoltage : 1; // 6 bit + Uint16 DcOverCurrent : 1; // 7 bit + + Uint16 CrankningOverCurrent : 1; // 0 bit + Uint16 PcbOverHeat : 1; // 1 bit + Uint16 FetOverHeat : 1; // 2 bit + Uint16 GenTempOverHeat1 : 1; // 3 bit + Uint16 GenTempOverHeat2 : 1; // 4 bit + Uint16 GenOverSpeed : 1; // 5 bit + Uint16 ResolverIC : 1; // 6 bit + Uint16 ResolverParity : 1; // 7 bit + } bit; + }GcuFault; +} CRx210; + +typedef struct ClassRx220 +{ + struct + { + Uint16 DcVoltage : 16; // 0:1 byte + Uint16 DcCurrent : 16; // 2:3 byte + Uint16 Rpm : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } GcuData; +} CRx220; + +typedef struct ClassRx221 +{ + struct + { + Uint16 PcbTemperature : 8; // 0 byte + Uint16 FetTemperature : 8; // 1 byte + Uint16 GenTemperature1 : 8; // 2 byte + Uint16 GenTemperature2 : 8; // 3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } GcuData; +} CRx221; + +typedef struct ClassRx300 +{ + struct + { + Uint16 VersionMajor : 8; // 0 byte + Uint16 VersionMinor : 8; // 1 byte + Uint16 VersionPatch : 8; // 2 byte + Uint16 rsvd_padding1 : 8; // 3 byte + Uint16 rsvd_padding2 : 16; // 4:5 byte + Uint16 rsvd_padding3 : 16; // 6:7 byte + } EcuData; +} CRx300; + +typedef struct ClassRx301 +{ + struct + { + Uint16 AlarmOccured : 1; // 0 bit + Uint16 PlayState : 3; // 1:3 bit + Uint16 OverrideActive : 1; // 4 bit + Uint16 GlowPlugActive : 1; // 5 bit + Uint16 HeaterActive : 1; // 6 bit + Uint16 OilPressureMissing : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } OperationInfo; +} CRx301; + +typedef struct ClassRx310 +{ + union + { + Uint16 uiTotal; + struct + { + Uint16 EngineOverHeat : 1; // 0 bit + Uint16 reserved : 1; // 1 bit + Uint16 LowOilLevel : 1; // 2 bit + Uint16 IntakeOverHeat : 1; // 3 bit + Uint16 IntakeLoPressure : 1; // 4 bit + Uint16 EngineLoTemperature : 1; // 5 bit + Uint16 EngineSensor : 1; // 6 bit + Uint16 DefaltValueActive : 1; // 7 bit + Uint16 rsvd_padding : 8; // 16bit е + } bit; + } EcuWarning; + + union + { + Uint16 uiTotal; + struct + { + Uint16 OilPressureMissing : 1; // 0 bit + Uint16 IntakeOverHeat : 1; // 1 bit + Uint16 EngineOverHeat : 1; // 2 bit + Uint16 Actuator : 1; // 3 bit + Uint16 RpmSignal : 1; // 4 bit + Uint16 EngineStartFail : 1; // 5 bit + Uint16 rsvd_padding : 10; // 16bit е + } bit; + } EcuFault; +} CRx310; + +typedef struct ClassRx320 +{ + struct + { + Uint16 ActualRpm : 16; // 0:1 byte + Uint16 SetRpm : 16; // 2:3 byte + Uint16 ActualTorque : 8; // 4 byte + Uint16 SetTorque : 8; // 5 byte + Uint16 SystemVoltage : 16; // 6:7 byte + } EcuData; +} CRx320; + +typedef struct ClassRx321 +{ + struct + { + Uint16 CoolantTemperature : 8; // 0 byte + Uint16 Fan1Speed : 8; // 1 byte + Uint16 Fan2Speed : 8; // 2 byte + Uint16 CoolantPumpSpeed : 8; // 3 byte + Uint16 BarometicPressure : 16; // 4:5 byte + Uint16 rsvd_padding : 16; // 6:7 byte + } EcuData; +} CRx321; + +typedef struct ClassRx322 +{ + struct + { + Uint16 TotalOperTimeL : 16; // 0:1 byte + Uint16 TotalOperTimeH : 16; // 2:3 byte + Uint16 rsvd_padding1 : 16; // 4:5 byte + Uint16 rsvd_padding2 : 16; // 6:7 byte + } EcuData; +} CRx322; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CTx102 Tx102; +extern CTx103 Tx103; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +#endif /* SOURCE_COMM_H_ */ diff --git a/.staticdata/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf b/.staticdata/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf new file mode 100644 index 0000000..c4f5352 --- /dev/null +++ b/.staticdata/K2DCU/fs/8890e9ee97c4444e796a9d2307745aaf @@ -0,0 +1,214 @@ +#include "main.h" + +void CApuStartReady(void); +void CApuStopProcedure(Uint16 Level); +void CSetEngineActualRpm(Uint16 Rpm); +static void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); +Uint16 CStartSwitchCheck(void); + + +void CApuOperProcedure(void) +{ + if (CApuSystemAlarmCheck() > 0U || KeyOperValue.KeyList.bit.Emergency == 1U) + { + // ˶ ( , ) + CSetApuOperIndex(APU_OPER_IDX_EMERGENCY); + + CActiveChipSelect(0U); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_STANDBY: + { + if (KeyOperValue.KeyList.bit.EngineStartStop == 1U) + { + CSetApuOperIndex(APU_OPER_IDX_START_CHECK); + + CActiveChipSelect(1U); // õŰ ԷµǸ CS ON + + if (CGetEngCoolantTemperature() < -10) // ð µ üũ + { + CSetApuOperIndex(APU_OPER_IDX_ENGINE_PREHEAT); + } + else + { + CSetApuOperIndex(APU_OPER_IDX_CRANKING); + } + } + break; + } + case APU_OPER_IDX_ENGINE_PREHEAT: + { + break; + } + case APU_OPER_IDX_CRANKING: + { + CSetGcuCommand(GCU_OPER_CMD_CRANKING); + + if (CGetGeneratorRpm() > 800) + { + CSetGcuCommand(GCU_OPER_CMD_STOP_CRANKING); + CSetApuOperIndex(APU_OPER_IDX_CHECK_OPERATION); + } + break; + } + case APU_OPER_IDX_CHECK_OPERATION: + { + + } + } + + + } +} + +void CSetApuOperIndex(eApuOperIdx idx) +{ + GeneralOperValue.uiApuState = (Uint16) idx; +} + +eApuOperIdx CGetApuOperIndex(void) +{ + return (eApuOperIdx)GeneralOperValue.uiApuState; +} + +Uint16 CStartSwitchCheck(void) +{ + return KeyOperValue.KeyList.bit.EngineStartStop; +} + + +Uint16 CApuSystemAlarmCheck(void) +{ + return ((FaultBitValue.ulTotal | Rx210.GcuFault.uiTotal | Rx310.EcuFault.uiTotal) > 0) ? 1U : 0U; +} + +void CSetEngineActualRpm(Uint16 Rpm) +{ + float32 fTemp = (float32) Rpm / 0.125f; // 0.125 mean : J1939 Scaling Factor. + + Tx103.EcuCommand.RpmSetpoint = (Uint16) fTemp; +} + +Uint16 CGetEngineActualRpm(void) +{ + float32 fTemp = (float32) Rx320.EcuData.ActualRpm * 0.125f; + + return (Uint16) fTemp; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.GcuData.Rpm; +} + +static void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if (Command == ECU_OPER_CMD_STOP) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(2400U); + } + else if (Command == ECU_OPER_CMD_START) + { + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; + CSetEngineActualRpm(2400U); + } + else + { + // Emergency + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.EcuData.CoolantTemperature - 40; // µ -40 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenence.ManualCranking == 1U) + { + if (CApuSystemAlarmCheck() == 0U) + { + ; // ˶ 츸 ϵ . + } + } + else + { + ; + } + + if (GeneralOperValue.Maintenence.LampTest == 1U) + { + GPIO_CPU_LED_OPERATION(1U); + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + } + else + { + GPIO_CPU_LED_OPERATION(0U); + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + } + + if (GeneralOperValue.Maintenence.KeyTest == 1U) + { + if ((GPIO_KEY_UP() == 1U) && (GPIO_KEY_DOWN() == 1U)) + { + GeneralOperValue.Maintenence.KeyTest = 0U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + } + } +} + +void CLedControlProcedure(void) +{ + switch (CGetApuOperIndex()) + { + case APU_OPER_IDX_EMERGENCY: + { + GPIO_CPU_LED_FAULT(1U); + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_STANDBY: + { + GPIO_CPU_LED_STOP(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_OPERATION(0U); + break; + } + case APU_OPER_IDX_ENGINE_STABLED: + { + GPIO_CPU_LED_OPERATION(1U); + + GPIO_CPU_LED_FAULT(0U); + GPIO_CPU_LED_STOP(0U); + break; + } + default: + { + break; + } + } +} diff --git a/.staticdata/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ b/.staticdata/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ new file mode 100644 index 0000000..3d2dc0f --- /dev/null +++ b/.staticdata/K2DCU/fs/9077ed2e39ea792eb6efb8fbf0f743ee_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ b/.staticdata/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ new file mode 100644 index 0000000..4d3413d --- /dev/null +++ b/.staticdata/K2DCU/fs/933da5f9c7d8493c891b753e1b164c93_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ b/.staticdata/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ new file mode 100644 index 0000000..ff2d98b --- /dev/null +++ b/.staticdata/K2DCU/fs/95072f0928fa2d7da9f755d67c6180f6_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b b/.staticdata/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b new file mode 100644 index 0000000..6b72ad5 --- /dev/null +++ b/.staticdata/K2DCU/fs/9821caf04f2ca6f57dea55cc0237aa3b @@ -0,0 +1,151 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +enum +{ + OLED_LINE_TITLE = 0U, + OLED_LINE_1 = 14U, + OLED_LINE_2 = 27U, + OLED_LINE_3 = 40U, + OLED_LINE_4 = 53U +}; + +enum +{ + OLED_ROW_0 = 0U, + OLED_ROW_1, + OLED_ROW_2, + OLED_ROW_3, + OLED_ROW_4 +}; + +enum +{ + OLED_PASS_DIGIT_1 = 0U, + OLED_PASS_DIGIT_2, + OLED_PASS_DIGIT_3, + OLED_PASS_DIGIT_4 +}; + +typedef enum +{ + OLED_PAGE_APU1 = 0U, // 0 + OLED_PAGE_APU2, // 1 + OLED_PAGE_MENU1, // 2 + OLED_PAGE_MENU2, // 3 + OLED_PAGE_TEMP, // 4 + OLED_PAGE_SENSOR1, // 5 + OLED_PAGE_SENSOR2, // 6 + OLED_PAGE_SENSOR3, // 7 + OLED_PAGE_SENSOR4, // 8 + OLED_PAGE_WARNING1, // 9 + OLED_PAGE_WARNING2, // 10 + OLED_PAGE_FAULT1, // 11 + OLED_PAGE_FAULT2, // 12 + OLED_PAGE_FAULT3, // 13 + OLED_PAGE_FAULT4, // 14 + OLED_PAGE_FAULT5, // 15 + OLED_PAGE_FAULT6, // 16 + OLED_PAGE_RESET_ALARM, // 17 + OLED_PAGE_PASSWORD, // 18 + OLED_PAGE_MAINTENENCE, // 19 + OLED_PAGE_KEY_TEST, // 20 + OLED_PAGE_SHUTDOWN, // 21 + OLED_PAGE_MAX +} EOledPage; + +enum +{ + OLED_MENU_APU = 0U, // 0 + OLED_MENU_TEMP, // 1 + OLED_MENU_SENSOR, // 2 + OLED_MENU_WARNING, // 3 + + OLED_MENU_FAULT = 0U, // 0 + OLED_MENU_RESET, // 1 + OLED_MENU_DEBUG // 2 +}; + +enum +{ + OLED_LINE_FOCUS_1 = 0U, + OLED_LINE_FOCUS_2, + OLED_LINE_FOCUS_3, + OLED_LINE_FOCUS_4 +}; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiAlarmPopCheck; + Uint16 uiAlreadyAlarm; + Uint16 uiPrevAlarmPage; + Uint16 uiResetAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X1; + Uint16 Y1; + Uint16 X2; + Uint16 Y2; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/.staticdata/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe b/.staticdata/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe new file mode 100644 index 0000000..fe8e0e0 --- /dev/null +++ b/.staticdata/K2DCU/fs/99817de263c0034e34d296b0cb56a4fe @@ -0,0 +1,47 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef enum +{ + APU_OPER_IDX_BOOT = 0U, // 0 + APU_OPER_IDX_INITIAL, // 1 + APU_OPER_IDX_POST, // 2 + APU_OPER_IDX_EMERGENCY, // 3 + APU_OPER_IDX_STANDBY, // 4 + APU_OPER_IDX_START_CHECK, // 5 + APU_OPER_IDX_ENGINE_PREHEAT, // 6 + APU_OPER_IDX_CRANKING, // 7 + APU_OPER_IDX_ENGINE_WARM_UP, // 8 + APU_OPER_IDX_CHECK_OPERATION, // 9 + APU_OPER_IDX_GENERATING, // 10 + APU_OPER_IDX_ENGINE_STABLED, // 11 + APU_OPER_IDX_ENGINE_STOP, // 12 + APU_OPER_IDX_ENGINE_COOLDOWN // 13 +} eApuOperIdx; + +typedef enum +{ + GCU_OPER_CMD_STOP = 0U, // 0 + GCU_OPER_CMD_CRANKING, // 1 + GCU_OPER_CMD_STOP_CRANKING, // 2 + GCU_OPER_CMD_GENERATING // 3 +} eGcuCmdIdx; + +typedef enum +{ + ECU_OPER_CMD_STOP = 0U, // 0 + ECU_OPER_CMD_START, // 1 + ECU_OPER_CMD_EMERGENCY // 2 +} eEcuCmdIdx; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +Uint16 CApuSystemAlarmCheck(void); +void CSetApuOperIndex(eApuOperIdx idx); +eApuOperIdx CGetApuOperIndex(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); + +#endif /* SOURCE_OPER_H_ */ diff --git a/.staticdata/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ b/.staticdata/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ new file mode 100644 index 0000000..5b0001b --- /dev/null +++ b/.staticdata/K2DCU/fs/9fed1f3d1b272ed64fb0aae7af58f579_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/.staticdata/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ b/.staticdata/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ new file mode 100644 index 0000000..4ce9ce2 --- /dev/null +++ b/.staticdata/K2DCU/fs/a6f881c54312ea8f400bf74355c4d150_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ b/.staticdata/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ new file mode 100644 index 0000000..4831619 --- /dev/null +++ b/.staticdata/K2DCU/fs/ac8764a3548e88d72daf71bdb8802637_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ b/.staticdata/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ new file mode 100644 index 0000000..4c4b852 --- /dev/null +++ b/.staticdata/K2DCU/fs/b6323dc93b829c14cb248143d278e658_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ b/.staticdata/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ new file mode 100644 index 0000000..c40164d --- /dev/null +++ b/.staticdata/K2DCU/fs/b7812b5c92f7e9a8222c90e7213de8a1_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ b/.staticdata/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ new file mode 100644 index 0000000..0aa33dc --- /dev/null +++ b/.staticdata/K2DCU/fs/be63107e4c571eca66a32b427e94f3b4_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ b/.staticdata/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ new file mode 100644 index 0000000..6614163 --- /dev/null +++ b/.staticdata/K2DCU/fs/bf0ae726f9a9f939656ec75fee474341_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ b/.staticdata/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ new file mode 100644 index 0000000..3b00d75 --- /dev/null +++ b/.staticdata/K2DCU/fs/cae8014a42e613f1823fc04b9619dd0d_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 b/.staticdata/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 new file mode 100644 index 0000000..19b41d3 --- /dev/null +++ b/.staticdata/K2DCU/fs/cd719760889f08faea1f4976a31b99e0 @@ -0,0 +1,192 @@ +#ifndef CFONT_H +#define CFONT_H + +const Uint16 EngFontTable[96][9] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ! + { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // # + { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $ + { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // % + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // & + { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' + { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // ( + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // ) + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // * + { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // , + { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // - + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // . + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // / + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0 + { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1 + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2 + { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3 + { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4 + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5 + { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6 + { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7 + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8 + { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9 + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // : + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ; + { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // < + { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // = + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // > + { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ? + { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @ + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A + { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B + { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D + { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E + { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G + { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J + { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K + { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M + { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P + { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S + { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T + { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V + { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W + { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // Y + { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z + { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [ + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON) + { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ] + { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _ + { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ` + { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b + { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c + { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e + { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i + { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k + { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l + { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n + { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q + { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r + { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t + { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w + { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x + { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z + { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // { + { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // | + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // } + { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~ + { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, //  +}; + +const Uint16 EtcFontTable[81][18] = +{ + { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }, // , A1C9 + { 0x00, 0x06, 0x00, 0x78, 0x07, 0xE0, 0x7F, 0x87, 0xFC, 0x7F, 0x87, 0xE0, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00 }, // , A2BA + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x12, 0xA1, 0x2A, 0x24, 0xC2, 0x48, 0x3C, 0xA4, 0x34, 0x40, 0x00, 0x00 }, // , A7A1 + { 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x68, 0xA5, 0x4A, 0x54, 0xC5, 0x48, 0x54, 0xA5, 0x54, 0x00, 0x00, 0x00 }, // , A7A2 + { 0x00, 0x00, 0x44, 0x04, 0xA0, 0x4A, 0x1C, 0xA2, 0x4A, 0x24, 0xC2, 0x48, 0x25, 0xA1, 0xE4, 0x00, 0x00, 0x00 }, // , A7A3 + { 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0x05, 0x00, 0x50, 0x06, 0x00, 0x40, 0x0D, 0x00, 0x20, 0x00, 0x00, 0x00 }, // , A7A4 + { 0x00, 0x02, 0x04, 0x20, 0xA2, 0x0A, 0x24, 0xA2, 0x8A, 0x30, 0xC3, 0x08, 0x29, 0x52, 0x62, 0x00, 0x00, 0x00 }, // , A7A5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xC2, 0x52, 0x21, 0x02, 0x10, 0x25, 0x21, 0x8C, 0x00, 0x00, 0x00 }, // , A7A6 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x6A, 0x95, 0x56, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7A7 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x36, 0x94, 0xD6, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7A8 + { 0x00, 0x00, 0x04, 0x00, 0x20, 0x04, 0x76, 0x24, 0x94, 0x49, 0x04, 0x90, 0x49, 0x04, 0x90, 0x00, 0x00, 0x00 }, // , A7A9 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x02, 0x4E, 0x95, 0x56, 0x65, 0x45, 0x54, 0x4D, 0x44, 0x54, 0x00, 0x00, 0x00 }, // , A7AA + { 0x00, 0x00, 0x80, 0x10, 0x01, 0x00, 0x3B, 0x41, 0x2A, 0x12, 0xA1, 0x2A, 0x12, 0xA1, 0x2A, 0x00, 0x00, 0x00 }, // , A7AB + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x44, 0xAA, 0x4A, 0xA4, 0xAA, 0x4A, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7AC + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0xA1, 0x55, 0x29, 0x52, 0x95, 0x35, 0x54, 0x15, 0x40, 0x00, 0x00 }, // , A7AD + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xA5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00 }, // , A7AE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x44, 0xAA, 0x42, 0xA4, 0x2A, 0x4A, 0xA3, 0x2A, 0x00, 0x00, 0x00 }, // , A7AF + { 0x00, 0x04, 0x00, 0x40, 0x04, 0x00, 0x4B, 0x45, 0x2A, 0x62, 0xA6, 0x2A, 0x52, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // , A7B0 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x6A, 0xA5, 0x57, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // , A7B1 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x36, 0xA4, 0xD7, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // , A7B2 + { 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x3B, 0x22, 0x4B, 0x24, 0x82, 0x48, 0x24, 0x82, 0x48, 0x00, 0x00, 0x00 }, // , A7B3 + { 0x00, 0x04, 0x02, 0x40, 0x14, 0x01, 0x4E, 0xA5, 0x57, 0x65, 0x46, 0x54, 0x55, 0x44, 0xD4, 0x00, 0x00, 0x00 }, // , A7B4 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x38, 0xC2, 0x52, 0x24, 0xE2, 0x52, 0x25, 0x22, 0x4D, 0x00, 0x00, 0x00 }, // , A7B5 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xE1, 0x52, 0x29, 0x22, 0x92, 0x34, 0xE4, 0x12, 0x40, 0xC0, 0x00 }, // , A7B6 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xE5, 0x52, 0x55, 0x25, 0x52, 0x54, 0xE5, 0x52, 0x00, 0xC0, 0x00 }, // , A7B7 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x24, 0xE2, 0x92, 0x31, 0x23, 0x12, 0x28, 0xE2, 0x52, 0x00, 0xC0, 0x00 }, // , A7B8 + { 0x00, 0x02, 0x08, 0x20, 0x82, 0x08, 0x25, 0xC2, 0x88, 0x30, 0x83, 0x08, 0x28, 0xA2, 0x44, 0x00, 0x00, 0x00 }, // , A7B9 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x33, 0x14, 0xC9, 0x43, 0x94, 0x49, 0x4C, 0x93, 0x35, 0x00, 0x00, 0x00 }, // , A7BA + { 0x00, 0x04, 0x01, 0x40, 0x14, 0x01, 0x56, 0x96, 0x95, 0x68, 0xD6, 0x95, 0x59, 0x55, 0x6B, 0x00, 0x00, 0x00 }, // , A7BB + { 0x00, 0x00, 0x5C, 0x05, 0x20, 0x52, 0x1D, 0x22, 0x5C, 0x25, 0x22, 0x52, 0x25, 0x21, 0xDC, 0x00, 0x00, 0x00 }, // , A7BC + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x68, 0xE5, 0x59, 0x55, 0x45, 0x52, 0x55, 0x95, 0x56, 0x00, 0x00, 0x00 }, // , A7BD + { 0x00, 0x00, 0x12, 0x01, 0x10, 0x21, 0x6A, 0xE5, 0x73, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7BE + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x39, 0x22, 0x0C, 0x20, 0x00, 0x00 }, // , A7BF + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x25, 0x22, 0x4C, 0x00, 0x00, 0x00 }, // , A7C0 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x61, 0x29, 0x24, 0x42, 0x42, 0x3A, 0x94, 0x06, 0x40, 0x00, 0x00 }, // , A7C1 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC5, 0x52, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // , A7C2 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x39, 0x42, 0x54, 0x25, 0x42, 0x48, 0x38, 0x82, 0x08, 0x20, 0x00, 0x00 }, // , A7C3 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x71, 0x44, 0x94, 0x49, 0x44, 0x88, 0x48, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C4 + { 0x00, 0x00, 0x11, 0x01, 0x10, 0x11, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x44, 0x3A, 0x44, 0x04, 0x40, 0x00, 0x00 }, // , A7C5 + { 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x69, 0x45, 0x54, 0x55, 0x45, 0x48, 0x54, 0x85, 0x48, 0x00, 0x00, 0x00 }, // , A7C6 + { 0x00, 0x04, 0x22, 0x42, 0x24, 0x22, 0x49, 0x45, 0x14, 0x61, 0x46, 0x08, 0x50, 0x84, 0x88, 0x00, 0x00, 0x00 }, // , A7C7 + { 0x00, 0x04, 0x51, 0x45, 0x16, 0xD1, 0x6C, 0xA5, 0x4A, 0x54, 0xA5, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00 }, // , A7C8 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0x44, 0xBE, 0x72, 0x24, 0x22, 0x40, 0x00, 0x00 }, // , A7C9 + { 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0xC4, 0xA2, 0x4A, 0x24, 0xA2, 0x00, 0x00, 0x00 }, // , A7CA + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x5F, 0x3B, 0x14, 0x11, 0x40, 0x00, 0x00 }, // , A7CB + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x68, 0xA5, 0x4A, 0x54, 0xA5, 0x5F, 0x55, 0x15, 0x51, 0x00, 0x00, 0x00 }, // , A7CC + { 0x00, 0x02, 0x04, 0x20, 0x42, 0x04, 0x24, 0xA2, 0x8A, 0x30, 0xA3, 0x1F, 0x29, 0x12, 0x51, 0x00, 0x00, 0x00 }, // , A7CD + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x71, 0x44, 0x14, 0x40, 0x00, 0x00 }, // , A7CE + { 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x49, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7CF + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x15, 0x51, 0x55, 0x29, 0x52, 0x8A, 0x34, 0xA4, 0x0A, 0x40, 0x00, 0x00 }, // , A7D0 + { 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x69, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x54, 0xA5, 0x4A, 0x00, 0x00, 0x00 }, // , A7D1 + { 0x00, 0x04, 0x2A, 0x42, 0xA4, 0x2A, 0x4A, 0xA5, 0x2A, 0x62, 0xA6, 0x14, 0x51, 0x44, 0x94, 0x00, 0x00, 0x00 }, // , A7D2 + { 0x00, 0x04, 0x55, 0x45, 0x56, 0xD5, 0x6D, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x44, 0xA4, 0x4A, 0x00, 0x00, 0x00 }, // , A7D3 + { 0x00, 0x02, 0x40, 0x24, 0x02, 0x40, 0x25, 0xE3, 0xC2, 0x24, 0x42, 0x48, 0x25, 0x02, 0x5E, 0x00, 0x00, 0x00 }, // , A7D4 + { 0x00, 0x04, 0x50, 0x45, 0x04, 0x50, 0x55, 0x75, 0x71, 0x65, 0x26, 0x52, 0x55, 0x45, 0x57, 0x00, 0x00, 0x00 }, // , A7D5 + { 0x00, 0x04, 0x48, 0x44, 0x86, 0xC8, 0x6C, 0xF5, 0x79, 0x54, 0xA5, 0x4A, 0x54, 0xC4, 0x4F, 0x00, 0x00, 0x00 }, // , A7D6 + { 0x00, 0x03, 0x28, 0x4A, 0x84, 0xA8, 0x42, 0xF5, 0xB9, 0x4A, 0xA4, 0xAA, 0x4A, 0xC3, 0xAF, 0x00, 0x00, 0x00 }, // , A7D7 + { 0x00, 0x07, 0xE8, 0x12, 0x81, 0x28, 0x12, 0xF1, 0x39, 0x12, 0xA1, 0x2A, 0x12, 0xC1, 0x2F, 0x00, 0x00, 0x00 }, // , A7D8 + { 0x00, 0x00, 0x00, 0x07, 0x00, 0x88, 0x10, 0x41, 0x04, 0x10, 0x40, 0x88, 0x15, 0x41, 0xDC, 0x00, 0x00, 0x00 }, // , A7D9 + { 0x00, 0x04, 0x1C, 0x42, 0x24, 0x22, 0x4A, 0x25, 0x22, 0x61, 0x46, 0x14, 0x51, 0x44, 0xB6, 0x00, 0x00, 0x00 }, // , A7DA + { 0x00, 0x04, 0x4E, 0x45, 0x16, 0xD1, 0x6D, 0x15, 0x51, 0x54, 0xA5, 0x4A, 0x44, 0xA4, 0x5B, 0x00, 0x00, 0x00 }, // , A7DB + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x72, 0x04, 0x20, 0x40, 0x00, 0x00 }, // , A7DC + { 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x4A, 0x04, 0xA0, 0x00, 0x00, 0x00 }, // , A7DD + { 0x00, 0x00, 0x0F, 0x00, 0x80, 0x08, 0x12, 0x81, 0x2E, 0x24, 0x82, 0x48, 0x3A, 0x84, 0x08, 0x40, 0x00, 0x00 }, // , A7DE + { 0x00, 0x00, 0x02, 0x00, 0x20, 0x02, 0x6B, 0x25, 0x4A, 0x54, 0xA5, 0x4A, 0x54, 0xA5, 0x72, 0x00, 0x00, 0x00 }, // , A7DF + { 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x31, 0xC4, 0xA4, 0x42, 0x44, 0x24, 0x4A, 0x43, 0x1C, 0x00, 0x00, 0x00 }, // , A7E0 + { 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x56, 0x36, 0x95, 0x47, 0x54, 0x95, 0x49, 0x54, 0x6B, 0x00, 0x00, 0x00 }, // , A7E1 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x54, 0x4E, 0xC0, 0x07, 0x07, 0x87, 0x86, 0x00, 0xC0, 0x02, 0x00, 0xC0, 0x00 }, // , A7E2 + { 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x57, 0x4E, 0xC0, 0x32, 0x1C, 0x16, 0x1A, 0x03, 0x30, 0x08, 0x03, 0x00, 0x00 }, // , A7E3 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xA2, 0x2C, 0x18, 0x80, 0x48, 0x22, 0x81, 0xC8, 0x00, 0x00, 0x00 }, // , A7E4 + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xC2, 0x52, 0x38, 0xE2, 0x12, 0x21, 0x22, 0x0D, 0x00, 0x00, 0x00 }, // , A7E5 + { 0x00, 0x04, 0x60, 0x45, 0x04, 0x50, 0x55, 0xC5, 0x52, 0x66, 0x66, 0x4A, 0x54, 0xA5, 0x47, 0x00, 0x00, 0x00 }, // , A7E6 + { 0x00, 0x04, 0x58, 0x45, 0x46, 0xD4, 0x6D, 0x65, 0x55, 0x55, 0xB5, 0x55, 0x45, 0x54, 0x53, 0x00, 0x00, 0x00 }, // , A7E7 + { 0x00, 0x03, 0x30, 0x4A, 0x84, 0xA8, 0x42, 0xE5, 0xA9, 0x4B, 0x34, 0xA5, 0x4A, 0x53, 0xA3, 0x00, 0x00, 0x00 }, // , A7E8 + { 0x00, 0x05, 0x50, 0x55, 0x05, 0x50, 0x55, 0xC5, 0x52, 0x55, 0x22, 0x92, 0x29, 0x22, 0x9C, 0x00, 0x00, 0x00 }, // , A7E9 + { 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x26, 0x82, 0x54, 0x25, 0x42, 0x54, 0x25, 0x42, 0x54, 0x00, 0x00, 0x00 }, // , A7EA + { 0x00, 0x01, 0x00, 0x10, 0x01, 0x00, 0x14, 0x41, 0x28, 0x11, 0x01, 0x10, 0x12, 0x81, 0x44, 0x00, 0x00, 0x00 }, // , A7EB + { 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xE3, 0x92, 0x25, 0x22, 0x52, 0x24, 0xE3, 0x82, 0x00, 0x20, 0x00 }, // , A7EC + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x42, 0x25, 0xA2, 0x49, 0x44, 0x94, 0x48, 0x83, 0x08, 0x03, 0x00, 0x00 }, // , A7ED + { 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x22, 0x21, 0x22, 0x09, 0x44, 0x94, 0x48, 0x83, 0x08, 0x00, 0x00, 0x00 }, // , A7EE + { 0x24, 0x05, 0x60, 0x56, 0x04, 0xA0, 0x4A, 0xB5, 0xAD, 0x2B, 0x51, 0x35, 0x12, 0xB1, 0x2D, 0x00, 0x20, 0x00 } // , A7EF +}; + +extern const Uint16 EngFontTable[96][9]; +extern const Uint16 EtcFontTable[81][18]; +#endif + diff --git a/.staticdata/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ b/.staticdata/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ new file mode 100644 index 0000000..ff7633e --- /dev/null +++ b/.staticdata/K2DCU/fs/d46a8813a02b41fd3bf57e1c75286e8f_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/.staticdata/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 b/.staticdata/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 new file mode 100644 index 0000000..dcd417b --- /dev/null +++ b/.staticdata/K2DCU/fs/da8070adbba349467ab6d7cf8ce841e4 @@ -0,0 +1,864 @@ +#include "main.h" + +void CInitAlarmOperValue(void); +void CKeyMainPowerProcess(void); +void CKeyArrowUpProcess(void); +void CKeyArrowDownProcess(void); +void CKeyEnterProcess(void); +void CKeyMenuProcess(void); +void CKeyEngineStartStopProcess(void); +void CKeyEmergencyProcess(void); +void CInitAdcStructure(void); +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh); +Uint32 CGetKey(void); +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void MoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; +CAlarmOperValue AlarmOperValue[IDX_FAULT_MAX]; +CFaultBitValue FaultBitValue; +CKeyOperValue KeyOperValue; + +static const CKeyHandler KeyTable[IDX_KEY_MAX] = +{ + { IDX_KEY_MAIN_POWER, CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, CKeyArrowDownProcess }, + { IDX_KEY_ENTER, CKeyEnterProcess }, + { IDX_KEY_MENU, CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, CKeyEmergencyProcess } +}; + +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN2_I]; + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0f); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0f); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0f); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0f); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0f); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0f); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0f); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + Uint64 ullFaultValue = ((Uint64)FaultBitValue.ulTotal & 0x3FFFFUL) | (((Uint64)Rx210.GcuFault.uiTotal & 0xFFFFU) << 19UL) | (((Uint64)Rx310.EcuFault.uiTotal & 0x3FU) << 35UL); + Uint32 ulWarningValue = ((Uint32)Rx210.GcuWarning.uiTotal & 0x7U) | (((Uint32)Rx310.EcuWarning.uiTotal & 0xFU) << 4U); + Uint16 i; + + if (OledOperValue.uiAlarmPopCheck == 0U) + { + if (ulWarningValue > 0U) + { + for (i = 0U; i < 16U; i++) + { + if ((ulWarningValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = ((i / 9U) + OLED_PAGE_WARNING1); + break; + } + } + } + if (ullFaultValue > 0U) + { + for (i = 0U; i < 64U; i++) + { + if ((ullFaultValue >> i) == 1U) + { + OledOperValue.uiAlarmPopCheck = 1U; + OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum; + OledOperValue.uiPageNum = (((i % 64U) / 8U) + OLED_PAGE_FAULT1); + break; + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0U; + + if (CGetApuOperIndex() == APU_OPER_IDX_EMERGENCY) + { + // Ÿ ƿ ߻ Ʈ Ŭ Ѵ. + GeneralOperValue.Conection.CarComputer = (FaultBitValue.bit.CarCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (FaultBitValue.bit.GcuCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (FaultBitValue.bit.EcuCommTimeOut == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + if (GeneralOperValue.uiAlarmReset == 1U) + { + GeneralOperValue.uiAlarmReset = 0U; + + CInitAlarmOperValue(); + } + } + else + { + if (GeneralOperValue.uiApuState > APU_OPER_IDX_EMERGENCY) + { + // Comm Timeout Checks + FaultBitValue.bit.CarCommTimeout = CAlarmCheck(IDX_FAULT_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GcuCommTimeout = CAlarmCheck(IDX_FAULT_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.EcuCommTimeOut = CAlarmCheck(IDX_FAULT_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK); + + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + // RPM Ǿ Ѵ. + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = ABS(iDiffRpm); + FaultBitValue.bit.RpmError = CAlarmCheck(IDX_FAULT_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK); + } + FaultBitValue.bit.EngineHeatOverCurrent = CAlarmCheck(IDX_FAULT_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.GlowPlugOverCurrent = CAlarmCheck(IDX_FAULT_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.SolenoidOverCurrent = CAlarmCheck(IDX_FAULT_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.FuelPumpOverCurrent = CAlarmCheck(IDX_FAULT_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.CoolantPumpOverCurrent = CAlarmCheck(IDX_FAULT_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan1OverCurrent = CAlarmCheck(IDX_FAULT_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK); + FaultBitValue.bit.Fan2OverCurrent = CAlarmCheck(IDX_FAULT_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK); + + // Fuse ȣ ġ ϴ CS ON ¿ ۵ϹǷ CS HI , Fuse ȣ HI ܼ + if (CGetApuOperIndex() > APU_OPER_IDX_STANDBY) + { + FaultBitValue.bit.EngineHeatOpen = CheckOpenFault(GPIO_ENGINE_HEATER_CS_READ(), GPIO_ENGINE_HEATER_FUSE()); + FaultBitValue.bit.GlowPlugOpen = CheckOpenFault(GPIO_GLOW_PLUG_CS_READ(), GPIO_GLOW_PLUG_FUSE()); + FaultBitValue.bit.SolenoidOpen = CheckOpenFault(GPIO_SOLENOID_CS_READ(), GPIO_SOLENOID_FUSE()); + FaultBitValue.bit.FuelPumpOpen = CheckOpenFault(GPIO_FUEL_PUMP_CS_READ(), GPIO_FUEL_PUMP_FUSE()); + FaultBitValue.bit.CoolantPumpOpen = CheckOpenFault(GPIO_COOLANT_PUMP_CS_READ(), GPIO_COOLANT_PUMP_FUSE()); + FaultBitValue.bit.Fan1Open = CheckOpenFault(GPIO_FAN1_CS_READ(), GPIO_FAN1_FUSE()); + FaultBitValue.bit.Fan2Open = CheckOpenFault(GPIO_FAN2_CS_READ(), GPIO_FAN2_FUSE()); + } + } + } +} + +Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh) +{ + // ȣ 1(High) 1(Fault) ȯ + return ((isCsHigh == 1U) && (isFuseHigh == 1U)) ? 1U : 0U; +} + +void CInitAlarmOperValue(void) +{ + int16 i; + + for (i = 0; i < IDX_FAULT_MAX; i++) + { + (void) memset(&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void) memset(&FaultBitValue, 0, sizeof(CFaultBitValue)); + (void) memset(&CommCheck, 0, sizeof(CCommCheck)); + + // ü/GCU/ECU ȣ ܼ ٸ Լ ó + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[IDX_FAULT_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime = 1U; // ð ϹǷ + + AlarmOperValue[IDX_FAULT_RPM_ERR].fCheckLimit = 300.0f; // Value + AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_SOLENOID_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN1_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime = 10U; // Value + + AlarmOperValue[IDX_FAULT_FAN2_OC].fCheckLimit = 10.0f; // Value + AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime = 10U; // Value + +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_I + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_I + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_I + + AdcRegs.ADCMAXCONV.all = IDX_ADC_MAX; // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + CInitAlarmOperValue(); +} + +void CInitAdcStructure(void) +{ + (void) memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + (void) memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void) memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_I.fGain = 0.005637f; + Adc_GlowPlug_I.fGain = 0.005637f; + Adc_Solenoid_I.fGain = 0.005637f; + Adc_FuelPump_I.fGain = 0.005637f; + Adc_CoolantPump_I.fGain = 0.005637f; + Adc_Fan1_I.fGain = 0.005637f; + Adc_Fan2_I.fGain = 0.005637f; + + Adc_EngineHeater_I.fOffset = -2.333f; + Adc_GlowPlug_I.fOffset = -2.333f; + Adc_Solenoid_I.fOffset = -2.333f; + Adc_FuelPump_I.fOffset = -2.333f; + Adc_CoolantPump_I.fOffset = -2.333f; + Adc_Fan1_I.fOffset = -2.333f; + Adc_Fan2_I.fOffset = -2.333f; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ +#if 1 + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 100) + { + AdcBuff->uiSamplingCount = 0; + AdcBuff->fSampledSum /= 100; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledSum) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); + AdcBuff->fSampledSum = 0.0f; + } +#else + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledValue) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue); +#endif +} + +Uint32 CGetKey(void) +{ + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + Uint16 ucKeyGpioList[7] = { 67, 39, 31, 30, 29, 66, 64}; + + for (i = 0; i < IDX_KEY_MAX; i++) + { + ucDiv = ucKeyGpioList[i] / 32; + ucMod = ucKeyGpioList[i] % 32; + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + static Uint32 ulLongKeyCnt = 0UL; // Ű īƮ + static Uint16 uiLongKeyProcessed = 0U; // Ű ó Ϸ ÷ (ߺ ) + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~KEY_POWER_MASK; // Ű Ű ϵ, Ű(Bit 0) ȭ (& ~KEY_POWER_MASK) + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // ä͸ + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + // Ű Ű POST ܰ谡 Ѿ Ѵ. + if ((KeyOperValue.uiKeyWaitCount == 0U) && (CGetApuOperIndex() > APU_OPER_IDX_POST)) + { + ulPrevKey = (ulPrevKey & KEY_POWER_MASK) | (ulReadKey & ~KEY_POWER_MASK); // ulPrevKey Ʈ ϰ Ʈ + CKeyCheck(ulChangeKey, ulReadKey); // Ϲ Ű + } + } + } + else + { + // ȭ ä͸ ʱȭ (Ϲ Ű) + // , ִ ulPrevKey ʿ + if ((KeyOperValue.uiKeyWait) != 0U && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // Bit 0 ִ Ȯ (1 = ) + if ((ulReadKey & KEY_POWER_MASK) == KEY_POWER_MASK) + { + // ̹ ó ° ƴ϶ īƮ + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 1(1000ms) + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + CKeyCheck(KEY_POWER_MASK, ulReadKey); // Ű (CKeyCheck Ű Ʈ ) + uiLongKeyProcessed = 1U; // ٽ ʵ ÷ + ulLongKeyCnt = LONG_KEY_TIME; // īƮ ÷ο + } + } + } + else + { + // Ű ʱȭ + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey Bit 0 µ 0 ȭ ( 񱳸 ) + ulPrevKey &= ~KEY_POWER_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + Uint16 i; + + for (i = 0U; i < IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +void CKeyArrowUpProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + MoveFocusLine(3U, DIR_UP); + } + } + } +} + +void CKeyArrowDownProcess(void) +{ + if (OledOperValue.uiPageNum == OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = OLED_PAGE_APU2; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_4) + { + // Bottom of Menu 1 -> Go to Menu 2 + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + MoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < OLED_PAGE_FAULT6)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle + } + else + { + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3; + } + else + { + MoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CChangePasswordDigit(Uint16 direction) +{ + // Ensure the focus digit is within valid range to avoid out-of-bounds access + if (OledOperValue.uiFocusDigit <= OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void MoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + maxLines - 1U) % maxLines; + } + else // DIR_DOWN + { + OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + 1U) % maxLines; + } +} + +void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case OLED_PAGE_MENU1: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_MENU_APU: + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + break; + } + case OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = OLED_PAGE_TEMP; + break; + } + case OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = OLED_PAGE_WARNING1; + } + break; + } + } + break; + } + case OLED_PAGE_MENU2: + { + switch (OledOperValue.uiFocusLine) + { + case OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = OLED_PAGE_FAULT1; + break; + } + case OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_RESET_ALARM; + break; + } + case OLED_LINE_FOCUS_3: // Maintenence + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + break; + } + default: + break; + } + break; + } + case OLED_PAGE_PASSWORD: + { + if (OledOperValue.uiFocusDigit < OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + // Check password + const Uint16 uiPassword[4] = DEBUG_MENU_PASSWORD; + + if (memcmp(GeneralOperValue.uiPassword, uiPassword, sizeof(uiPassword)) == 0U) + { + GeneralOperValue.uiMaintenence = 1U; + OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE; + OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1; + } + } + break; + } + case OLED_PAGE_RESET_ALARM: + { + // Selected "YES" + if (OledOperValue.uiResetAnswer == 1U) + { + if (CApuSystemAlarmCheck() > 0) + { + GeneralOperValue.uiAlarmReset = 1U; + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + break; + } + case OLED_PAGE_MAINTENENCE: + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenence.ManualCranking = GeneralOperValue.Maintenence.ManualCranking ^ 1U; // Toggle + } + else if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenence.LampTest = GeneralOperValue.Maintenence.LampTest ^ 1U; // Toggle + } + else + { + if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenence.KeyTest = GeneralOperValue.Maintenence.KeyTest ^ 1U; // Toggle + OledOperValue.uiPageNum = OLED_PAGE_KEY_TEST; + } + } + break; + } + default: + { + // Handle Fault/Warning page return logic + if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6)) + { + if (OledOperValue.uiAlarmPopCheck == 1U) + { + OledOperValue.uiAlreadyAlarm = 1U; + OledOperValue.uiPageNum = OledOperValue.uiPrevAlarmPage; + } + } + break; + } + } +} + +void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_MAINTENENCE)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE) + { + GeneralOperValue.uiMaintenence = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = OLED_PAGE_MENU1; + } + } +} + +void CKeyMainPowerProcess(void) +{ + if (CGetApuOperIndex() <= APU_OPER_IDX_STANDBY) + { + // APU ¿ ġ Է + OledOperValue.uiPageNum = OLED_PAGE_SHUTDOWN; + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, TIME_1SEC) == TIME_OVER) + { + GPIO_POWER_HOLD(0); + } + } +} + +void CKeyEngineStartStopProcess(void) +{ + KeyOperValue.KeyList.bit.EngineStartStop = KeyOperValue.KeyList.bit.EngineStartStop ^ 1U; // Toggle +} + +void CKeyEmergencyProcess(void) +{ + // ġ Ŭ ϱ ؼ APU ýۿ ˶ Ѵ. + KeyOperValue.KeyList.bit.Emergency = KeyOperValue.KeyList.bit.Emergency ^ 1U; // Toggle +} diff --git a/.staticdata/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ b/.staticdata/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ new file mode 100644 index 0000000..9ccf069 --- /dev/null +++ b/.staticdata/K2DCU/fs/e18c20618a81a43fd0da48225beac590_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ b/.staticdata/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ new file mode 100644 index 0000000..a4564ad --- /dev/null +++ b/.staticdata/K2DCU/fs/e910164c4975d133b716df08d5962dc0_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ b/.staticdata/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ new file mode 100644 index 0000000..1461873 --- /dev/null +++ b/.staticdata/K2DCU/fs/ea671316ae9e88d01cc786a75cc14e8c_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/.staticdata/K2DCU/fs/f9a156ec434632a46725fb267c577743_ b/.staticdata/K2DCU/fs/f9a156ec434632a46725fb267c577743_ new file mode 100644 index 0000000..e19cb54 --- /dev/null +++ b/.staticdata/K2DCU/fs/f9a156ec434632a46725fb267c577743_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef b/.staticdata/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef new file mode 100644 index 0000000..71b6378 --- /dev/null +++ b/.staticdata/K2DCU/fs/fa7923e9870aeba29fc81ef6ccc608ef @@ -0,0 +1,545 @@ +#include "main.h" + +CPowerOnCheckValue PowerOnCheckValue; +CGeneralOperValue GeneralOperValue; + +CSoftTimer SoftTimer[TIMER_MAX]; +CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +Uint32 ulSoftClock; + +void CInitSystem(void); +void CInitGeneralOperValue(void); +void CInitGpio(void); +void CSystemConfigure(void); +void CMappingInterrupt(void); +void CProcessSoftTimer(void); +Uint16 CPowerOnCheck(void); +void CSoftTimerWorkProcess(void); +Uint16 CIsStatusSoftTimer(Uint16 ucTimerIndex); +void CReloadSoftTimer(Uint16 ucTimerIndex); +void CInitSoftTimers(void); +void CInitSoftTimer(void); +void CConfigSoftTimer(Uint16 ucTimerIndex, Uint32 ulDelay); +void CStartSoftTimer(Uint16 ucTimerIndex); +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +Uint32 CGetSoftClock(void); +void CSOftWaitCountCancel(Uint16 Index); + +int main(void) +{ + CSetApuOperIndex(APU_OPER_IDX_BOOT); + + CInitSystem(); + + CInitOled(); + + CSetApuOperIndex(APU_OPER_IDX_INITIAL); + + for ( ; ; ) + { + CSoftTimerWorkProcess(); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == TIME_OVER) + { + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_POST); // Adc Ϸ POST + } + } + } + else if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + if (CPowerOnCheck() == 0U) + { + AdcOperValue.uiOffsetAdjustStart = 1U; // offset . + + COledBufferReset(); + CSetApuOperIndex(APU_OPER_IDX_STANDBY); + } + } + else + { + if (GeneralOperValue.uiMaintenence == 0U) + { + // 尡 ־ . + //CApuOperProcedure(); + + CLedControlProcedure(); + + GPIO_ENGINE_HEATER_CS(GPIO_USER_MODE_1()); + GPIO_GLOW_PLUG_CS(GPIO_USER_MODE_1()); + GPIO_SOLENOID_CS(GPIO_USER_MODE_1()); + GPIO_FUEL_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_COOLANT_PUMP_CS(GPIO_USER_MODE_1()); + GPIO_FAN1_CS(GPIO_USER_MODE_1()); + GPIO_FAN2_CS(GPIO_USER_MODE_1()); + } + else + { + CDebugModeProcedure(); + } + } + } +} + +void CSoftTimerWorkProcess(void) +{ + static Uint16 RefeshDelay = 0U; + + if (CIsStatusSoftTimer(TIMER_01MS) == SOFTTIMER_TIME_OVER) // Excute Per 1msec + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > APU_OPER_IDX_POST) // ADC Ϸ + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + if (GeneralOperValue.Maintenence.KeyTest == 0U) + { + // (:Ű׽Ʈ) ƴϸ Ű Է . + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (CIsStatusSoftTimer(TIMER_10MS) == SOFTTIMER_TIME_OVER) // Excute Per 10msec + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataA(); + CSendECanDataB(); + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); + + if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) + { + if (CGetApuOperIndex() == APU_OPER_IDX_POST) + { + CDisplayPostFail(); + } + else + { + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + } + + if (CIsStatusSoftTimer(TIMER_100MS) == SOFTTIMER_TIME_OVER) // Excute Per 100msec + { + CReloadSoftTimer(TIMER_100MS); + + // ǻ ѹ̶ Ǿ ŸӾƿ üũ + if (CApuSystemAlarmCheck() == 0U) + { + // ߻ ŸӾƿ üũ ʴ´. + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer < COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : 0U; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : 0U; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : 0U; + } + } + if (CIsStatusSoftTimer(TIMER_1SEC) == SOFTTIMER_TIME_OVER) // Excute Per 1s + { + CReloadSoftTimer(TIMER_1SEC); + + if (OledOperValue.uiAlreadyAlarm == 1U) // ˶ ߻ 1е ٽ ˾ ϱ . + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_POPUP, (TIME_1SEC * 60UL)) == TIME_OVER) + { + OledOperValue.uiAlarmPopCheck = 0U; + OledOperValue.uiAlreadyAlarm = 0U; + } + } + else + { + CSOftWaitCountCancel(SOFTTIMER_WAIT_POPUP); + } + } +} + +void CSOftWaitCountCancel(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0f, 100.0f); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO1 = 0U; // GPIO_COOLING_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U; // GPIO_FUEL_PUMP_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U; // GPIO_COOLING_FAN1_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U; // GPIO_COOLING_FAN2_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U; // GPIO_GLOW_PLUG_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO6 = 0U; // GPIO_ENGINE_HEATER_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U; // GPIO_STOP_SOLENOID_FUSE + GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U; // GPIO_ECU_ON_OFF + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GPIO_POWER_HOLD(1); + + GPIO_CPU_LED_COM_FAULT_N(1); + GPIO_CPU_LED_COM_RUN_N(1); + GPIO_CPU_LED_COM_STA_N(1); + + EDIS; +} + +void CActiveChipSelect(Uint16 Active) +{ + if (Active == 0U) + { + // Ȳ CS OFFѴ. (0 - CS OFF, 1 - CS ON) + GPIO_ENGINE_HEATER_CS(0); + GPIO_GLOW_PLUG_CS(0); + GPIO_SOLENOID_CS(0); + GPIO_FUEL_PUMP_CS(0); + + GPIO_COOLANT_PUMP_CS(0); + GPIO_FAN1_CS(0); + GPIO_FAN2_CS(0); + } + else + { + //  ¿ EcuSignal ¸ Ȯϰ , ۷ο÷, ̵ַ, Ѵ. + // 0 - CS OFF, 1 - CS ON + GPIO_ENGINE_HEATER_CS(GPIO_ENGINE_HEATER()); + GPIO_GLOW_PLUG_CS(GPIO_GLOW_PLUG()); + GPIO_SOLENOID_CS(GPIO_SOLENOID()); + GPIO_FUEL_PUMP_CS(GPIO_FUEL_PUMP()); + + GPIO_COOLANT_PUMP_CS(1); + GPIO_FAN1_CS(1); + GPIO_FAN2_CS(1); + } +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +void CInitGeneralOperValue(void) +{ + (void) memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + (void) memset(&PowerOnCheckValue, 0x1FF, sizeof(CPowerOnCheckValue)); // Set All bit 1 + + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] = 0; +} + +void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = M_INT1 | M_INT9; + + EDIS; +} + +void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + CConfigSoftTimer(TIMER_1SEC, TIME_1SEC); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); + CStartSoftTimer(TIMER_1SEC); +} + +void CStartSoftTimer(Uint16 ucTimerIndex) +{ + if (SoftTimer[ucTimerIndex].iTimer != -1) + { + SoftTimer[ucTimerIndex].iStart = 1; + } +} + +void CInitSoftTimer(void) +{ + Uint16 i; + + (void) memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void) memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +Uint16 CPowerOnCheck(void) +{ + // Ȯ CAN ͷƮ ߻ , üũ + Uint16 retValue = (*(Uint16*)&PowerOnCheckValue) & 0x7FU; + + PowerOnCheckValue.EngineHeaterSensor = ((Adc_EngineHeater_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.GlowPlugSensor = ((Adc_GlowPlug_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.SolenoidSensor = ((Adc_Solenoid_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.FuelPumpSensor = ((Adc_FuelPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.CoolantPumpSensor = ((Adc_CoolantPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan1Sensor = ((Adc_Fan1_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + PowerOnCheckValue.Fan2Sensor = ((Adc_Fan2_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U; + + return retValue; // '0' +} diff --git a/.staticdata/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ b/.staticdata/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ new file mode 100644 index 0000000..0df8e48 --- /dev/null +++ b/.staticdata/K2DCU/fs/fccd551da5b37c73512aba48753f6cec_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ b/.staticdata/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ new file mode 100644 index 0000000..712b04b --- /dev/null +++ b/.staticdata/K2DCU/fs/ff74bbc4db95bf06df6c840598a3ab27_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/.staticdata/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 b/.staticdata/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 new file mode 100644 index 0000000..376775e --- /dev/null +++ b/.staticdata/K2DCU/fs/ff8818a27a6ba924e7d4965307df3de2 @@ -0,0 +1,220 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +typedef signed char int8; +typedef unsigned char Uint8; + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "DSP2833x_EPwm_defines.h" +#include "DSP2833x_I2c_defines.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (!GpioDataRegs.GPBDAT.bit.GPIO39) +#define GPIO_KEY_DOWN() (!GpioDataRegs.GPADAT.bit.GPIO31) +#define GPIO_KEY_ENTER() (!GpioDataRegs.GPADAT.bit.GPIO30) +#define GPIO_KEY_MENU() (!GpioDataRegs.GPADAT.bit.GPIO29) +#define GPIO_KEY_POWER() (!GpioDataRegs.GPCDAT.bit.GPIO67) +#define GPIO_KEY_START() (!GpioDataRegs.GPCDAT.bit.GPIO66) +#define GPIO_KEY_EMERGENCY() (!GpioDataRegs.GPCDAT.bit.GPIO64) + +// CS ȰǾ FUSE high ߻ (ips Ĩ Ǵ fuse) +#define GPIO_ENGINE_HEATER_FUSE() (GpioDataRegs.GPADAT.bit.GPIO6) +#define GPIO_GLOW_PLUG_FUSE() (GpioDataRegs.GPADAT.bit.GPIO5) +#define GPIO_SOLENOID_FUSE() (GpioDataRegs.GPADAT.bit.GPIO7) +#define GPIO_FUEL_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO2) +#define GPIO_COOLANT_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO1) +#define GPIO_FAN1_FUSE() (GpioDataRegs.GPADAT.bit.GPIO3) +#define GPIO_FAN2_FUSE() (GpioDataRegs.GPADAT.bit.GPIO4) + +#define GPIO_ECU_ON_OFF() (GpioDataRegs.GPADAT.bit.GPIO8) +#define GPIO_FUEL_PUMP() (GpioDataRegs.GPADAT.bit.GPIO9) +#define GPIO_GLOW_PLUG() (GpioDataRegs.GPADAT.bit.GPIO10) +#define GPIO_SOLENOID() (GpioDataRegs.GPADAT.bit.GPIO11) +#define GPIO_ENGINE_HEATER() (GpioDataRegs.GPADAT.bit.GPIO24) +#define GPIO_USER_MODE_1() (!GpioDataRegs.GPCDAT.bit.GPIO81) +#define GPIO_USER_MODE_2() (!GpioDataRegs.GPCDAT.bit.GPIO82) +#define GPIO_USER_MODE_3() (!GpioDataRegs.GPCDAT.bit.GPIO83) + +#define GPIO_ENGINE_HEATER_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO49) +#define GPIO_GLOW_PLUG_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO27) +#define GPIO_SOLENOID_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO48) +#define GPIO_FUEL_PUMP_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO26) +#define GPIO_COOLANT_PUMP_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO52) +#define GPIO_FAN1_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO50) +#define GPIO_FAN2_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO51) + +// ChipSelect Port +#define GPIO_ENGINE_HEATER_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO49 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1)); +#define GPIO_GLOW_PLUG_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO27 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO27 = 1)); +#define GPIO_SOLENOID_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO48 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1)); +#define GPIO_FUEL_PUMP_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO26 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO26 = 1)); +#define GPIO_COOLANT_PUMP_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO52 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1)); +#define GPIO_FAN1_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO50 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1)); +#define GPIO_FAN2_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO51 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1)); + +// Pannel LED Port +#define GPIO_CPU_LED_STOP(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO12 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO12 = 1)); +#define GPIO_CPU_LED_FAULT(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO14 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO14 = 1)); +#define GPIO_CPU_LED_OPERATION(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO13 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO13 = 1)); + +#define GPIO_OLED_RESET(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO37 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1)); + +#define GPIO_FAULT_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO55 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1)); +#define GPIO_EMERGENCY_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO56 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1)); +#define GPIO_STOP_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO57 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1)); +#define GPIO_START_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO58 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1)); + +#define GPIO_POWER_HOLD(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO65 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1)); +#define GPIO_CPU_LED_COM_FAULT_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO68 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1)); +#define GPIO_CPU_LED_COM_RUN_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO69 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1)); +#define GPIO_CPU_LED_COM_STA_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO70 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1)); + +/* Comment Description + * [!] : + * [?] : ʿ + * [*] : Ǻ + */ + +/* Firmware (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // ȣȯ ʴ ȭ , ȭ +#define FIRMWARE_VERSION_MINOR (0) // ȣȯ Ǹ鼭 ο , ǰų +#define FIRMWARE_VERSION_PATCH (5) // ȣȯ Ǹ鼭 , Ȱ ˾ Ҽ + +/* Version History + * [0.0.1] : DCU Ʈ + * [0.0.2] : DCU ߿ ž + * [0.0.3] : OLED XINTF(BUS) ̺ + * [0.0.4] : OLED ǥ ȭ + * [0.0.5] : CAN-B Ȯ + */ + +#define DEBUG_MENU_PASSWORD {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10U) +#define TIME_10MS (100U) +#define TIME_20MS (200U) +#define TIME_50MS (500U) +#define TIME_100MS (1000U) +#define TIME_500MS (5000U) +#define TIME_1SEC (10000U) + +// 0A ذ 450(0.33V), +/- 150 +#define SENSOR_OFFSET_REF 450 +#define SENSOR_TOLERANCE 150 +#define SENSOR_MIN_LIMIT (SENSOR_OFFSET_REF - SENSOR_TOLERANCE) // 300 +#define SENSOR_MAX_LIMIT (SENSOR_OFFSET_REF + SENSOR_TOLERANCE) // 600 + +#define TIME_OVER (1U) + +#define ABS(x) ((x) < 0 ? -(x) : (x)) + +enum +{ + TIMER_01MS = 0, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0, + SOFTTIMER_WAIT_POPUP, + SOFTTIMER_WAIT_APU_STOP, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef struct ClassPowerOnCheckValue +{ + Uint16 EngineHeaterSensor : 1; + Uint16 GlowPlugSensor : 1; + Uint16 SolenoidSensor : 1; + Uint16 FuelPumpSensor : 1; + Uint16 CoolantPumpSensor : 1; + Uint16 Fan1Sensor : 1; + Uint16 Fan2Sensor : 1; +} CPowerOnCheckValue; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiPassword[4]; + Uint16 uiAlarmOccured; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenence; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd : 4; + Uint16 rsvd_padding : 4; + } GcuCommand; + struct + { + Uint16 EngineStart : 1; + Uint16 EngineStop : 1; + Uint16 rsvd : 2; + Uint16 RpmSetPoint : 2; + Uint16 Override : 1; + Uint16 Emergency : 1; + } EcuCommand; + struct + { + Uint16 CarComputer : 1; + Uint16 Gcu : 1; + Uint16 Ecu : 1; + } Conection; + struct + { + Uint16 ManualCranking : 1; + Uint16 LampTest : 1; + Uint16 KeyTest : 1; + } Maintenence; +} CGeneralOperValue; + +Uint16 CSoftWaitCountProcedure(Uint16 ucIndex, Uint32 ulWaitTime); +void CActiveChipSelect(Uint16 Active); + +extern CGeneralOperValue GeneralOperValue; +extern CPowerOnCheckValue PowerOnCheckValue; + +#endif /* SOURCE_MAIN_H_ */ diff --git a/.staticdata/K2DCU/fs/fs_hash_map.json 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설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: K2APU_DCU\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\\Source\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\\Source\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\\Source\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\\Source\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\\Source\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"2026-01-13T00:04:02.857Z\",\n\n \"last_capture_time\": \"2026-01-13T00:06:33.760Z\"\n\n}" +} \ No newline at end of file diff --git a/.staticdata/artifacts.zip b/.staticdata/artifacts.zip new file mode 100644 index 0000000..a331d10 Binary files /dev/null and b/.staticdata/artifacts.zip differ diff --git a/.staticdata/cstrace.json b/.staticdata/cstrace.json new file mode 100644 index 0000000..2f745f4 --- /dev/null +++ b/.staticdata/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_5_04_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v005\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v005" + ] + } +} \ No newline at end of file diff --git a/.staticdata/error.json b/.staticdata/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/.staticdata/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/.staticdata/exclude_project.json b/.staticdata/exclude_project.json new file mode 100644 index 0000000..1f5e5dd --- /dev/null +++ b/.staticdata/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "K2APU_DCU", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/.staticdata/preinclude/gnu_preinclude.h b/.staticdata/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/.staticdata/preinclude/recent_preinclude_c.h b/.staticdata/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/.staticdata/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/.staticdata/preinclude/recent_preinclude_cpp.h b/.staticdata/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/.staticdata/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/DSP2833x_Headers_nonBIOS.cmd b/DSP2833x_Headers_nonBIOS.cmd new file mode 100644 index 0000000..3089f15 --- /dev/null +++ b/DSP2833x_Headers_nonBIOS.cmd @@ -0,0 +1,183 @@ +/* +// TI File $Revision: /main/8 $ +// Checkin $Date: June 2, 2008 11:12:24 $ +//########################################################################### +// +// FILE: DSP2833x_Headers_nonBIOS.cmd +// +// TITLE: DSP2833x Peripheral registers linker command file +// +// DESCRIPTION: +// +// This file is for use in Non-BIOS applications. +// +// Linker command file to place the peripheral structures +// used within the DSP2833x headerfiles into the correct memory +// mapped locations. +// +// This version of the file includes the PieVectorTable structure. +// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file +// which does not include the PieVectorTable structure. +// +//########################################################################### +// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $ +// $Release Date: August 1, 2008 $ +//########################################################################### +*/ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ + FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ + CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ + + ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ + + XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ + + DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ + + MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ + + ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ + ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ + ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ + ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ + ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ + + ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ + ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ + ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ + ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ + ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ + + EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ + + ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ + + GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ + GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ + GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ + + SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ + SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ + SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ + XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ + + ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ + + SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ + + SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ + + I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ + + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ + + PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ +} + + +SECTIONS +{ + PieVectTableFile : > PIE_VECT, PAGE = 1 + +/*** Peripheral Frame 0 Register Structures ***/ + DevEmuRegsFile : > DEV_EMU, PAGE = 1 + FlashRegsFile : > FLASH_REGS, PAGE = 1 + CsmRegsFile : > CSM, PAGE = 1 + AdcMirrorFile : > ADC_MIRROR, PAGE = 1 + XintfRegsFile : > XINTF, PAGE = 1 + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + DmaRegsFile : > DMA, PAGE = 1 + +/*** Peripheral Frame 3 Register Structures ***/ + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + +/*** Peripheral Frame 1 Register Structures ***/ + ECanaRegsFile : > ECANA, PAGE = 1 + ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 + ECanaMboxesFile : > ECANA_MBOX PAGE = 1 + ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 + ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 + + ECanbRegsFile : > ECANB, PAGE = 1 + ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 + ECanbMboxesFile : > ECANB_MBOX PAGE = 1 + ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 + ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 + + EPwm1RegsFile : > EPWM1 PAGE = 1 + EPwm2RegsFile : > EPWM2 PAGE = 1 + EPwm3RegsFile : > EPWM3 PAGE = 1 + EPwm4RegsFile : > EPWM4 PAGE = 1 + EPwm5RegsFile : > EPWM5 PAGE = 1 + EPwm6RegsFile : > EPWM6 PAGE = 1 + + ECap1RegsFile : > ECAP1 PAGE = 1 + ECap2RegsFile : > ECAP2 PAGE = 1 + ECap3RegsFile : > ECAP3 PAGE = 1 + ECap4RegsFile : > ECAP4 PAGE = 1 + ECap5RegsFile : > ECAP5 PAGE = 1 + ECap6RegsFile : > ECAP6 PAGE = 1 + + EQep1RegsFile : > EQEP1 PAGE = 1 + EQep2RegsFile : > EQEP2 PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 + GpioDataRegsFile : > GPIODAT PAGE = 1 + GpioIntRegsFile : > GPIOINT PAGE = 1 + +/*** Peripheral Frame 2 Register Structures ***/ + SysCtrlRegsFile : > SYSTEM, PAGE = 1 + SpiaRegsFile : > SPIA, PAGE = 1 + SciaRegsFile : > SCIA, PAGE = 1 + XIntruptRegsFile : > XINTRUPT, PAGE = 1 + AdcRegsFile : > ADC, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + +/*** Code Security Module Register Structures ***/ + CsmPwlFile : > CSM_PWL, PAGE = 1 + +/*** Device Part ID Register Structures ***/ + PartIdRegsFile : > PARTID, PAGE = 1 + +} + + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/Description/APU_CONTROLLER_260320.pdf b/Description/APU_CONTROLLER_260320.pdf new file mode 100644 index 0000000..4c95fb3 Binary files /dev/null and b/Description/APU_CONTROLLER_260320.pdf differ diff --git a/Description/Calibration.exe b/Description/Calibration.exe new file mode 100644 index 0000000..544634f Binary files /dev/null and b/Description/Calibration.exe differ diff --git a/Description/font.txt b/Description/font.txt new file mode 100644 index 0000000..59980ba --- /dev/null +++ b/Description/font.txt @@ -0,0 +1,100 @@ + +const unsigned char EngFontTable[96][9] = { +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // +{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ! +{ 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " +{ 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // # +{ 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $ +{ 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // % +{ 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // & +{ 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' +{ 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // ( +{ 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // ) +{ 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // * +{ 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // + +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // , +{ 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // - +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // . +{ 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // / +{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0 +{ 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1 +{ 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2 +{ 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3 +{ 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4 +{ 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5 +{ 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6 +{ 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7 +{ 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8 +{ 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9 +{ 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // : +{ 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ; +{ 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // < +{ 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // = +{ 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // > +{ 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ? +{ 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @ +{ 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A +{ 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B +{ 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C +{ 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D +{ 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E +{ 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F +{ 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G +{ 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H +{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I +{ 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J +{ 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K +{ 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L +{ 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M +{ 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N +{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O +{ 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P +{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q +{ 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R +{ 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S +{ 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T +{ 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U +{ 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V +{ 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W +{ 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X +//{ 0x45, 0x14, 0x4A, 0x28, 0xA1, 0x04, 0x10, 0x40, 0x00 }, // old Y is similer V. +{ 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // new version Y +{ 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z +{ 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [ +{ 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON) +{ 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ] +{ 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^ +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _ +{ 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ` +{ 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a +{ 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b +{ 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c +{ 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d +{ 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e +{ 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f +{ 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g +{ 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h +{ 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i +{ 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j +{ 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k +{ 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l +{ 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m +{ 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n +{ 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o +{ 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p +{ 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q +{ 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r +{ 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s +{ 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t +{ 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u +{ 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v +{ 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w +{ 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x +{ 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y +{ 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z +{ 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // { +{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // | +{ 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // } +{ 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~ +{ 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, //  +}; \ No newline at end of file diff --git a/F2833x_nonBIOS_flash.cmd b/F2833x_nonBIOS_flash.cmd new file mode 100644 index 0000000..f915e43 --- /dev/null +++ b/F2833x_nonBIOS_flash.cmd @@ -0,0 +1,147 @@ +/*############################################################################ + + FILE: DSP2833x_nonBIOS_flash.cmd + + DESCRIPTION: Linker allocation for all sections. +############################################################################ + Author: Tim Love + Release Date: March 2008 +############################################################################*/ + + +MEMORY +{ +PAGE 0: /* Program Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ + + ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ + RAM_L0L1L2L3: origin = 0x008000, length = 0x006000 /* on-chip RAM */ + OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ + ZONE6 : origin = 0x100000, length = 0x100000 /* XINTF zone 6 */ + ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */ + FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */ + FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */ + FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */ + FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */ + FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */ + FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */ + FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */ + CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ + BEGIN_FLASH : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ + CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ + ADC_CAL : origin = 0x380080, length = 0x000009 /* Part of TI OTP */ + IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ + IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ + FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ + ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ + RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ + VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ + + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ + /* Registers remain on PAGE1 */ + + //RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */ + //BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */ + //RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */ + RAM0M1 : origin = 0x000000, length = 0x000800 /* M0+RSVD+M1 */ + RAML4 : origin = 0x00E000, length = 0x001000 + //RAML4 : origin = 0x00D000, length = 0x002000 /* on-chip RAM block L4 */ + RAML5 : origin = 0x00F000, length = 0x000400 /* on-chip RAM block L5 */ + RAML6 : origin = 0x00F400, length = 0x000400 /* on-chip RAM block L6 */ + RAML7 : origin = 0x00F800, length = 0x000400 /* on-chip RAM block L7 */ + ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ + ZONE6COM : origin = 0x100000, length = 0x000001 /* XINTF zone 6 */ + ZONE6DAT : origin = 0x100001, length = 0x000001 /* XINTF zone 6 */ +} + +/**************************************************************/ +/* Link all user defined sections */ +/**************************************************************/ +SECTIONS +{ + +/*** Code Security Password Locations ***/ + csmpasswds : > CSM_PWL PAGE = 0 + csm_rsvd : > CSM_RSVD PAGE = 0 + +/*** User Defined Sections ***/ + codestart : > BEGIN_FLASH, PAGE = 0 /* Used by file CodeStartBranch.asm */ + wddisable : > FLASHA, PAGE = 0 + copysections : > FLASHA, PAGE = 0 + + /* Allocate IQ math areas: */ + IQmath : > FLASHC PAGE = 0 /* Math Code */ + IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD + IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD + FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD + + /* Allocate DMA-accessible RAM sections: */ + DMARAML4 : > RAML4, PAGE = 1 + DMARAML5 : > RAML5, PAGE = 1 + DMARAML6 : > RAML6, PAGE = 1 + DMARAML7 : > RAML7, PAGE = 1 + + /* Allocate 0x400 of XINTF Zone 7 to storing data */ + ZONE7DATA : > ZONE7B, PAGE = 1 + ZONE6_COM : > ZONE6COM, PAGE = 1 + ZONE6_DAT : > ZONE6DAT, PAGE = 1 + +/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ + .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD + +/* .reset is a standard section used by the compiler. It contains the */ +/* the address of the start of _c_int00 for C Code. /* +/* When using the boot ROM this section and the CPU vector */ +/* table is not needed. Thus the default type is set here to */ +/* DSECT */ + .reset : > RESET, PAGE = 0, TYPE = DSECT + vectors : > VECTORS PAGE = 0, TYPE = DSECT + +/*** Uninitialized Sections ***/ + .stack : > RAM0M1, PAGE = 1 + + .ebss : > RAML4, PAGE = 1 + + .esysmem : > RAM0M1, PAGE = 1 + +/*** Initialized Sections ***/ + .cinit : LOAD = FLASHA, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_cinit_loadstart), + RUN_START(_cinit_runstart), + SIZE(_cinit_size) + + .const : LOAD = FLASHA, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_const_loadstart), + RUN_START(_const_runstart), + SIZE(_const_size) + + .econst : LOAD = FLASHA, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_econst_loadstart), + RUN_START(_econst_runstart), + SIZE(_econst_size) + + .pinit : LOAD = FLASHA, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_pinit_loadstart), + RUN_START(_pinit_runstart), + SIZE(_pinit_size) + + .switch : LOAD = FLASHA, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_switch_loadstart), + RUN_START(_switch_runstart), + SIZE(_switch_size) + + .text : LOAD = FLASHC, PAGE = 0 /* can be ROM */ + RUN = RAM_L0L1L2L3, PAGE = 0 /* must be CSM secured RAM */ + LOAD_START(_text_loadstart), + RUN_START(_text_runstart), + SIZE(_text_size) +} + +/******************* end of file ************************/ diff --git a/Lib/Src/DSP2833x_Adc.c b/Lib/Src/DSP2833x_Adc.c new file mode 100644 index 0000000..1929e45 --- /dev/null +++ b/Lib/Src/DSP2833x_Adc.c @@ -0,0 +1,99 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: October 23, 2007 13:34:09 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// Defines +// +#define ADC_usDELAY 5000L + +// +// InitAdc - This function initializes ADC to a known state. +// +void +InitAdc(void) +{ + extern void DSP28x_usDelay(Uint32 Count); + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from + // TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. See the device data manual and/or + // the ADC Reference Manual for more information. + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + // + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and + // ADC core. Before the first conversion is performed a 5ms delay must be + // observed after power up to give all analog circuits time to power up + // and settle + // + + // + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + // + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(ADC_usDELAY); // Delay before converting ADC channels +} + +// +// End of file +// + diff --git a/Lib/Src/DSP2833x_CpuTimers.c b/Lib/Src/DSP2833x_CpuTimers.c new file mode 100644 index 0000000..ae9c20d --- /dev/null +++ b/Lib/Src/DSP2833x_CpuTimers.c @@ -0,0 +1,199 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 9, 2009 10:51:59 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +// NOTES: CpuTimer2 is reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these this timer in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Defines +// +struct CPUTIMER_VARS CpuTimer0; + +// +// When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. +// +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void +InitCpuTimers(void) +{ + // + // CPU Timer 0 - Initialize address pointers to respective timer registers + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT) + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer0.InterruptCount = 0; + + // + // CpuTimer2 is reserved for DSP BIOS & other RTOS + // Do not use this timer if you ever plan on integrating + // DSP-BIOS or another realtime OS. + // + + // + // Initialize address pointers to respective timer registers + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Make sure timers are stopped + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" is entered as +// "MHz" and the period in "uSeconds". The timer is held in the stopped state +// after configuration. +// +void +ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT) + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register + // + + // + // 1 = Stop timer, 0 = Start/Restart Timer + // + Timer->RegsAddr->TCR.bit.TSS = 1; + + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 1; + Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run + + // + // 0 = Disable/ 1 = Enable Timer Interrupt + // + Timer->RegsAddr->TCR.bit.TIE = 1; + + // + // Reset interrupt counter + // + Timer->InterruptCount = 0; +} + +// +// End of File +// + diff --git a/Lib/Src/DSP2833x_DefaultIsr.c b/Lib/Src/DSP2833x_DefaultIsr.c new file mode 100644 index 0000000..b0a52d0 --- /dev/null +++ b/Lib/Src/DSP2833x_DefaultIsr.c @@ -0,0 +1,2024 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: January 14, 2008 11:17:46 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.c +// +// TITLE: DSP2833x Device Default Interrupt Service Routines. +// +// This file contains shell ISR routines for the 2833x PIE vector table. +// Typically these shell ISR routines can be used to populate the entire PIE +// vector table during device debug. In this manner if an interrupt is taken +// during firmware development, there will always be an ISR to catch it. +// +// As development progresses, these ISR routines can be eliminated and replaced +// with the user's own ISR routines for each interrupt. Since these shell ISRs +// include infinite loops they will typically not be included as-is in the final +// production firmware. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// INT13_ISR - Connected to INT13 of CPU (use MINT13 mask): +// Note CPU-Timer1 is reserved for TI use, however XINT13 +// ISR can be used by the user. +// +interrupt void +INT13_ISR(void) // INT13 or CPU-Timer1 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT14_ISR - Note CPU-Timer2 is reserved for TI use. +// +interrupt void +INT14_ISR(void) // CPU-Timer2 +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DATALOG_ISR - Datalogging interrupt +// +interrupt void +DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOSINT_ISR - RTOS interrupt +// +interrupt void +RTOSINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EMUINT_ISR - Emulation interrupt +// +interrupt void +EMUINT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// NMI_ISR - Non-maskable interrupt +// +interrupt void +NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ILLEGAL_ISR - Illegal operation TRAP +// +interrupt void +ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER1_ISR - User Defined trap 1 +// +interrupt void +USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER2_ISR - User Defined trap 2 +// +interrupt void +USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER3_ISR - User Defined trap 3 +// +interrupt void +USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER4_ISR - User Defined trap 4 +// +interrupt void +USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER5_ISR - User Defined trap 5 +// +interrupt void +USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER6_ISR - User Defined trap 6 +// +interrupt void +USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER7_ISR - User Defined trap 7 +// +interrupt void +USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER8_ISR - User Defined trap 8 +// +interrupt void +USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER9_ISR - User Defined trap 9 +// +interrupt void +USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER10_ISR - User Defined trap 10 +// +interrupt void +USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER11_ISR - User Defined trap 11 +// +interrupt void +USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// USER12_ISR - User Defined trap 12 +// +interrupt void +USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 1 - MUXed into CPU INT1 +// + +// +// SEQ1INT_ISR - INT1.1 +// +interrupt void +SEQ1INT_ISR(void) //SEQ1 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SEQ2INT_ISR - INT1.2 +// +interrupt void +SEQ2INT_ISR(void) //SEQ2 ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this interrupt + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + + asm(" ESTOP0"); + for(;;); +} + +// +// INT1.3 - Reserved +// + +// +// XINT1_ISR - INT1.4 +// +interrupt void +XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT2_ISR - INT1.5 +// +interrupt void +XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ADCINT_ISR - INT1.6 +// +interrupt void +ADCINT_ISR(void) // ADC +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// TINT0_ISR - INT1.7 +// +interrupt void +TINT0_ISR(void) // CPU-Timer 0 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// WAKEINT_ISR - INT1.8 +// +interrupt void +WAKEINT_ISR(void) // WD, LOW Power +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 2 - MUXed into CPU INT2 +// + +// +// EPWM1_TZINT_ISR - INT2.1 +// +interrupt void +EPWM1_TZINT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_TZINT_ISR - INT2.2 +// +interrupt void +EPWM2_TZINT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_TZINT_ISR - INT2.3 +// +interrupt void +EPWM3_TZINT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge + // this interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_TZINT_ISR - INT2.4 +// +interrupt void +EPWM4_TZINT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_TZINT_ISR - INT2.5 +// +interrupt void +EPWM5_TZINT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_TZINT_ISR - INT2.6 +// +interrupt void +EPWM6_TZINT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT2.7 - Reserved +// + +// +// INT2.8 - Reserved +// + +// +// PIE Group 3 - MUXed into CPU INT3 +// + +// +// EPWM1_INT_ISR - INT 3.1 +// +interrupt void +EPWM1_INT_ISR(void) // EPWM-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM2_INT_ISR - INT3.2 +// +interrupt void +EPWM2_INT_ISR(void) // EPWM-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM3_INT_ISR - INT3.3 +// +interrupt void +EPWM3_INT_ISR(void) // EPWM-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM4_INT_ISR - INT3.4 +// +interrupt void +EPWM4_INT_ISR(void) // EPWM-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM5_INT_ISR - INT3.5 +// +interrupt void +EPWM5_INT_ISR(void) // EPWM-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EPWM6_INT_ISR - INT3.6 +// +interrupt void +EPWM6_INT_ISR(void) // EPWM-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT3.7 - Reserved +// + +// +// INT3.8 - Reserved +// + +// +// PIE Group 4 - MUXed into CPU INT4 +// + +// +// ECAP1_INT_ISR - INT 4.1 +// +interrupt void +ECAP1_INT_ISR(void) // ECAP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP2_INT_ISR - INT4.2 +// +interrupt void +ECAP2_INT_ISR(void) // ECAP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP3_INT_ISR - INT4.3 +// +interrupt void +ECAP3_INT_ISR(void) // ECAP-3 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP4_INT_ISR - INT4.4 +// +interrupt void +ECAP4_INT_ISR(void) // ECAP-4 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP5_INT_ISR - INT4.5 +// +interrupt void +ECAP5_INT_ISR(void) // ECAP-5 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAP6_INT_ISR - INT4.6 +// +interrupt void +ECAP6_INT_ISR(void) // ECAP-6 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT4.7 - Reserved +// + +// +// INT4.8 - Reserved +// + +// +// PIE Group 5 - MUXed into CPU INT5 +// + +// +// EQEP1_INT_ISR - INT 5.1 +// +interrupt void +EQEP1_INT_ISR(void) // EQEP-1 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// EQEP2_INT_ISR - INT5.2 +// +interrupt void +EQEP2_INT_ISR(void) // EQEP-2 +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT5.3 - Reserved +// + +// +// INT5.4 - Reserved +// + +// +// INT5.5 - Reserved +// + +// +// INT5.6 - Reserved +// + +// +// INT5.7 - Reserved +// + +// +// INT5.8 - Reserved +// + +// +// PIE Group 6 - MUXed into CPU INT6 +// + +// +// SPIRXINTA_ISR - INT6.1 +// +interrupt void +SPIRXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SPITXINTA_ISR - INT6.2 +// +interrupt void +SPITXINTA_ISR(void) // SPI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTB_ISR - INT6.3 +// +interrupt void +MRINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTB_ISR - INT6.4 +// +interrupt void +MXINTB_ISR(void) // McBSP-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MRINTA_ISR - INT6.5 +// +interrupt void +MRINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// MXINTA_ISR - INT6.6 +// +interrupt void +MXINTA_ISR(void) // McBSP-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT6.7 - Reserved +// + +// +// INT6.8 - Reserved +// + +// +// PIE Group 7 - MUXed into CPU INT7 +// + +// +// DINTCH1_ISR - INT7.1 +// +interrupt void +DINTCH1_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH2_ISR - INT7.2 +// +interrupt void +DINTCH2_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH3_ISR - INT7.3 +// +interrupt void +DINTCH3_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH4_ISR - INT7.4 +// +interrupt void +DINTCH4_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH5_ISR - INT7.5 +// +interrupt void +DINTCH5_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// DINTCH6_ISR - INT7.6 +// +interrupt void +DINTCH6_ISR(void) // DMA +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT7.7 - Reserved +// + +// +// INT7.8 - Reserved +// + +// +// PIE Group 8 - MUXed into CPU INT8 +// + +// +// I2CINT1A_ISR - INT8.1 +// +interrupt void +I2CINT1A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// I2CINT2A_ISR - INT8.2 +// +interrupt void +I2CINT2A_ISR(void) // I2C-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.3 - Reserved +// + +// +// INT8.4 - Reserved +// + +// +// SCIRXINTC_ISR - INT8.5 +// +interrupt void +SCIRXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTC_ISR - INT8.6 +// +interrupt void +SCITXINTC_ISR(void) // SCI-C +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT8.7 - Reserved +// + +// +// INT8.8 - Reserved +// + +// +// PIE Group 9 - MUXed into CPU INT9 +// + +// +// SCIRXINTA_ISR - INT9.1 +// +interrupt void +SCIRXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTA_ISR - INT9.2 +// +interrupt void +SCITXINTA_ISR(void) // SCI-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCIRXINTB_ISR - INT9.3 +// +interrupt void +SCIRXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// SCITXINTB_ISR - INT9.4 +// +interrupt void +SCITXINTB_ISR(void) // SCI-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTA_ISR - INT9.5 +// +interrupt void +ECAN0INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTA_ISR - INT9.6 +// +interrupt void +ECAN1INTA_ISR(void) // eCAN-A +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN0INTB_ISR - INT9.7 +// +interrupt void +ECAN0INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// ECAN1INTB_ISR - INT9.8 +// +interrupt void +ECAN1INTB_ISR(void) // eCAN-B +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// PIE Group 10 - MUXed into CPU INT10 +// + +// +// INT10.1 - Reserved +// + +// +// INT10.2 - Reserved +// + +// +// INT10.3 - Reserved +// + +// +// INT10.4 - Reserved +// + +// +// INT10.5 - Reserved +// + +// +// INT10.6 - Reserved +// + +// +// INT10.7 - Reserved +// + +// +// INT10.8 - Reserved +// + +// +// PIE Group 11 - MUXed into CPU INT11 +// + +// +// INT11.1 - Reserved +// + +// +// INT11.2 - Reserved +// + +// +// INT11.3 - Reserved +// + +// +// INT11.4 - Reserved +// + +// +// INT11.5 - Reserved +// + +// +// INT11.6 - Reserved +// + +// +// INT11.7 - Reserved +// + +// +// INT11.8 - Reserved +// + +// +// PIE Group 12 - MUXed into CPU INT12 +// + +// +// XINT3_ISR - INT12.1 +// +interrupt void +XINT3_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT4_ISR - INT12.2 +// +interrupt void +XINT4_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT5_ISR - INT12.3 +// +interrupt void +XINT5_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT6_ISR - INT12.4 +// +interrupt void +XINT6_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// XINT7_ISR - INT12.5 +// +interrupt void +XINT7_ISR(void) // External Interrupt +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// INT12.6 - Reserved +// + +// +// LVF_ISR - INT12.7 +// +interrupt void +LVF_ISR(void) // Latched overflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// LUF_ISR - INT12.8 +// +interrupt void +LUF_ISR(void) // Latched underflow +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, acknowledge this + // interrupt + // + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch All Default ISRs: +// + +// +// PIE_RESERVED - Reserved space. For test. +// +interrupt void +PIE_RESERVED(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// rsvd_ISR - For test +// +interrupt void +rsvd_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// End of file +// + diff --git a/Lib/Src/DSP2833x_GlobalVariableDefs.c b/Lib/Src/DSP2833x_GlobalVariableDefs.c new file mode 100644 index 0000000..38a0341 --- /dev/null +++ b/Lib/Src/DSP2833x_GlobalVariableDefs.c @@ -0,0 +1,407 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: June 2, 2008 11:12:33 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalVariableDefs.c +// +// TITLE: DSP2833x Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File + +// +// Define Global Peripheral Variables +// +#ifdef __cplusplus +#pragma DATA_SECTION("AdcRegsFile") +#else +#pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); +#endif +volatile struct ADC_REGS AdcRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcMirrorFile") +#else +#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile"); +#endif +volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmPwlFile") +#else +#pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); +#endif +volatile struct CSM_PWL CsmPwl; + +#ifdef __cplusplus +#pragma DATA_SECTION("CsmRegsFile") +#else +#pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); +#endif +volatile struct CSM_REGS CsmRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DevEmuRegsFile") +#else +#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); +#endif +volatile struct DEV_EMU_REGS DevEmuRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaRegsFile") +#else +#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); +#endif +volatile struct ECAN_REGS ECanaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMboxesFile") +#else +#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanaMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaLAMRegsFile") +#else +#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanaLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanaMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanaMOTORegsFile") +#else +#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanaMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbRegsFile") +#else +#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile"); +#endif +volatile struct ECAN_REGS ECanbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMboxesFile") +#else +#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile"); +#endif +volatile struct ECAN_MBOXES ECanbMboxes; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbLAMRegsFile") +#else +#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile"); +#endif +volatile struct LAM_REGS ECanbLAMRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTSRegsFile") +#else +#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile"); +#endif +volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECanbMOTORegsFile") +#else +#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile"); +#endif +volatile struct MOTO_REGS ECanbMOTORegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("GpioIntRegsFile") +#else +#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile"); +#endif +volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct MCBSP_REGS McbspaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PartIdRegsFile") +#else +#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile"); +#endif +volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("SysCtrlRegsFile") +#else +#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); +#endif +volatile struct SYS_CTRL_REGS SysCtrlRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("FlashRegsFile") +#else +#pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); +#endif +volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XIntruptRegsFile") +#else +#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); +#endif +volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("XintfRegsFile") +#else +#pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); +#endif +volatile struct XINTF_REGS XintfRegs; + +// +// End of file +// + diff --git a/Lib/Src/DSP2833x_PieCtrl.c b/Lib/Src/DSP2833x_PieCtrl.c new file mode 100644 index 0000000..0b46fcf --- /dev/null +++ b/Lib/Src/DSP2833x_PieCtrl.c @@ -0,0 +1,126 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:35 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.c +// +// TITLE: DSP2833x Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a known +// state. +// +void +InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU interrupts +// +void +EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// + diff --git a/Lib/Src/DSP2833x_PieVect.c b/Lib/Src/DSP2833x_PieVect.c new file mode 100644 index 0000000..8c8d479 --- /dev/null +++ b/Lib/Src/DSP2833x_PieVect.c @@ -0,0 +1,262 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:46:38 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.c +// +// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED, // 0 Reserved space + PIE_RESERVED, // 1 Reserved space + PIE_RESERVED, // 2 Reserved space + PIE_RESERVED, // 3 Reserved space + PIE_RESERVED, // 4 Reserved space + PIE_RESERVED, // 5 Reserved space + PIE_RESERVED, // 6 Reserved space + PIE_RESERVED, // 7 Reserved space + PIE_RESERVED, // 8 Reserved space + PIE_RESERVED, // 9 Reserved space + PIE_RESERVED, // 10 Reserved space + PIE_RESERVED, // 11 Reserved space + PIE_RESERVED, // 12 Reserved space + + // + // Non-Peripheral Interrupts + // + INT13_ISR, // XINT13 or CPU-Timer 1 + INT14_ISR, // CPU-Timer2 + DATALOG_ISR, // Datalogging interrupt + RTOSINT_ISR, // RTOS interrupt + EMUINT_ISR, // Emulation interrupt + NMI_ISR, // Non-maskable interrupt + ILLEGAL_ISR, // Illegal operation TRAP + USER1_ISR, // User Defined trap 1 + USER2_ISR, // User Defined trap 2 + USER3_ISR, // User Defined trap 3 + USER4_ISR, // User Defined trap 4 + USER5_ISR, // User Defined trap 5 + USER6_ISR, // User Defined trap 6 + USER7_ISR, // User Defined trap 7 + USER8_ISR, // User Defined trap 8 + USER9_ISR, // User Defined trap 9 + USER10_ISR, // User Defined trap 10 + USER11_ISR, // User Defined trap 11 + USER12_ISR, // User Defined trap 12 + + // + // Group 1 PIE Vectors + // + SEQ1INT_ISR, // 1.1 ADC + SEQ2INT_ISR, // 1.2 ADC + rsvd_ISR, // 1.3 + XINT1_ISR, // 1.4 + XINT2_ISR, // 1.5 + ADCINT_ISR, // 1.6 ADC + TINT0_ISR, // 1.7 Timer 0 + WAKEINT_ISR, // 1.8 WD, Low Power + + // + // Group 2 PIE Vectors + // + EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone + EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone + EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone + EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone + EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone + EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone + rsvd_ISR, // 2.7 + rsvd_ISR, // 2.8 + + // + // Group 3 PIE Vectors + // + EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt + EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt + EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt + EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt + EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt + EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt + rsvd_ISR, // 3.7 + rsvd_ISR, // 3.8 + + // + // Group 4 PIE Vectors + // + ECAP1_INT_ISR, // 4.1 ECAP-1 + ECAP2_INT_ISR, // 4.2 ECAP-2 + ECAP3_INT_ISR, // 4.3 ECAP-3 + ECAP4_INT_ISR, // 4.4 ECAP-4 + ECAP5_INT_ISR, // 4.5 ECAP-5 + ECAP6_INT_ISR, // 4.6 ECAP-6 + rsvd_ISR, // 4.7 + rsvd_ISR, // 4.8 + + // + // Group 5 PIE Vectors + // + EQEP1_INT_ISR, // 5.1 EQEP-1 + EQEP2_INT_ISR, // 5.2 EQEP-2 + rsvd_ISR, // 5.3 + rsvd_ISR, // 5.4 + rsvd_ISR, // 5.5 + rsvd_ISR, // 5.6 + rsvd_ISR, // 5.7 + rsvd_ISR, // 5.8 + + // + // Group 6 PIE Vectors + // + SPIRXINTA_ISR, // 6.1 SPI-A + SPITXINTA_ISR, // 6.2 SPI-A + MRINTA_ISR, // 6.3 McBSP-A + MXINTA_ISR, // 6.4 McBSP-A + MRINTB_ISR, // 6.5 McBSP-B + MXINTB_ISR, // 6.6 McBSP-B + rsvd_ISR, // 6.7 + rsvd_ISR, // 6.8 + + // + // Group 7 PIE Vectors + // + DINTCH1_ISR, // 7.1 DMA channel 1 + DINTCH2_ISR, // 7.2 DMA channel 2 + DINTCH3_ISR, // 7.3 DMA channel 3 + DINTCH4_ISR, // 7.4 DMA channel 4 + DINTCH5_ISR, // 7.5 DMA channel 5 + DINTCH6_ISR, // 7.6 DMA channel 6 + rsvd_ISR, // 7.7 + rsvd_ISR, // 7.8 + + // + // Group 8 PIE Vectors + // + I2CINT1A_ISR, // 8.1 I2C + I2CINT2A_ISR, // 8.2 I2C + rsvd_ISR, // 8.3 + rsvd_ISR, // 8.4 + SCIRXINTC_ISR, // 8.5 SCI-C + SCITXINTC_ISR, // 8.6 SCI-C + rsvd_ISR, // 8.7 + rsvd_ISR, // 8.8 + + // + // Group 9 PIE Vectors + // + SCIRXINTA_ISR, // 9.1 SCI-A + SCITXINTA_ISR, // 9.2 SCI-A + SCIRXINTB_ISR, // 9.3 SCI-B + SCITXINTB_ISR, // 9.4 SCI-B + ECAN0INTA_ISR, // 9.5 eCAN-A + ECAN1INTA_ISR, // 9.6 eCAN-A + ECAN0INTB_ISR, // 9.7 eCAN-B + ECAN1INTB_ISR, // 9.8 eCAN-B + + // + // Group 10 PIE Vectors + // + rsvd_ISR, // 10.1 + rsvd_ISR, // 10.2 + rsvd_ISR, // 10.3 + rsvd_ISR, // 10.4 + rsvd_ISR, // 10.5 + rsvd_ISR, // 10.6 + rsvd_ISR, // 10.7 + rsvd_ISR, // 10.8 + + // + // Group 11 PIE Vectors + // + rsvd_ISR, // 11.1 + rsvd_ISR, // 11.2 + rsvd_ISR, // 11.3 + rsvd_ISR, // 11.4 + rsvd_ISR, // 11.5 + rsvd_ISR, // 11.6 + rsvd_ISR, // 11.7 + rsvd_ISR, // 11.8 + + // + // Group 12 PIE Vectors + // + XINT3_ISR, // 12.1 + XINT4_ISR, // 12.2 + XINT5_ISR, // 12.3 + XINT6_ISR, // 12.4 + XINT7_ISR, // 12.5 + rsvd_ISR, // 12.6 + LVF_ISR, // 12.7 + LUF_ISR, // 12.8 +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + volatile Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 128; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// + diff --git a/Lib/Src/DSP2833x_SysCtrl.c b/Lib/Src/DSP2833x_SysCtrl.c new file mode 100644 index 0000000..59379b2 --- /dev/null +++ b/Lib/Src/DSP2833x_SysCtrl.c @@ -0,0 +1,459 @@ +// TI File $Revision: /main/8 $ +// Checkin $Date: April 15, 2009 09:54:05 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.c +// +// TITLE: DSP2833x Device System Control Initialization & Support Functions. +// +// DESCRIPTION: Example initialization of system resources. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "DSP2833x_Device.h" // Headerfile Include File +#include "DSP2833x_Examples.h" // Examples Include File + +// +// Functions that will be run from RAM need to be assigned to +// a different section. This section will then be mapped to a load and +// run address using the linker cmd file. +// +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #endif +#endif + +// +// InitSysCtrl - This function initializes the System Control registers to a +// known state. +// - Disables the watchdog +// - Set the PLLCR for proper SYSCLKOUT frequency +// - Set the pre-scaler for the high and low frequency peripheral clocks +// - Enable the clocks to the peripherals +// +void +InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + + // + // Initialize the PLL control: PLLCR and DIVSEL + // DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h + // + InitPll(DSP28_PLLCR,DSP28_DIVSEL); + + // + // Initialize the peripheral clocks + // + InitPeripheralClocks(); +} + +// +// InitFlash - This function initializes the Flash Control registers +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +void +InitFlash(void) +{ + EALLOW; + + // + // Enable Flash Pipeline mode to improve performance + // of code executed from Flash. + // + FlashRegs.FOPT.bit.ENPIPE = 1; + + // + // CAUTION + // Minimum waitstates required for the flash operating + // at a given CPU rate must be characterized by TI. + // Refer to the datasheet for the latest information. + // +#if CPU_FRQ_150MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; +#endif + +#if CPU_FRQ_100MHZ + // + // Set the Paged Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; + + // + // Set the Random Waitstate for the Flash + // + FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; + + // + // Set the Waitstate for the OTP + // + FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; +#endif + // + // CAUTION + // ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED + // + FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; + FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; + EDIS; + + // + // Force a pipeline flush to ensure that the write to + // the last register configured occurs before returning. + // + asm(" RPT #7 || NOP"); +} + +// +// ServiceDog - This function resets the watchdog timer. +// Enable this function for using ServiceDog in the application +// +void +ServiceDog(void) +{ + EALLOW; + SysCtrlRegs.WDKEY = 0x0055; + SysCtrlRegs.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void +DisableDog(void) +{ + EALLOW; + SysCtrlRegs.WDCR= 0x0068; + EDIS; +} + +// +// InitPll - This function initializes the PLLCR register. +// +void +InitPll(Uint16 val, Uint16 divsel) +{ + // + // Make sure the PLL is not running in limp mode + // + if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0) + { + // + // Missing external clock has been detected + // Replace this line with a call to an appropriate + // SystemShutdown(); function. + // + asm(" ESTOP0"); + } + + // + // DIVSEL MUST be 0 before PLLCR can be changed from + // 0x0000. It is set to 0 by an external reset XRSn + // This puts us in 1/4 + // + if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; + EDIS; + } + + // + // Change the PLLCR + // + if (SysCtrlRegs.PLLCR.bit.DIV != val) + { + EALLOW; + + // + // Before setting PLLCR turn off missing clock detect logic + // + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; + SysCtrlRegs.PLLCR.bit.DIV = val; + EDIS; + + // + // Optional: Wait for PLL to lock. + // During this time the CPU will switch to OSCCLK/2 until + // the PLL is stable. Once the PLL is stable the CPU will + // switch to the new PLL value. + // + // This time-to-lock is monitored by a PLL lock counter. + // + // Code is not required to sit and wait for the PLL to lock. + // However, if the code does anything that is timing critical, + // and requires the correct clock be locked, then it is best to + // wait until this switching has completed. + // + + // + // Wait for the PLL lock bit to be set. + // + + // + // The watchdog should be disabled before this loop, or fed within + // the loop via ServiceDog(). + // + + // + // Uncomment to disable the watchdog + // + DisableDog(); + + while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) + { + // + // Uncomment to service the watchdog + // + //ServiceDog(); + } + + EALLOW; + SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; + EDIS; + } + + // + // If switching to 1/2 + // + if((divsel == 1)||(divsel == 2)) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel; + EDIS; + } + + // + // NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF + // If switching to 1/1 + // * First go to 1/2 and let the power settle + // The time required will depend on the system, this is only an example + // * Then switch to 1/1 + // + if(divsel == 3) + { + EALLOW; + SysCtrlRegs.PLLSTS.bit.DIVSEL = 2; + DELAY_US(50L); + SysCtrlRegs.PLLSTS.bit.DIVSEL = 3; + EDIS; + } +} + +// +// InitPeripheralClocks - This function initializes the clocks to the +// peripheral modules. First the high and low clock prescalers are set +// Second the clocks are enabled to each peripheral. To reduce power, leave +// clocks to unused peripherals disabled +// +// Note: If a peripherals clock is not enabled then you cannot +// read or write to the registers for that peripheral +// +void +InitPeripheralClocks(void) +{ + EALLOW; + + // + // HISPCP/LOSPCP prescale register settings, normally it will be set to + // default values + // + SysCtrlRegs.HISPCP.all = 0x0001; + SysCtrlRegs.LOSPCP.all = 0x0002; + + // + // XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT + // XTIMCLK = SYSCLKOUT/2 + // + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + + // + // XCLKOUT = XTIMCLK/2 + // + XintfRegs.XINTCNF2.bit.CLKMODE = 1; + + // + // Enable XCLKOUT + // + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + + // + // Peripheral clock enables set for the selected peripherals. + // If you are not using a peripheral leave the clock off + // to save on power. + // + // Note: not all peripherals are available on all 2833x derivates. + // Refer to the datasheet for your particular device. + // + // This function is not written to be an example of efficient code. + // + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from TI + // reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. + // See the device data manual and/or the ADC Reference + // Manual for more information. + // + ADC_cal(); + + SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C + SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A + SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B + SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C + SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A + SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A + SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B + SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A + SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B + + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM + SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 + SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 + SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 + SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 + SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 + SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 + SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM + + SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 + SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4 + SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5 + SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6 + SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 + SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 + SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1 + SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2 + + SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1 + SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2 + + SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock + SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK + SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock + + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +Uint16 +CsmUnlock() +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + CsmRegs.KEY0 = 0xFFFF; + CsmRegs.KEY1 = 0xFFFF; + CsmRegs.KEY2 = 0xFFFF; + CsmRegs.KEY3 = 0xFFFF; + CsmRegs.KEY4 = 0xFFFF; + CsmRegs.KEY5 = 0xFFFF; + CsmRegs.KEY6 = 0xFFFF; + CsmRegs.KEY7 = 0xFFFF; + EDIS; + + // + // Perform a dummy read of the password locations if they match the key + // values, the CSM will unlock + // + temp = CsmPwl.PSWD0; + temp = CsmPwl.PSWD1; + temp = CsmPwl.PSWD2; + temp = CsmPwl.PSWD3; + temp = CsmPwl.PSWD4; + temp = CsmPwl.PSWD5; + temp = CsmPwl.PSWD6; + temp = CsmPwl.PSWD7; + + // + // If the CSM unlocked, return succes, otherwise return failure. + // + if (CsmRegs.CSMSCR.bit.SECURE == 0) + { + return STATUS_SUCCESS; + } + else + { + return STATUS_FAIL; + } +} + +// +// End of file +// + diff --git a/Lib/asm/DSP2833x_ADC_cal.asm b/Lib/asm/DSP2833x_ADC_cal.asm new file mode 100644 index 0000000..063e8ae --- /dev/null +++ b/Lib/asm/DSP2833x_ADC_cal.asm @@ -0,0 +1,74 @@ +;; TI File $Revision: /main/1 $ +;; Checkin $Date: July 30, 2007 10:29:23 $ +;;########################################################################### +;; +;; FILE: ADC_cal.asm +;; +;; TITLE: 2833x Boot Rom ADC Cal routine. +;; +;; Functions: +;; +;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and +;; ADCOFFTRIM registers +;; Notes: +;; +;;########################################################################### +;; $TI Release: 2833x/2823x Header Files V1.32 $ +;; $Release Date: June 28, 2010 $ +;; $Copyright: +;// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;;########################################################################### + + .def _ADC_cal + .asg "0x711C", ADCREFSEL_LOC + +;----------------------------------------------- +; _ADC_cal +;----------------------------------------------- +;----------------------------------------------- +; This is the ADC cal routine.This routine is programmed into +; reserved memory by the factory. 0xAAAA and 0xBBBB are place- +; holders for calibration data. +;The actual values programmed by TI are device specific. +; +; This function assumes that the clocks have been +; enabled to the ADC module. +;----------------------------------------------- + + .sect ".adc_cal" + +_ADC_cal + MOVW DP, #ADCREFSEL_LOC >> 6 + MOV @28, #0xAAAA ; actual value may not be 0xAAAA + MOV @29, #0xBBBB ; actual value may not be 0xBBBB + LRETR +;eof ---------- diff --git a/Lib/asm/DSP2833x_usDelay.asm b/Lib/asm/DSP2833x_usDelay.asm new file mode 100644 index 0000000..9d67b60 --- /dev/null +++ b/Lib/asm/DSP2833x_usDelay.asm @@ -0,0 +1,76 @@ +;// TI File $Revision: /main/4 $ +;// Checkin $Date: July 30, 2007 10:28:57 $ +;//########################################################################### +;// +;// FILE: DSP2833x_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// +;// To use this function: +;// +;// 1 - update the CPU clock speed in the DSP2833x_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed +;// +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the DSP2833x_Examples.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// +;// extern void Delay(long LoopCount); +;// +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// +;// Or as follows (if count is less then 16-bits): +;// +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;// +;//########################################################################### +;// $TI Release: DSP2833x Header Files V1.00 $ +;// $Release Date: September 7, 2007 $ +;//########################################################################### + + .def _DSP28x_usDelay + .text + + .global __DSP28x_usDelay +_DSP28x_usDelay: + SUB ACC,#1 + BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +;//=========================================================================== +;// End of file. +;//=========================================================================== diff --git a/Lib/asm/DSP28xxx_CodeStartBranch.asm b/Lib/asm/DSP28xxx_CodeStartBranch.asm new file mode 100644 index 0000000..d485bd4 --- /dev/null +++ b/Lib/asm/DSP28xxx_CodeStartBranch.asm @@ -0,0 +1,88 @@ +;// TI File $Revision: /main/1 $ +;// Checkin $Date: December 1, 2004 11:11:32 $ +;//########################################################################### +;// +;// FILE: DSP28xxx_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// From this code the watchdog will be disabled followed by calling the +;// copy_section function to copy sections from flash to ram. +;// +;// In addition, the example DSP28xxx projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The copy_sections code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: DSP280x, DSP2801x Header Files V1.41 $ +;// $Release Date: August 7th, 2006 $ +;// Modified by: Tim Love +;// Modified Date: March 2008 +;//########################################################################### + + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref copy_sections + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB copy_sections ;Branch to copy_sections + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .sect "wddisable" +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB copy_sections ;Branch to copy_sections + + .endif + +;end wd_disable + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== \ No newline at end of file diff --git a/Lib/asm/DSP28xxx_SectionCopy_nonBIOS.asm b/Lib/asm/DSP28xxx_SectionCopy_nonBIOS.asm new file mode 100644 index 0000000..3f50afc --- /dev/null +++ b/Lib/asm/DSP28xxx_SectionCopy_nonBIOS.asm @@ -0,0 +1,88 @@ +;############################################################################ +; +; FILE: DSP28xxx_SectionCopy_nonBIOS.asm +; +; DESCRIPTION: Provides functionality for copying intialized sections from +; flash to ram at runtime before entering the _c_int00 startup +; routine +;############################################################################ +; Author: Tim Love +; Release Date: March 2008 +;############################################################################ + + + .ref _c_int00 + .global copy_sections + .global _cinit_loadstart, _cinit_runstart, _cinit_size + .global _const_loadstart, _const_runstart, _const_size + .global _econst_loadstart, _econst_runstart, _econst_size + .global _pinit_loadstart, _pinit_runstart, _pinit_size + .global _switch_loadstart, _switch_runstart, _switch_size + .global _text_loadstart, _text_runstart, _text_size + +*********************************************************************** +* Function: copy_sections +* +* Description: Copies initialized sections from flash to ram +*********************************************************************** + + .sect "copysections" + +copy_sections: + + + MOVL XAR5,#_cinit_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_cinit_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_cinit_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + MOVL XAR5,#_const_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_const_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_const_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + MOVL XAR5,#_econst_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_econst_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_econst_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + MOVL XAR5,#_pinit_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_pinit_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_pinit_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + MOVL XAR5,#_switch_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_switch_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_switch_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + MOVL XAR5,#_text_size ; Store Section Size in XAR5 + MOVL ACC,@XAR5 ; Move Section Size to ACC + MOVL XAR6,#_text_loadstart ; Store Load Starting Address in XAR6 + MOVL XAR7,#_text_runstart ; Store Run Address in XAR7 + LCR copy ; Branch to Copy + + + LB _c_int00 ; Branch to start of boot.asm in RTS library + +copy: + B return,EQ ; Return if ACC is Zero (No section to copy) + + SUBB ACC,#1 + + RPT AL ; Copy Section From Load Address to + || PWRITE *XAR7, *XAR6++ ; Run Address + +return: + LRETR ; Return + + .end + +;//=========================================================================== +;// End of file. +;//=========================================================================== \ No newline at end of file diff --git a/Source/.STATICFILE b/Source/.STATICFILE new file mode 100644 index 0000000..c4bae38 --- /dev/null +++ b/Source/.STATICFILE @@ -0,0 +1,66 @@ +{ + "REANALYZE": false, + "WORKING_DIR": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", + "COMPILER_INSTALLATION_PATH": [], + "PRE_BUILD_COMMAND": "", + "COMMAND": [], + "STATIC_SERVER_ADDRESS": "gw.seoltech.com:8080", + "PROJECT_KEY": "K2DCU", + "TOOLCHAIN_FILENAME": "TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf", + "PARSING": { + "C": { + "include": [ + "C:\\ti\\ccs1281\\ccs\\tools\\compiler\\ti-cgt-c2000_22.6.1.LTS\\include" + ], + "conf": [ + "cs_encoding", + "cs_define_macro_value=__has_include(STR);0" + ], + "removes": [] + }, + "CPP": { + "include": [ + "C:\\ti\\ccs1281\\ccs\\tools\\compiler\\ti-cgt-c2000_22.6.1.LTS\\include" + ], + "conf": [], + "removes": [] + } + }, + "USER_DEFINED_EXTENSIONS": { + "header": [ + ".h", + ".H", + ".hpp", + ".HPP", + ".tcc", + ".inl", + ".INL" + ], + "source": [ + ".c", + ".C", + ".c++", + ".C++", + ".cpp", + ".CPP", + ".cxx", + ".CXX", + ".cc", + ".CC", + ".cp", + ".CP" + ], + "object": [ + ".o", + ".O", + ".lo", + ".obj", + ".OBJ" + ] + }, + "MULTI_PROCESSOR": false, + "EXCLUSIONS": [], + "EXTRA_OPTIONS": { + "SPECIFIED_ANALYSIS_AGENT_VERSION": "" + } +} \ No newline at end of file diff --git a/Source/.spec b/Source/.spec new file mode 100644 index 0000000..1d6510f --- /dev/null +++ b/Source/.spec @@ -0,0 +1,44 @@ +[ + { + NAME: Default + COMMON_COMPILE_FLAG: -I "C:\ti\c2000\C2000Ware_4_03_00_00\device_support\f2833x\common\include" -I "C:\ti\c2000\C2000Ware_4_03_00_00\device_support\f2833x\headers\include" + SOURCES: + [ + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS} + FILENAME: Comm.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS} + FILENAME: Display.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS} + FILENAME: Oper.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS} + FILENAME: State.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + { + SOURCE_FILE_HANDLER: file + SEARCH_DIR: ${THIS} + FILENAME: main.c + COMPILE_FLAG: inherit + BUILD_DIR: ${THIS} + } + ] + } +] \ No newline at end of file diff --git a/Source/.staticdata/.hint b/Source/.staticdata/.hint new file mode 100644 index 0000000..5aa3102 --- /dev/null +++ b/Source/.staticdata/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/.hint b/Source/.staticdata/.previous/20260407_213608/.hint new file mode 100644 index 0000000..5aa3102 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/.spec b/Source/.staticdata/.previous/20260407_213608/.spec new file mode 100644 index 0000000..4cc0997 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v019\Source\.spec \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/config/.inf b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/config/ci.ini b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/config/csa.exe b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/csa.exe differ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/config/psionic.ini b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e new file mode 100644 index 0000000..b77e1da --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b4e66dfc4efeb665671c8b94be6ce283 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b4e66dfc4efeb665671c8b94be6ce283 new file mode 100644 index 0000000..cfd7f8d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b4e66dfc4efeb665671c8b94be6ce283 @@ -0,0 +1,1978 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + ch = (ch > 95U) ? 0U : ch; + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6]; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 new file mode 100644 index 0000000..678488d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fs_hash_map.json b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fs_hash_map.json new file mode 100644 index 0000000..d3a2a53 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_PIECTRL.H": [ + "beb797cd9bcae5c0ce186c9071f47086_", + false, + true, + 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b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1f5a659fa6f96a4a24515785f070097e b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1f5a659fa6f96a4a24515785f070097e new file mode 100644 index 0000000..59c5d53 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/1f5a659fa6f96a4a24515785f070097e @@ -0,0 +1,1978 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = (TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + ch = (ch > 95U) ? 0U : ch; + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6]; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 new file mode 100644 index 0000000..678488d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fs_hash_map.json b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fs_hash_map.json new file mode 100644 index 0000000..8263607 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/K2DCU/fs_/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/COMMON/INCLUDE/DSP2833X_GLOBALPROTOTYPES.H": [ + "5087ebaeb4c90cf7a0a088e87497fcc2_", + false, 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설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"2026-01-13T00:04:02.857Z\",\n\n \"last_capture_time\": \"2026-04-02T08:37:05.176Z\"\n\n}" +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/artifacts.zip b/Source/.staticdata/.previous/20260407_213608/artifacts.zip new file mode 100644 index 0000000..bfb13c0 Binary files /dev/null and b/Source/.staticdata/.previous/20260407_213608/artifacts.zip differ diff --git a/Source/.staticdata/.previous/20260407_213608/cstrace.json b/Source/.staticdata/.previous/20260407_213608/cstrace.json new file mode 100644 index 0000000..f3a4b1b --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + } +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/error.json b/Source/.staticdata/.previous/20260407_213608/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/exclude_project.json b/Source/.staticdata/.previous/20260407_213608/exclude_project.json new file mode 100644 index 0000000..2dba8e4 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "Default", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260407_213608/preinclude/gnu_preinclude.h b/Source/.staticdata/.previous/20260407_213608/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_c.h b/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_cpp.h b/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/Source/.staticdata/.previous/20260407_213608/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_091142/.hint b/Source/.staticdata/.previous/20260408_091142/.hint new file mode 100644 index 0000000..5aa3102 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/.spec b/Source/.staticdata/.previous/20260408_091142/.spec new file mode 100644 index 0000000..4cc0997 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v019\Source\.spec \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/config/.inf b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/config/ci.ini b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/config/csa.exe b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/csa.exe differ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/config/psionic.ini b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e new file mode 100644 index 0000000..b77e1da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/82fc78abdaf4bc603d799273546d4356 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/82fc78abdaf4bc603d799273546d4356 new file mode 100644 index 0000000..c545d98 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/82fc78abdaf4bc603d799273546d4356 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + //CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4d3b2ae07892b83f863b5915b3211d8 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4d3b2ae07892b83f863b5915b3211d8 new file mode 100644 index 0000000..7cadafa --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f4d3b2ae07892b83f863b5915b3211d8 @@ -0,0 +1,1978 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1U); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + ch = (ch > 95U) ? 0U : ch; + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fs_hash_map.json b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fs_hash_map.json new file mode 100644 index 0000000..8e1254d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DEVEMU.H": [ + "3639c9c8a3264ec88cb369751be62a8d_", + false, + true, + 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b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b4e66dfc4efeb665671c8b94be6ce283 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b4e66dfc4efeb665671c8b94be6ce283 new file mode 100644 index 0000000..cfd7f8d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b4e66dfc4efeb665671c8b94be6ce283 @@ -0,0 +1,1978 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + ch = (ch > 95U) ? 0U : ch; + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6]; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 new file mode 100644 index 0000000..678488d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b5d424479a96c0e4f4fc5ca18a4ffdc3 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fs_hash_map.json b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fs_hash_map.json new file mode 100644 index 0000000..d3a2a53 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/K2DCU/fs_/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_PIECTRL.H": [ + "beb797cd9bcae5c0ce186c9071f47086_", + false, + true, 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설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[PA]\n\n; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.\n\n; default 값은 N 입니다.\n\nCLEAN_MODE=N\n\n;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.\n\n; default 값은 N 입니다.\n\nAUTO_ENCODING_UTF8=N\n\n\n\n; 프로젝트 DB 에 대한 초기화 쿼리\n\nINIT_QUERY=PRAGMA mmap_size=2147418112;\n\n\n\n; 람다 코드를 CFG에 포함할지 여부입니다. \n\n; 초기 값은 'N' 입니다.\n\nDISABLE_LAMBDA_CFG=N\n\n\n\n\n\n; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성\n\n; 초기 값은 'Y' 입니다.\n\nMAKE_UNIQUE_REFINED_DIR=Y\n\n;\n\n;-------------------------------------------------------------------------\n\n;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.\n\n;default 값은 Y 입니다.\n\n[CI]\n\nREINDEX_MODE=Y\n\n\n\n;\n\n;\n\n; DFA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[DFA]\n\nDFA_ENABLE=Y\n\nSCFG_OUT=N\n\nLIMIT_ITER=N\n\nRESULT_OUT=N\n\nITER_OUT=N\n\nTRANSFER_OUT=N\n\nFYCYC_ITER=40\n\n;\n\n;\n\n; Abstract Interpreter 설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"2026-01-13T00:04:02.857Z\",\n\n \"last_capture_time\": \"2026-04-02T08:37:05.176Z\"\n\n}" +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/artifacts.zip b/Source/.staticdata/.previous/20260408_091142/artifacts.zip new file mode 100644 index 0000000..1d485d3 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_091142/artifacts.zip differ diff --git a/Source/.staticdata/.previous/20260408_091142/cstrace.json b/Source/.staticdata/.previous/20260408_091142/cstrace.json new file mode 100644 index 0000000..f3a4b1b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + } +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/error.json b/Source/.staticdata/.previous/20260408_091142/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/exclude_project.json b/Source/.staticdata/.previous/20260408_091142/exclude_project.json new file mode 100644 index 0000000..2dba8e4 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "Default", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_091142/preinclude/gnu_preinclude.h b/Source/.staticdata/.previous/20260408_091142/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_c.h b/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_cpp.h b/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_091142/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_093929/.hint b/Source/.staticdata/.previous/20260408_093929/.hint new file mode 100644 index 0000000..5aa3102 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/.hint @@ -0,0 +1 @@ +{"base_dir": "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\.staticdata", "server_address": "gw.seoltech.com", "project_key": "K2DCU", "response": {"status_code": 200, "body": "Analysis upload successful"}} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/.spec b/Source/.staticdata/.previous/20260408_093929/.spec new file mode 100644 index 0000000..4cc0997 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v019\Source\.spec \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/config/.inf b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/config/ci.ini b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/config/csa.exe b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/csa.exe differ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/config/psionic.ini b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e new file mode 100644 index 0000000..b77e1da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 new file mode 100644 index 0000000..678488d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 new file mode 100644 index 0000000..72f3250 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 @@ -0,0 +1,1979 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1U); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + Uint16 uiCh = ch; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + uiCh -= 0x20U; // font offset + uiCh = (uiCh > 95U) ? 0U : uiCh; + pFontData = EngFontTable[uiCh]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fs_hash_map.json b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fs_hash_map.json new file mode 100644 index 0000000..4e1da2b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_XINTF.H": [ + "9a0ce54b7ac8c23b398b7f623c6ec79f_", + false, + true, + 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b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/82fc78abdaf4bc603d799273546d4356 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/82fc78abdaf4bc603d799273546d4356 new file mode 100644 index 0000000..c545d98 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/82fc78abdaf4bc603d799273546d4356 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + //CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4d3b2ae07892b83f863b5915b3211d8 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4d3b2ae07892b83f863b5915b3211d8 new file mode 100644 index 0000000..7cadafa --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f4d3b2ae07892b83f863b5915b3211d8 @@ -0,0 +1,1978 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1U); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + ch -= 0x20U; // font offset + ch = (ch > 95U) ? 0U : ch; + pFontData = EngFontTable[ch]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fs_hash_map.json b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fs_hash_map.json new file mode 100644 index 0000000..8e1254d --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/K2DCU/fs_/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_DEVEMU.H": [ + "3639c9c8a3264ec88cb369751be62a8d_", + false, + true, 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\"cs_define_macro_value=__signed_chars__;1\",\n\n \"cs_define_macro_value=__DATE__;\",\n\n \"cs_define_macro_value=__TIME__;\",\n\n \"cs_define_macro_value=__STDC__;1\",\n\n \"cs_define_macro_value=__STDC_VERSION__;199409L\",\n\n \"cs_define_macro_value=__edg_front_end__;1\",\n\n \"cs_define_macro_value=__EDG_VERSION__;404\",\n\n \"cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long\",\n\n \"cs_define_macro_value=__TI_COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__COMPILER_VERSION__;6002000\",\n\n \"cs_define_macro_value=__TMS320C2000__;1\",\n\n \"cs_define_macro_value=_TMS320C2000;1\",\n\n \"cs_define_macro_value=__TMS320C28XX__;1\",\n\n \"cs_define_macro_value=_TMS320C28XX;1\",\n\n \"cs_define_macro_value=__TMS320C28X__;1\",\n\n \"cs_define_macro_value=_TMS320C28X;1\",\n\n \"cs_define_macro_value=__TMS320C28XX_FPU32__;1\",\n\n \"cs_define_macro_value=__LARGE_MODEL__;1\",\n\n \"cs_define_macro_value=__SIZE_T_TYPE__;unsigned long\",\n\n \"cs_define_macro_value=__PTRDIFF_T_TYPE__;long\",\n\n \"cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int\",\n\n \"cs_define_macro_value=__little_endian__;1\",\n\n \"cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1\",\n\n \"cs_define_macro_value=__TI_WCHAR_T_BITS__;16\",\n\n \"cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0\",\n\n \"cs_define_macro_value=__TI_STRICT_FP_MODE__;1\",\n\n \"cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1\",\n\n \"cs_set_type_size=int;2\",\n\n \"cs_set_type_size=long;4\",\n\n \"cs_set_type_size=pointer;2\",\n\n \"cs_set_type_size=float;4\",\n\n \"cs_set_type_size=double;4\",\n\n \"cs_plain_char=signed\",\n\n \"cs_plain_bit_field=unsigned\",\n\n \"cs_for_init_scope=outer\",\n\n \"cs_using_std=disable\",\n\n \"gnu_version=40702\"\n\n ],\n\n \"include\": []\n\n }\n\n]", + "ci_ini": ";\n\n;\n\n; PA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[PA]\n\n; 최초 PA 실행시에 테이블의 레코드를 모두 제거한 후 PA 가 수행됩니다.\n\n; default 값은 N 입니다.\n\nCLEAN_MODE=N\n\n;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.\n\n; default 값은 N 입니다.\n\nAUTO_ENCODING_UTF8=N\n\n\n\n; 프로젝트 DB 에 대한 초기화 쿼리\n\nINIT_QUERY=PRAGMA mmap_size=2147418112;\n\n\n\n; 람다 코드를 CFG에 포함할지 여부입니다. \n\n; 초기 값은 'N' 입니다.\n\nDISABLE_LAMBDA_CFG=N\n\n\n\n\n\n; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성\n\n; 초기 값은 'Y' 입니다.\n\nMAKE_UNIQUE_REFINED_DIR=Y\n\n;\n\n;-------------------------------------------------------------------------\n\n;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.\n\n;default 값은 Y 입니다.\n\n[CI]\n\nREINDEX_MODE=Y\n\n\n\n;\n\n;\n\n; DFA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[DFA]\n\nDFA_ENABLE=Y\n\nSCFG_OUT=N\n\nLIMIT_ITER=N\n\nRESULT_OUT=N\n\nITER_OUT=N\n\nTRANSFER_OUT=N\n\nFYCYC_ITER=40\n\n;\n\n;\n\n; Abstract Interpreter 설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"2026-01-13T00:04:02.857Z\",\n\n \"last_capture_time\": \"2026-04-02T08:37:05.176Z\"\n\n}" +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/artifacts.zip b/Source/.staticdata/.previous/20260408_093929/artifacts.zip new file mode 100644 index 0000000..b492d97 Binary files /dev/null and b/Source/.staticdata/.previous/20260408_093929/artifacts.zip differ diff --git a/Source/.staticdata/.previous/20260408_093929/cstrace.json b/Source/.staticdata/.previous/20260408_093929/cstrace.json new file mode 100644 index 0000000..f3a4b1b --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + } +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/error.json b/Source/.staticdata/.previous/20260408_093929/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/exclude_project.json b/Source/.staticdata/.previous/20260408_093929/exclude_project.json new file mode 100644 index 0000000..2dba8e4 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "Default", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/Source/.staticdata/.previous/20260408_093929/preinclude/gnu_preinclude.h b/Source/.staticdata/.previous/20260408_093929/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_c.h b/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_cpp.h b/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/Source/.staticdata/.previous/20260408_093929/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/.spec b/Source/.staticdata/.spec new file mode 100644 index 0000000..4cc0997 --- /dev/null +++ b/Source/.staticdata/.spec @@ -0,0 +1 @@ +C:\ti\Project\K2APU_DCU_v019\Source\.spec \ No newline at end of file diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci new file mode 100644 index 0000000..db1d318 Binary files /dev/null and b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci differ diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa new file mode 100644 index 0000000..c5b28b6 Binary files /dev/null and b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa differ diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/csa.exe differ diff --git a/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/.toolbox_cache/AnalysisAgent_v4.8.0.p8/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/K2DCU/config/.inf b/Source/.staticdata/K2DCU/config/.inf new file mode 100644 index 0000000..bc5286a --- /dev/null +++ b/Source/.staticdata/K2DCU/config/.inf @@ -0,0 +1 @@ +{"name":"STATIC Analysis Agent","version":"4.8.0.p8","description":null,"files":["bin/ci","bin/csa","bin/csa.exe","bin/ci.ini","bin/Psionic/psionic.ini"]} \ No newline at end of file diff --git a/Source/.staticdata/K2DCU/config/ci.ini b/Source/.staticdata/K2DCU/config/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/.staticdata/K2DCU/config/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/.staticdata/K2DCU/config/csa.exe b/Source/.staticdata/K2DCU/config/csa.exe new file mode 100644 index 0000000..d509ada Binary files /dev/null and b/Source/.staticdata/K2DCU/config/csa.exe differ diff --git a/Source/.staticdata/K2DCU/config/psionic.ini b/Source/.staticdata/K2DCU/config/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/.staticdata/K2DCU/config/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/.staticdata/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e b/Source/.staticdata/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e new file mode 100644 index 0000000..b77e1da --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/04e43fb5be4196c8a44f0c60a3b1677e @@ -0,0 +1,63 @@ +#ifndef SOURCE_OPER_H_ +#define SOURCE_OPER_H_ + +typedef struct ClassLedPattern +{ + Uint16 Fault; + Uint16 Operation; + Uint16 Stop; +} CLedPattern; + +typedef enum +{ + IDX_APU_OPER_BOOT = 0U, // 0 부팅 + IDX_APU_OPER_INITIAL, // 1 하드웨어 초기화 + IDX_APU_OPER_POST, // 2 자체 진단 + IDX_APU_OPER_EMERGENCY, // 3 비상 정지 + IDX_APU_OPER_STANDBY, // 4 대기 + IDX_APU_OPER_READY, // 5 준비 상태 + IDX_APU_OPER_PREHEAT, // 6 연료 펌프 구동 및 예열 + IDX_APU_OPER_CRANKING, // 7 스타터 모터 구동 + IDX_APU_OPER_RETRY_CRANKING, // 8 시동 재시도 + IDX_APU_OPER_ENGINE_IDLE, // 9 시동 성공 후 RPM 안정화 대기 + IDX_APU_OPER_GENERATING, // 10 발전 시작 + IDX_APU_OPER_COOLDOWN, // 11 엔진 냉각(정지 시) + IDX_APU_OPER_STOPPING, // 12 연료 펌프 및 솔레노이드, 냉각팬 차단 +} E_IDX_APU_OPER; + +typedef enum +{ + IDX_ECU_STAT_STANDBY = 0U, // 0 + IDX_ECU_STAT_STARTING, // 1 + IDX_ECU_STAT_IDLE, // 2 + IDX_ECU_STAT_OPERATION, // 3 + IDX_ECU_STAT_DERATING, // 4 + IDX_ECU_STAT_COOLDOWN, // 5 + IDX_ECU_STAT_STOP // 6 +} E_IDX_ECU_STAT; + +typedef enum +{ + IDX_GCU_CMD_STOP = 0U, // 0 + IDX_GCU_CMD_CRANKING, // 1 + IDX_GCU_CMD_STOP_CRANKING, // 2 + IDX_GCU_CMD_GENERATING // 3 +} E_IDX_GCU_CMD; + +typedef enum +{ + IDX_ECU_CMD_STOP = 0U, // 0 + IDX_ECU_CMD_START, // 1 + IDX_ECU_CMD_EMERGENCY // 2 +} E_IDX_ECU_CMD; + +void CApuOperProcedure(void); +void CDebugModeProcedure(void); +void CLedControlProcedure(void); +int16 CGetEngCoolantTemperature(void); +Uint16 CGetGeneratorRpm(void); +Uint16 CGetEngineActualRpm(void); +void CSetGcuCommand(Uint16 Command); +void CSetEcuCommand(Uint16 Command); + +#endif /* SOURCE_OPER_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ b/Source/.staticdata/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ new file mode 100644 index 0000000..0d98732 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/0677fd7e81d1e42d5d888dd0d275b1fe_ @@ -0,0 +1,233 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 22, 2007 10:40:22 $ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ b/Source/.staticdata/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ new file mode 100644 index 0000000..a37d398 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/1784ef9f6544b15ca51cc304251630b3_ @@ -0,0 +1,243 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:39 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 b/Source/.staticdata/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 new file mode 100644 index 0000000..3cdec6d --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/1e648022ba6efd01149b89021ce76b65 @@ -0,0 +1,156 @@ +#ifndef SOURCE_DISPLAY_H_ +#define SOURCE_DISPLAY_H_ + +#define ZONE6_DAT *(volatile Uint16*)0x00100001 +#define ZONE6_COM *(volatile Uint16*)0x00100000 + +#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127 +#define OLED_HEIGHT (64U) +#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7 + +#define TXT_ENG_WIDTH (6U) +#define TXT_ENG_HEIGHT (12U) + +#define TXT_TYPE_ENG (0U) +#define TXT_TYPE_ETC (1U) + +#define TXT_MAX_LEN (22U) +#define TXT_LINE_LEN (5U) + +#define OLED_LOAD_PROGRESS_X (14U) +#define OLED_LOAD_PROGRESS_Y (52U) +#define OLED_LOAD_PROGRESS_W (114U) +#define OLED_LOAD_PROGRESS_H (10U) + +#define MODE_COMMAND (0U) +#define MODE_DATA (1U) + +#define DIR_UP (1U) +#define DIR_DOWN (0U) + +typedef signed char int8; +typedef unsigned char Uint8; + +typedef enum +{ + IDX_OLED_LINE_TITLE = 0U, + IDX_OLED_LINE_1 = 14U, + IDX_OLED_LINE_2 = 27U, + IDX_OLED_LINE_3 = 40U, + IDX_OLED_LINE_4 = 53U +} E_IDX_OLED_LINE; + +typedef enum +{ + IDX_OLED_ROW_0 = 0U, + IDX_OLED_ROW_1, + IDX_OLED_ROW_2, + IDX_OLED_ROW_3, + IDX_OLED_ROW_4 +} E_IDX_OLED_ROW; + +typedef enum +{ + IDX_OLED_PASS_DIGIT_1 = 0U, + IDX_OLED_PASS_DIGIT_2, + IDX_OLED_PASS_DIGIT_3, + IDX_OLED_PASS_DIGIT_4 +} E_IDX_OLED_PASS; + +typedef enum +{ + IDX_OLED_PAGE_APU1 = 0U, // 0 + IDX_OLED_PAGE_APU2, // 1 + IDX_OLED_PAGE_MENU1, // 2 + IDX_OLED_PAGE_MENU2, // 3 + IDX_OLED_PAGE_TEMP, // 4 + IDX_OLED_PAGE_SENSOR1, // 5 + IDX_OLED_PAGE_SENSOR2, // 6 + IDX_OLED_PAGE_SENSOR3, // 7 + IDX_OLED_PAGE_SENSOR4, // 8 + IDX_OLED_PAGE_WARNING1, // 9 + IDX_OLED_PAGE_WARNING2, // 10 + IDX_OLED_PAGE_FAULT1, // 11 + IDX_OLED_PAGE_FAULT2, // 12 + IDX_OLED_PAGE_FAULT3, // 13 + IDX_OLED_PAGE_FAULT4, // 14 + IDX_OLED_PAGE_FAULT5, // 15 + IDX_OLED_PAGE_FAULT6, // 16 + IDX_OLED_PAGE_FAULT7, // 17 + IDX_OLED_PAGE_RESET_ALARM, // 18 + IDX_OLED_PAGE_PASSWORD, // 19 + IDX_OLED_PAGE_MAINTENANCE, // 20 + IDX_OLED_PAGE_VERSION, // 21 + IDX_OLED_PAGE_KEY_TEST, // 21 + IDX_OLED_PAGE_SHUTDOWN, // 23 + IDX_OLED_PAGE_MAX +} E_IDX_OLED_PAGE; + +typedef enum +{ + IDX_OLED_MENU_APU = 0U, // 0 + IDX_OLED_MENU_TEMP, // 1 + IDX_OLED_MENU_SENSOR, // 2 + IDX_OLED_MENU_WARNING, // 3 +} E_IDX_OLED_MENU1; + +typedef enum +{ + IDX_OLED_MENU_FAULT = 0U, // 0 + IDX_OLED_MENU_RESET, // 1 + IDX_OLED_MENU_DEBUG // 2 +} E_IDX_OLED_MENU2; + +typedef enum +{ + IDX_OLED_LINE_FOCUS_1 = 0U, + IDX_OLED_LINE_FOCUS_2, + IDX_OLED_LINE_FOCUS_3, + IDX_OLED_LINE_FOCUS_4 +} E_IDX_OLED_LINE_FOCUS; + +typedef struct ClassPageHandler +{ + Uint16 uiPage; + void (*pAction) (void); // PageTable 참조 +} CPageHandler; + +typedef struct ClassOledOperValue +{ + Uint16 uiBuff[OLED_WIDTH][OLED_PAGE]; + Uint16 uiPageNum; + Uint16 uiOldPageNum; + Uint16 uiFocusLine; + Uint16 uiPrevFocusLine; + Uint16 uiFocusDigit; + Uint16 uiProgressValue; + Uint16 uiProgressDone; + Uint16 uiResetAlarmAnswer; + Uint16 uiResetHourAnswer; + int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN]; + int8 cAlignBuffer[TXT_MAX_LEN]; + struct + { + Uint16 TxtColor; + Uint16 BgColor; + } Color; + struct + { + Uint16 X; + Uint16 Y; + } Point; +} COledOperValue; + +void CInitXintf(void); +void CInitOled(void); +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height); +void CDisplayPostFail(void); +void CSetPage(Uint16 PageNum); +void CInitKeyOperValue(void); +void CInitializePage(void); +void COledBufferReset(void); +void CDisplayAntiNoiseRefresh(void); + +extern COledOperValue OledOperValue; + +#endif /* SOURCE_DISPLAY_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 b/Source/.staticdata/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 new file mode 100644 index 0000000..f33b76b --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/28df5e74bd8ddae9115a4fb8166fcf29 @@ -0,0 +1,1295 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ALARM_UNDER_CHECK (0U) +#define ALARM_OVER_CHECK (1U) + +#define LONG_KEY_TIME (500UL) +#define KEY_POWER_MASK (0x0001UL) // 0x0001 - LOCAL POWER +#define KEY_START_MASK (0x01A0UL) // 0x0100 - REMOTE STOP, 0x0080 - REMOTE START, 0x0020 - LOCAL START/STOP + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CAlarmOperValue AlarmOperValue[(Uint16)IDX_FAULT_DCU_MAX]; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitAlarmOperValue(void); +static void CKeyMainPowerProcess(void); +static void CProcessArrowUpFocusChange(void); +static void CProcessArrowUpPageChange(void); +static void CKeyArrowUpProcess(void); +static void CKeyArrowDownProcess(void); +static void CProcessArrowDownPageChange(void); +static void CProcessArrowDownFocusChange(void); +static void CProcessEnterMenu1(void); +static void CProcessEnterMenu2(void); +static void CProcessEnterPassword(void); +static void CProcessEnterMaintenance(void); +static void CKeyEnterProcess(void); +static void CKeyMenuProcess(void); +static void CKeyEngineStartStopProcess(void); +static void CKeyRemoteEngineStartProcess(void); +static void CKeyRemoteEngineStopProcess(void); +static void CKeyEmergencyProcess(void); +static void CKeyBattleModeProcess(void); +static void CInitAdcStructure(void); +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType); +static void CApuSystemAlarmCheck(void); +static Uint32 CGetKey(void); +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead); +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction); +static void CChangePasswordDigit(Uint16 direction); +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CAdcCalcValue Adc_EngineHeater_V; +CAdcCalcValue Adc_GlowPlug_V; +CAdcCalcValue Adc_Solenoid_V; +CAdcCalcValue Adc_FuelPump_V; +CAdcCalcValue Adc_CoolantPump_V; +CAdcCalcValue Adc_Fan1_V; +CAdcCalcValue Adc_Fan2_V; + +CAdcCalcValue Adc_EngineHeater_I; +CAdcCalcValue Adc_GlowPlug_I; +CAdcCalcValue Adc_Solenoid_I; +CAdcCalcValue Adc_FuelPump_I; +CAdcCalcValue Adc_CoolantPump_I; +CAdcCalcValue Adc_Fan1_I; +CAdcCalcValue Adc_Fan2_I; + +CAdcOperValue AdcOperValue; + +CKeyOperValue KeyOperValue; + +Uint32 ulDcuTotalAlarm = 0UL; +Uint32 ulGcuTotalAlarm = 0UL; +Uint32 ulEcuTotalAlarm = 0UL; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CAdcInterrupt(void) +{ + Uint16 uiTemp[(Uint16)IDX_ADC_MAX]; + Uint16 i; + + const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0; + + for (i = 0U; i < (Uint16)IDX_ADC_MAX; i++) + { + uiTemp[i] = (*(pAdcAddress++) >> 4); + } + + Adc_EngineHeater_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_V]; + Adc_GlowPlug_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_V]; + Adc_Solenoid_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_V]; + Adc_FuelPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_V]; + Adc_CoolantPump_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_V]; + Adc_Fan1_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_V]; + Adc_Fan2_V.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_V]; + + Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_ENGINE_HEATER_I]; + Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_GLOW_PLUG_I]; + Adc_Solenoid_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_SOLENOID_I]; + Adc_FuelPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FUEL_PUMP_I]; + Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_COOLANT_PUMP_I]; + Adc_Fan1_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN1_I]; + Adc_Fan2_I.iAdcValue = (int16) uiTemp[(Uint16)IDX_ADC_FAN2_I]; + + if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration + { + Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue; + Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue; + Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue; + Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue; + Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue; + Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue; + Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue; + + AdcOperValue.uiAdcOffsetIndex--; + + if (AdcOperValue.uiAdcOffsetIndex == 0U) + { + Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0F); + Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0F); + Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0F); + Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0F); + Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0F); + Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0F); + Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0F); + + AdcOperValue.uiOffsetAdjustStart = 0U; + } + } + else + { + CCalcAdcSum(&Adc_EngineHeater_V); + CCalcAdcSum(&Adc_GlowPlug_V); + CCalcAdcSum(&Adc_Solenoid_V); + CCalcAdcSum(&Adc_FuelPump_V); + CCalcAdcSum(&Adc_CoolantPump_V); + CCalcAdcSum(&Adc_Fan1_V); + CCalcAdcSum(&Adc_Fan2_V); + + CCalcAdcSum(&Adc_EngineHeater_I); + CCalcAdcSum(&Adc_GlowPlug_I); + CCalcAdcSum(&Adc_Solenoid_I); + CCalcAdcSum(&Adc_FuelPump_I); + CCalcAdcSum(&Adc_CoolantPump_I); + CCalcAdcSum(&Adc_Fan1_I); + CCalcAdcSum(&Adc_Fan2_I); + } + + // Reinitialize for next ADC sequence + AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1 + AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE +} + +void CDisplayAlarmPopup(void) +{ + static Uint64 PrevFaultValue = 0U; + static Uint32 PrevWarningValue = 0U; + + // FaultValue는 랫치상태 + Uint64 FaultValue = ((Uint64)ulDcuTotalAlarm & MASK_26BIT) | (((Uint64)ulGcuTotalAlarm & MASK_WORD) << 26UL) | (((Uint64)ulEcuTotalAlarm & MASK_6BIT) << 42UL); + + // WarningValue는 경고가 사라질수 있기 때문에 랫치 하지 않음 + Uint32 WarningValue = (((Uint32)Rx210.GcuWarning & (Uint32)MASK_LOW_NIBBLE) | (((Uint32)Rx310.EcuWarning & 0xFDU) << 4U)); + + // 0 → 1로 바뀐 비트만 추출 + Uint64 NewFault = FaultValue & (~PrevFaultValue); + Uint32 NewWarning = WarningValue & (~PrevWarningValue); + + // 현재 값 저장 + PrevFaultValue = FaultValue; + PrevWarningValue = WarningValue; + + Uint16 i; + Uint16 UpdatePage = 0U; // 0: 유지, 1: Fault 이동, 2: Warning 이동 + Uint64 TargetFault = 0U; // 검색할 대상 변수 (Fault) + Uint32 TargetWarning = 0U; // 검색할 대상 변수 (Warning) + + if (NewFault > 0ULL) + { + TargetFault = NewFault; // 새로 뜬 Fault만 검색 대상 + UpdatePage = 1U; + } + else + { + if (NewWarning > 0U) + { + TargetWarning = NewWarning; // 새로 뜬 Warning만 검색 대상 + UpdatePage = 2U; + } + } + + // [페이지 이동 로직] + if (UpdatePage > 0U) + { + /* Fault 처리 */ + if (UpdatePage == 1U) + { + for (i = 0U; i < 64U; i++) + { + /* 비트 추출 시 Essential Type 일치를 위해 1ULL(또는 명시적 캐스팅) 사용 */ + if (((TargetFault >> i) & 1ULL) == 1ULL) + { + if (i < (Uint16)IDX_FAULT_DCU_MAX) + { + Uint16 uiCalcPage = (Uint16)((i / 8U) + (Uint16)IDX_OLED_PAGE_FAULT1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT4) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT4; + } + else + { + Uint16 uiCalcPage = (Uint16)((Uint16)IDX_OLED_PAGE_FAULT5 + ((i - (Uint16)IDX_FAULT_DCU_MAX) / 8U)); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_FAULT7) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_FAULT7; + } + break; /* 가장 낮은 비트(새로 발생한 것) 찾으면 즉시 이동 */ + } + } + } + else + { + /* 발전상태에서만 경고 처리, 고장 발생시 경고 페이지 이동 무시 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((NewWarning > 0U) && (FaultValue == 0U)) + { + for (i = 0U; i < 16U; i++) + { + if (((TargetWarning >> i) & 1U) == 1U) + { + Uint16 uiCalcPage = (Uint16)((i / 9U) + (Uint16)IDX_OLED_PAGE_WARNING1); + OledOperValue.uiPageNum = (uiCalcPage <= (Uint16)IDX_OLED_PAGE_WARNING2) ? uiCalcPage : (Uint16)IDX_OLED_PAGE_WARNING2; + break; + } + } + } + } + } + } +} + +void CAlarmProcedure(void) +{ + int16 iDiffRpm = 0; + + /* 통신 상태 업데이트 */ + CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer <= COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : CommCheck.CarComputer; + CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : CommCheck.Gcu; + CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu <= COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : CommCheck.Ecu; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* Emergency 상태 시 처리 로직 (필요 시 작성) */ + } + else + { + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_EMERGENCY) + { + /* 통신 타임아웃 체크 및 비트 업데이트 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM, CAlarmCheck(IDX_FAULT_DCU_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM, CAlarmCheck(IDX_FAULT_DCU_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM, CAlarmCheck(IDX_FAULT_DCU_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK)); + + /* 타임아웃 발생 시 연결 비트 클리어 */ + GeneralOperValue.Conection.CarComputer = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM) == 1U) ? 0U : GeneralOperValue.Conection.CarComputer; + GeneralOperValue.Conection.Gcu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Gcu; + GeneralOperValue.Conection.Ecu = (CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM) == 1U) ? 0U : GeneralOperValue.Conection.Ecu; + + /* 과전류 알람 체크 */ + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC, CAlarmCheck(IDX_FAULT_DCU_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC, CAlarmCheck(IDX_FAULT_DCU_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK)); + + /* 개별 전압 알람 체크 */ + /* Engine Heater */ + if (ENGINE_HEATER_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_UV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV, CAlarmCheck(IDX_FAULT_DCU_ENGINE_HEAT_OV, Adc_EngineHeater_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckCount = 0U; + } + + /* Glow Plug */ + if (GLOW_PLUG_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_UV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV, CAlarmCheck(IDX_FAULT_DCU_GLOW_PLUG_OV, Adc_GlowPlug_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckCount = 0U; + } + + /* Solenoid */ + if (SOLENOID_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_UV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV, CAlarmCheck(IDX_FAULT_DCU_SOLENOID_OV, Adc_Solenoid_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckCount = 0U; + } + + /* Fuel Pump */ + if (FUEL_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_UV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_FUEL_PUMP_OV, Adc_FuelPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckCount = 0U; + } + + /* Coolant Pump */ + if (COOLANT_PUMP_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_UV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV, CAlarmCheck(IDX_FAULT_DCU_COOLANT_PUMP_OV, Adc_CoolantPump_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckCount = 0U; + } + + /* Fan1 */ + if (FAN1_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV, CAlarmCheck(IDX_FAULT_DCU_FAN1_UV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV, CAlarmCheck(IDX_FAULT_DCU_FAN1_OV, Adc_Fan1_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckCount = 0U; + } + + /* Fan2 */ + if (FAN2_OUT() == 1U) + { + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV, CAlarmCheck(IDX_FAULT_DCU_FAN2_UV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime, ALARM_UNDER_CHECK)); + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV, CAlarmCheck(IDX_FAULT_DCU_FAN2_OV, Adc_Fan2_V.fLpfValue, AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime, ALARM_OVER_CHECK)); + } + else + { + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckCount = 0U; + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckCount = 0U; + } + + /* RPM Error 체크 */ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm(); + iDiffRpm = (iDiffRpm < 0) ? -iDiffRpm : iDiffRpm; + CUpdateFault(&ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR, CAlarmCheck(IDX_FAULT_DCU_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK)); + } + } + } + } + + /* 알람 리셋 처리 */ + if (GeneralOperValue.uiAlarmReset == 1U) + { + CInitAlarmOperValue(); + ulDcuTotalAlarm = 0UL; /* 전체 비트 클리어 */ + + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_ALARM_RESET, TIME_1SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiAlarmReset = 0U; + } + } + + CApuSystemAlarmCheck(); +} + +static Uint16 CAlarmCheck(E_IDX_DCU_FAULT Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType) +{ + Uint16 uiCheckStatus = 0; + + if (AlarmOperValue[Idx].uiCheck == 0U) + { + if (uiCheckType == ALARM_OVER_CHECK) + { + // Over Check ! + if (fValue >= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + else + { + // Under Check ! + if (fValue <= AlarmOperValue[Idx].fCheckLimit) + { + uiCheckStatus = 1U; + } + } + + if (uiCheckStatus == 1U) + { + if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime) + { + AlarmOperValue[Idx].uiCheckCount++; + } + else + { + AlarmOperValue[Idx].uiCheck = 1U; + AlarmOperValue[Idx].uiCheckCount = 0U; + AlarmOperValue[Idx].fFaultValue = fValue; + } + } + else + { + AlarmOperValue[Idx].uiCheckCount = 0U; + } + } + + return AlarmOperValue[Idx].uiCheck; +} + +static void CApuSystemAlarmCheck(void) +{ + Uint32 TotalFault = 0UL; + Uint16 GcuCurrentFault; + Uint16 EcuCurrentFault; + + /* 각 바이트를 Uint16으로 먼저 승격시킨 후 연산 수행 */ + + GcuCurrentFault = Rx210.GcuFault; + EcuCurrentFault = Rx310.EcuFault; + + ulGcuTotalAlarm = ulGcuTotalAlarm | (Uint32)GcuCurrentFault; + ulEcuTotalAlarm = ulEcuTotalAlarm | (Uint32)EcuCurrentFault; + + TotalFault = (Uint32)ulDcuTotalAlarm | (Uint32)ulGcuTotalAlarm | (Uint32)ulEcuTotalAlarm; + + if (TotalFault > 0U) + { + GeneralOperValue.uiFaultOccured = 1U; + } + else + { + GeneralOperValue.uiFaultOccured = 0U; + } +} + +static void CInitAlarmOperValue(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_FAULT_DCU_MAX; i++) + { + (void)memset((void*)&AlarmOperValue[i], 0, sizeof(CAlarmOperValue)); + } + + (void)memset(&CommCheck, 0, sizeof(CCommCheck)); + + // 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리 + /* + * Alarm Check Standard Value + * Alarm Count per 1mS + */ + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출 + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].fCheckLimit = 300.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_RPM_ERR].uiCheckTime = 10U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].fCheckLimit = 30.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].fCheckLimit = 10.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].fCheckLimit = 5.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].fCheckLimit = 7.5F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OC].uiCheckTime = 100U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].fCheckLimit = 35.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OC].uiCheckTime = 100U; // Value + + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_SOLENOID_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN1_OV].uiCheckTime = 1000U; // Value + + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].fCheckLimit = 18.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_UV].uiCheckTime = 1000U; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].fCheckLimit = 31.0F; // Value + AlarmOperValue[(Uint16)IDX_FAULT_DCU_FAN2_OV].uiCheckTime = 1000U; // Value +} + +void CInitAdc(void) +{ + InitAdc(); // ADC Initialize in DSP2833x_Adc.c + + AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler + AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz + AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode + AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS + AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode + + AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_V + AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_V + AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_V + AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_V + AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_V + AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_V + AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x8; // Engine_Heater_I + AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x9; // Glow_Plug_I + AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0xA; // Solenoid_I + AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xB; // Fuel_Pump_I + AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xC; // Cooling_Pump_I + AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xD; // Fan1_I + AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xE; // Fan2_I + + AdcRegs.ADCMAXCONV.all = ((Uint16)IDX_ADC_MAX - 1U); // Setup 16 channel conversion for cascade sequence mode + + AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v] + AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; + AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS) + AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1) + + CInitAdcStructure(); + + CInitAlarmOperValue(); +} + +static void CInitAdcStructure(void) +{ + (void)memset(&AdcOperValue, 0, sizeof(CAdcOperValue)); + + (void)memset(&Adc_EngineHeater_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_V, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_V, 0, sizeof(CAdcCalcValue)); + + (void)memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue)); + (void)memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue)); + + AdcOperValue.uiAdcOffsetIndex = 10000U; + + Adc_EngineHeater_V.fGain = 0.026726F; + Adc_GlowPlug_V.fGain = 0.026726F; + Adc_Solenoid_V.fGain = 0.026726F; + Adc_FuelPump_V.fGain = 0.026726F; + Adc_CoolantPump_V.fGain = 0.026726F; + Adc_Fan1_V.fGain = 0.026726F; + Adc_Fan2_V.fGain = 0.026726F; + + Adc_EngineHeater_V.fOffset = -71.157F; + Adc_GlowPlug_V.fOffset = -71.157F; + Adc_Solenoid_V.fOffset = -71.157F; + Adc_FuelPump_V.fOffset = -71.157F; + Adc_CoolantPump_V.fOffset = -71.157F; + Adc_Fan1_V.fOffset = -71.157F; + Adc_Fan2_V.fOffset = -71.157F; + + Adc_EngineHeater_I.fGain = 0.027778F; // 40A Limit + Adc_GlowPlug_I.fGain = 0.027778F; // 40A Limit + Adc_Solenoid_I.fGain = 0.027778F; // 20A Limit + Adc_FuelPump_I.fGain = 0.027778F; // 20A Limit + Adc_CoolantPump_I.fGain = 0.027778F; // 20A Limit + Adc_Fan1_I.fGain = 0.027778F; // 40A Limit + Adc_Fan2_I.fGain = 0.027778F; // 40A Limit + + Adc_EngineHeater_I.fOffset = -62.277778F; + Adc_GlowPlug_I.fOffset = -62.277778F; + Adc_Solenoid_I.fOffset = -62.277778F; + Adc_FuelPump_I.fOffset = -62.277778F; + Adc_CoolantPump_I.fOffset = -62.277778F; + Adc_Fan1_I.fOffset = -62.277778F; + Adc_Fan2_I.fOffset = -62.277778F; +} + +static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff) +{ + AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset; + AdcBuff->fSampledSum += AdcBuff->fSampledValue; + AdcBuff->uiSamplingCount++; + if (AdcBuff->uiSamplingCount >= 20U) + { + AdcBuff->uiSamplingCount = 0U; + AdcBuff->fSampledSum = AdcBuff->fSampledSum / 20.0F; + AdcBuff->fLpfValue = (0.01884955F * AdcBuff->fSampledSum) + ((1.0F - 0.01884955F) * AdcBuff->fLpfValue); // 0.01884955f = (PI2 * ADC_LPF_COFF * (1.0F / ADC_FREQ)) + AdcBuff->fLpfValue = (AdcBuff->fLpfValue < 0.0F) ? 0.0F : AdcBuff->fLpfValue; + AdcBuff->fSampledSum = 0.0F; + } +} + +static Uint32 CGetKey(void) +{ + const Uint16 uiKeyGpioList[(Uint16)IDX_KEY_MAX] = { 67U, 39U, 31U, 30U, 29U, 66U, 64U, 58U, 57U, 56U, 54U }; + + Uint16 i, ucDiv, ucMod; + Uint32 ulGpioData = 0UL, ulKeyRead = 0UL; + + /* + * ------GPIO Key List------ + * + * GPIO67 - POWER + * GPIO39 - UP Arrow + * GPIO31 - DOWN Arrow + * GPIO30 - ENTER + * GPIO29 - MENU + * GPIO66 - START + * GPIO64 - EMERGENCY + * GPIO58 - REMOTE START + * GPIO57 - REMOTE STOP + * GPIO56 - REMOTE EMERGENCY + * GPIO54 - REMOTE BATTLE MODE + * ------------------------- + */ + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + ucDiv = (Uint16)((Uint16)uiKeyGpioList[i] / 32U); + ucMod = (Uint16)((Uint16)uiKeyGpioList[i] % 32U); + + if (ucDiv == 0U) // GPIO-A + { + ulGpioData = GpioDataRegs.GPADAT.all; + } + else if (ucDiv == 1U) + { + ulGpioData = GpioDataRegs.GPBDAT.all; + } + else + { + ulGpioData = GpioDataRegs.GPCDAT.all; + } + + if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check + { + ulKeyRead |= (0x01UL << i); + } + } + return ulKeyRead; +} + +void CKeyCheckProcedure(void) +{ + // [전원키용 변수] + static Uint32 ulLongKeyCnt = 0UL; + static Uint16 uiLongKeyProcessed = 1U; // 전원 켤 때 한번 무시 + + // [StartStop키용 변수 추가] + static Uint32 ulStartKeyCnt = 0UL; // StartStop 롱키 카운트 + static Uint16 uiStartKeyProcessed = 0U; // StartStop 롱키 처리 플래그 + + static Uint32 ulPrevKey = 0UL; + Uint32 ulChangeKey; + Uint32 ulReadKey = CGetKey(); + + // 전원키(KEY_POWER_MASK)와 StartStop키(KEY_START_MASK) 둘 다 일반 변화 감지에서 제외 + ulChangeKey = (ulPrevKey ^ ulReadKey) & ~(KEY_POWER_MASK | KEY_START_MASK); + + if (ulChangeKey > 0UL) + { + if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작 + { + KeyOperValue.uiKeyWait = 1U; + KeyOperValue.uiKeyWaitCount = 20; // 20ms + } + else + { + if ((KeyOperValue.uiKeyWaitCount == 0U) && (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST)) + { + // ulPrevKey 갱신 시, 롱키 처리되는 비트들(Power, StartStop)은 기존 상태를 유지하고 나머지만 갱신 + ulPrevKey = (ulPrevKey & (KEY_POWER_MASK | KEY_START_MASK)) | (ulReadKey & ~(KEY_POWER_MASK | KEY_START_MASK)); + + CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작 + } + } + } + else + { + // 변화가 없으면 채터링 대기 초기화 (일반 키용) + if ((KeyOperValue.uiKeyWait != 0U) && (KeyOperValue.uiKeyWaitCount == 0U)) + { + KeyOperValue.uiKeyWait = 0U; + } + } + + // --------------------------------------------------------- + // 전원키 (Power Key) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedPowerKey = ulReadKey & KEY_POWER_MASK; + + if (ulPressedPowerKey != 0UL) + { + if (uiLongKeyProcessed == 0U) + { + ulLongKeyCnt++; + + // 롱키 시간 도달 시 동작 수행 + if (ulLongKeyCnt >= LONG_KEY_TIME) + { + // KEY_POWER_MASK 전체가 아닌 '실제로 눌린 키(ulPressedPowerKey)'를 전달 + CKeyCheck(ulPressedPowerKey, ulReadKey); + + uiLongKeyProcessed = 1U; // 처리 완료 플래그 + ulLongKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulLongKeyCnt = 0UL; + uiLongKeyProcessed = 0U; + + // ulPrevKey의 로컬 전원 키 비트를 모두 0으로 동기화 + ulPrevKey &= ~KEY_POWER_MASK; + } + + // --------------------------------------------------------- + // 시동/정지 키 (StartStop) 롱키 처리 (로컬 & 리모트 모두 포함) + // --------------------------------------------------------- + Uint32 ulPressedStartKey = ulReadKey & KEY_START_MASK; + + if (ulPressedStartKey != 0UL) + { + if (uiStartKeyProcessed == 0U) + { + ulStartKeyCnt++; // 카운트 증가 + + // 0.5초(500ms) 도달 시 동작 수행 + if (ulStartKeyCnt >= LONG_KEY_TIME) + { + // KEY_START_MASK가 아닌 '실제로 눌린 키(ulPressedStartKey)'를 전달 + CKeyCheck(ulPressedStartKey, ulReadKey); + + uiStartKeyProcessed = 1U; // 처리 완료 플래그 + ulStartKeyCnt = LONG_KEY_TIME; // 오버플로우 방지 + } + } + } + else + { + // 키를 뗐을 때 초기화 + ulStartKeyCnt = 0UL; + uiStartKeyProcessed = 0U; + + // ulPrevKey의 해당 비트(Bit 5, Bit 8) 모두 0으로 동기화 + ulPrevKey &= ~KEY_START_MASK; + } +} + +void CKeyWaitCount(void) +{ + if (KeyOperValue.uiKeyWait == 1U) + { + if (KeyOperValue.uiKeyWaitCount > 0U) + { + KeyOperValue.uiKeyWaitCount--; + } + else + { + KeyOperValue.uiKeyWait = 0U; + } + } +} + +static void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead) +{ + static const CKeyHandler KeyTable[(Uint16)IDX_KEY_MAX] = + { + { IDX_KEY_MAIN_POWER, &CKeyMainPowerProcess }, + { IDX_KEY_ARR_UP, &CKeyArrowUpProcess }, + { IDX_KEY_ARR_DOWN, &CKeyArrowDownProcess }, + { IDX_KEY_ENTER, &CKeyEnterProcess }, + { IDX_KEY_MENU, &CKeyMenuProcess }, + { IDX_KEY_ENG_START_STOP, &CKeyEngineStartStopProcess }, + { IDX_KEY_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_REMOTE_START, &CKeyRemoteEngineStartProcess }, + { IDX_KEY_REMOTE_STOP, &CKeyRemoteEngineStopProcess }, + { IDX_KEY_REMOTE_EMERGENCY, &CKeyEmergencyProcess }, + { IDX_KEY_BATTLE_MODE, &CKeyBattleModeProcess } + }; + + Uint16 i; + + for (i = 0U; i < (Uint16)IDX_KEY_MAX; i++) + { + if ((ulChangeKey & (0x1UL << i)) > 0U) + { + if ((ulKeyRead & (0x1UL << i)) > 0U) + { + KeyTable[i].pAction(); + } + } + } +} + +static void CProcessArrowUpPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU2) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + else + { + if ((OledOperValue.uiPageNum > (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U; + } + } +} + +static void CProcessArrowUpFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + // Go back to Menu 1 + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + else + { + CMoveFocusLine(4U, DIR_UP); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_UP); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + CMoveFocusLine(3U, DIR_UP); + } + } + } +} + +static void CKeyArrowUpProcess(void) +{ + CProcessArrowUpPageChange(); + CProcessArrowUpFocusChange(); +} + +static void CProcessArrowDownPageChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_APU1) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU2; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_SENSOR4)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_WARNING2)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U; + } + } +} + +static void CProcessArrowDownFocusChange(void) +{ + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_4) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_4; + } + else + { + CMoveFocusLine(4U, DIR_DOWN); + } + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_PASSWORD) + { + CChangePasswordDigit(DIR_DOWN); + } + else if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_RESET_ALARM) + { + OledOperValue.uiResetAlarmAnswer = (OledOperValue.uiResetAlarmAnswer == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_3; + } + else + { + CMoveFocusLine(3U, DIR_DOWN); + } + } + } +} + +static void CKeyArrowDownProcess(void) +{ + CProcessArrowDownPageChange(); + CProcessArrowDownFocusChange(); +} + +static void CChangePasswordDigit(Uint16 direction) +{ + if (OledOperValue.uiFocusDigit <= (Uint16)IDX_OLED_PASS_DIGIT_4) + { + Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit]; + + if (direction == DIR_UP) + { + *pDigit = (*pDigit + 1U) % 10U; + } + else // DIR_DOWN + { + if (*pDigit == 0U) + { + *pDigit = 9U; + } + else + { + *pDigit = (*pDigit - 1U) % 10U; + } + } + } +} + +static void CMoveFocusLine(Uint16 maxLines, Uint16 direction) +{ + if (maxLines > 0U) + { + if (direction == DIR_UP) + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + (Uint16)(maxLines - 1U)) % maxLines); + } + else /* DIR_DOWN */ + { + OledOperValue.uiFocusLine = (Uint16)((OledOperValue.uiFocusLine + 1U) % maxLines); + } + } +} + +static void CProcessEnterMenu1(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_MENU_APU: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + break; + } + case (Uint16)IDX_OLED_MENU_TEMP: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_TEMP; + break; + } + case (Uint16)IDX_OLED_MENU_SENSOR: + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SENSOR1; + break; + } + default: + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_MENU_WARNING) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_WARNING1; + } + break; + } + } +} + +static void CProcessEnterMenu2(void) +{ + switch (OledOperValue.uiFocusLine) + { + case (Uint16)IDX_OLED_LINE_FOCUS_1: // Fault + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_FAULT1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_2: // Reset + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_RESET_ALARM; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_3: // Maintenance + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_PASSWORD; + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + break; + } + case (Uint16)IDX_OLED_LINE_FOCUS_4: // Version + { + OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_VERSION; + break; + } + default: + { + break; + } + } +} + +static void CProcessEnterPassword(void) +{ + if (OledOperValue.uiFocusDigit < (Uint16)IDX_OLED_PASS_DIGIT_4) + { + OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U; + } + else + { + const Uint16 uiPassword[4] = MAINTENECE_PASSKEY; + Uint16 i; + Uint16 uiIsMatch = 1U; // 1U: 일치함, 0U: 불일치함 + + for (i = 0U; i < (Uint16)(sizeof(uiPassword) / sizeof(uiPassword[0])); i++) + { + if (GeneralOperValue.uiPassword[i] != uiPassword[i]) + { + uiIsMatch = 0U; // 하나라도 다르면 불일치 + break; + } + } + + if (uiIsMatch == 1U) + { + GeneralOperValue.uiMaintenance = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + OledOperValue.uiFocusLine = (Uint16)IDX_OLED_LINE_FOCUS_1; + } + else + { + OledOperValue.uiFocusDigit = (Uint16)IDX_OLED_PASS_DIGIT_1; + } + } +} + +static void CProcessEnterMaintenance(void) +{ + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) + { + GeneralOperValue.Maintenance.ManualCranking = (GeneralOperValue.Maintenance.ManualCranking == 1U) ? 0U : 1U; + } + else if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) + { + GeneralOperValue.Maintenance.LampTest = (GeneralOperValue.Maintenance.LampTest == 1U) ? 0U : 1U; + } + else + { + if (OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) + { + GeneralOperValue.Maintenance.KeyTest = (GeneralOperValue.Maintenance.KeyTest == 1U) ? 0U : 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_KEY_TEST; + } + } +} + +static void CKeyEnterProcess(void) +{ + switch (OledOperValue.uiPageNum) + { + case (Uint16)IDX_OLED_PAGE_MENU1: + { + CProcessEnterMenu1(); + break; + } + case (Uint16)IDX_OLED_PAGE_MENU2: + { + CProcessEnterMenu2(); + break; + } + case (Uint16)IDX_OLED_PAGE_PASSWORD: + { + CProcessEnterPassword(); + break; + } + case (Uint16)IDX_OLED_PAGE_MAINTENANCE: + { + CProcessEnterMaintenance(); + break; + } + case (Uint16)IDX_OLED_PAGE_RESET_ALARM: + { + if (OledOperValue.uiResetAlarmAnswer == 1U) + { + GeneralOperValue.uiAlarmReset = 1U; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + break; + } + default: + { + // Fault/Warning page return to main page + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_FAULT7)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + } + break; + } + } +} + +static void CKeyMenuProcess(void) +{ + // Return to main menus from sub-pages + if ((OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MENU2)) + { + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_APU1; + OledOperValue.uiFocusLine = 0U; + } + else + { + if ((OledOperValue.uiPageNum >= (Uint16)IDX_OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= (Uint16)IDX_OLED_PAGE_VERSION)) + { + // Return to Menu 2 from Faults or Debug + if (OledOperValue.uiPageNum == (Uint16)IDX_OLED_PAGE_MAINTENANCE) + { + GeneralOperValue.uiMaintenance = 0U; + OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine; + } + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU2; + } + else + { + // Return to Menu 1 from others (APU, Temp, Sensor, Warning) + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MENU1; + } + } +} + +static void CKeyMainPowerProcess(void) +{ + if (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_STANDBY) + { + // APU가 정지 상태에서만 전원 스위치 입력 가능 + KeyOperValue.KeyList.MainPower = 1U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_SHUTDOWN; + } +} + +static void CKeyEngineStartStopProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } + else + { + KeyOperValue.KeyList.EngineStartStop = 0U; + } +} + +static void CKeyRemoteEngineStartProcess(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + // 스탠바이 상태에서만 시동 시작 스위치 입력 받는다. + KeyOperValue.KeyList.EngineStartStop = 1U; + } +} + +static void CKeyRemoteEngineStopProcess(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; +} + +static void CKeyEmergencyProcess(void) +{ + KeyOperValue.KeyList.Emergency = KeyOperValue.KeyList.Emergency ^ 1U; +} + +static void CKeyBattleModeProcess(void) +{ + KeyOperValue.KeyList.BattleMode = KeyOperValue.KeyList.BattleMode ^ 1U; +} diff --git a/Source/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ b/Source/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/306227024c018cd03aca28832762ed44_ @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ b/Source/.staticdata/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ new file mode 100644 index 0000000..84b35e0 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/33009c837a13a198dda5c87e283a5091_ @@ -0,0 +1,208 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: April 17, 2008 11:08:27 $ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ b/Source/.staticdata/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ new file mode 100644 index 0000000..aef14e9 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/3639c9c8a3264ec88cb369751be62a8d_ @@ -0,0 +1,131 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: April 15, 2009 10:05:17 $ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ b/Source/.staticdata/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ new file mode 100644 index 0000000..5193241 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/3932151096406d1bbe5a24cc2d6f26ea_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: April 16, 2008 17:16:47 $ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ b/Source/.staticdata/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ new file mode 100644 index 0000000..e4a3271 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/3efcd47861f9989461f67b4f6afef174_ @@ -0,0 +1,109 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:39 $ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ b/Source/.staticdata/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ new file mode 100644 index 0000000..c497fb2 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/5087ebaeb4c90cf7a0a088e87497fcc2_ @@ -0,0 +1,291 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: May 12, 2008 14:30:08 $ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ b/Source/.staticdata/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ new file mode 100644 index 0000000..503f701 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/697fab38bd3b21b4ad4f4a941bea5997_ @@ -0,0 +1,239 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: January 22, 2008 16:55:35 $ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "DSP2833x_Adc.h" // ADC Registers +#include "DSP2833x_DevEmu.h" // Device Emulation Registers +#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "DSP2833x_ECap.h" // Enhanced Capture +#include "DSP2833x_DMA.h" // DMA Registers +#include "DSP2833x_EPwm.h" // Enhanced PWM +#include "DSP2833x_EQep.h" // Enhanced QEP +#include "DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "DSP2833x_I2c.h" // I2C Registers +#include "DSP2833x_Mcbsp.h" // McBSP +#include "DSP2833x_PieCtrl.h" // PIE Control Registers +#include "DSP2833x_PieVect.h" // PIE Vector Table +#include "DSP2833x_Spi.h" // SPI Registers +#include "DSP2833x_Sci.h" // SCI Registers +#include "DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "DSP2833x_XIntrupt.h" // External Interrupts +#include "DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ b/Source/.staticdata/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ new file mode 100644 index 0000000..b2beaa3 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/70868bbf531d9aa79c87c32e4788ee4e_ @@ -0,0 +1,1287 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: May 7, 2007 16:05:39 $ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ b/Source/.staticdata/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ new file mode 100644 index 0000000..9ee836d --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/75eb44d83379bf4f199984eafdfd4d93_ @@ -0,0 +1,179 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:07 $ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ b/Source/.staticdata/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ new file mode 100644 index 0000000..92e0022 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/7d86d3df0c09119c711baf3e0fc3da7a_ @@ -0,0 +1,265 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 16, 2007 09:00:21 $ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ b/Source/.staticdata/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ new file mode 100644 index 0000000..70f997b --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/7db20b7d65499aa92f223811bf4e2ee0_ @@ -0,0 +1,493 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: November 15, 2007 09:58:53 $ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 b/Source/.staticdata/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 new file mode 100644 index 0000000..03f9c19 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/87db14bcf223072d659483224d9ba3a7 @@ -0,0 +1,252 @@ +#ifndef SOURCE_MAIN_H_ +#define SOURCE_MAIN_H_ + +#include +#include "DSP28x_Project.h" +#include "DSP2833x_Device.h" +#include "State.h" +#include "Oper.h" +#include "Display.h" +#include "Comm.h" + +#define AUX_TEST + +#define true (1U) +#define false (0U) + +// Key Input Port (Lo Active) +#define GPIO_KEY_UP() (GpioDataRegs.GPBDAT.bit.GPIO39) // LOW Active +#define GPIO_KEY_DOWN() (GpioDataRegs.GPADAT.bit.GPIO31) // LOW Active +#define GPIO_KEY_ENTER() (GpioDataRegs.GPADAT.bit.GPIO30) // LOW Active +#define GPIO_KEY_MENU() (GpioDataRegs.GPADAT.bit.GPIO29) // LOW Active +#define GPIO_KEY_POWER() (GpioDataRegs.GPCDAT.bit.GPIO67) // LOW Active +#define GPIO_KEY_START() (GpioDataRegs.GPCDAT.bit.GPIO66) // LOW Active +#define GPIO_KEY_EMERGENCY() (GpioDataRegs.GPCDAT.bit.GPIO64) // LOW Active +#define GPIO_KEY_REMOTE_START() (GpioDataRegs.GPBDAT.bit.GPIO58) // LOW Active +#define GPIO_KEY_REMOTE_STOP() (GpioDataRegs.GPBDAT.bit.GPIO57) // LOW Active +#define GPIO_KEY_REMOTE_EMERGENCY() (GpioDataRegs.GPBDAT.bit.GPIO56) // LOW Active + +// Read ChipSelect State +#define ENGINE_HEATER_OUT() (GpioDataRegs.GPBDAT.bit.GPIO49) // HIGH is Active +#define GLOW_PLUG_OUT() (GpioDataRegs.GPADAT.bit.GPIO27) // HIGH is Active +#define SOLENOID_OUT() (GpioDataRegs.GPBDAT.bit.GPIO48) // HIGH is Active +#define FUEL_PUMP_OUT() (GpioDataRegs.GPADAT.bit.GPIO26) // HIGH is Active +#define COOLANT_PUMP_OUT() (GpioDataRegs.GPBDAT.bit.GPIO52) // HIGH is Active +#define FAN1_OUT() (GpioDataRegs.GPBDAT.bit.GPIO50) // HIGH is Active +#define FAN2_OUT() (GpioDataRegs.GPBDAT.bit.GPIO51) // HIGH is Active + +// Active Read From ECU +#define GPIO_ENGINE_HEATER_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO24) // LOW is Active +#define GPIO_GLOW_PLUG_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO10) // LOW is Active +#define GPIO_SOLENOID_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO11) // LOW is Active +#define GPIO_FUEL_PUMP_ACTIVE() (GpioDataRegs.GPADAT.bit.GPIO9) // LOW is Active + +// Fail-Safe Enable(ECU HW Emergency) +#define GPIO_FAIL_SAFE_READ() (GpioDataRegs.GPADAT.bit.GPIO25) // LOW is Active + +// Auxiliary Read all +#define STATUS_BIT_HEATER (0) +#define STATUS_BIT_GLOW (1) +#define STATUS_BIT_SOLENOID (2) +#define STATUS_BIT_FUEL (3) +#define STATUS_BIT_COOLANT (4) +#define STATUS_BIT_FAN1 (5) +#define STATUS_BIT_FAN2 (6) + +#define GET_ALL_AUX_STATUS() \ +( \ + (GpioDataRegs.GPBDAT.bit.GPIO49 << STATUS_BIT_HEATER) | \ + (GpioDataRegs.GPADAT.bit.GPIO27 << STATUS_BIT_GLOW) | \ + (GpioDataRegs.GPBDAT.bit.GPIO48 << STATUS_BIT_SOLENOID) | \ + (GpioDataRegs.GPADAT.bit.GPIO26 << STATUS_BIT_FUEL) | \ + (GpioDataRegs.GPBDAT.bit.GPIO52 << STATUS_BIT_COOLANT) | \ + (GpioDataRegs.GPBDAT.bit.GPIO50 << STATUS_BIT_FAN1) | \ + (GpioDataRegs.GPBDAT.bit.GPIO51 << STATUS_BIT_FAN2) \ +) + +/* Comment Description + * [!] : 변경시 주의 + * [?] : 결정이 필요 + * [*] : 주의보다 더 엄중 + */ + +/* Firmware 버전 (Semantic Versioning) */ +#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때 +#define FIRMWARE_VERSION_MINOR (1) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때 +#define FIRMWARE_VERSION_PATCH (9) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때 + +/* Version History + * [0.0.1] : DCU 프로젝트 생성 + * [0.0.2] : DCU 펌웨어 탑재 성공 + * [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현 + * [0.0.4] : OLED 표시 화면 구현 + * [0.0.5] : CAN-B 확인 및 맵핑 + * [0.0.6] : 시동 시퀀스 구현 및 정비 화면 수정 + * [0.1.6] : Suter 보조엔진 시동 완료 시점 + * [0.1.7] : 발전상태 전환 조건 추가 26-02-23 + * [0.1.8] : 장치 운용시간 로직 추가(Eeprom 사용), define USE_EEPROM 26-03-16 <삭제> + * [0.1.9] : IPS 회로 변경으로 전압센싱 추가 및 고장 알람 비트 추가, CAN-A 채널 송신 데이터 추가 26-03-26 + */ + +#define MAINTENECE_PASSKEY {0,0,0,0} + +#define ENABLED (1) +#define DISABLED (!ENABLED) + +/* + * Bit mask + */ +#define MASK_LOW_NIBBLE (0x0FU) +#define MASK_HIGH_NIBBLE (0xF0U) +#define MASK_BYTE (0xFFU) +#define MASK_WORD (0xFFFFU) +#define MASK_6BIT (0x3FU) +#define MASK_26BIT (0x3FFFFFFUL) + +/* +Timer Clock Per 100us +*/ +#define SYSTEM_10MIN_TIME (6000000UL) +#define TIME_01MS (10UL) +#define TIME_10MS (100UL) +#define TIME_20MS (200UL) +#define TIME_50MS (500UL) +#define TIME_100MS (1000UL) +#define TIME_500MS (5000UL) +#define TIME_1SEC (10000UL) +#define TIME_5SEC (50000UL) +#define TIME_10SEC (100000UL) +#define TIME_60SEC (600000UL) + +// 전압/전류센서 AdcRefValue 기준값 전압:2300, 전류:2250 +#define SENSOR_LOW_LIMIT (2000) // 단선 +#define SENSOR_HIGH_LIMIT (4000) // 단락 + +#define TIME_OVER (1U) + +enum +{ + TIMER_01MS = 0U, + TIMER_10MS, + TIMER_20MS, + TIMER_50MS, + TIMER_100MS, + TIMER_500MS, + TIMER_1SEC, + TIMER_MAX +}; + +enum +{ + SOFTTIMER_TIME_OVER = 0U, + SOFTTIMER_RUNNING, + SOFTTIMER_PAUSE, + SOFTTIMER_DONT_EXIST +}; + +enum +{ + SOFTTIMER_WAIT_INIT = 0U, + SOFTTIMER_WAIT_ALARM_RESET, + SOFTTIMER_WAIT_ENG_COOLDOWN, + SOFTTIMER_WAIT_PREHEAT, + SOFTTIMER_WAIT_CRANKING, + SOFTTIMER_WAIT_RETRY_CRANKING, + SOFTTIMER_WAIT_OPERATION, + SOFTTIMER_WAIT_SHUTDOWN, + SOFTTIMER_WAIT_AFTER_COOLDOWN, + SOFTTIMER_WAIT_MAX +}; + +typedef enum +{ + IDX_CS_ENG_HEATER = 0, + IDX_CS_GLOW_PLUG, + IDX_CS_SOLENOID, + IDX_CS_FUEL_PUMP, + IDX_CS_COOLANT_PUMP, + IDX_CS_FAN1, + IDX_CS_FAN2, + IDX_CS_MAX +} E_AUX_CS_IDX; + +typedef struct ClassSoftTimer +{ + Uint32 ulSetValue; + Uint32 ulDecreaseValue; + int16 iTimer; + int16 iStart; +} CSoftTimer; + +typedef struct ClassWaitTimer +{ + Uint32 ulCountSoftClock; + Uint16 uiSoftCountTarget; +} CWaitTimer; + +typedef enum +{ + IDX_SENSOR_ENGINE_HEATER = 0U, // 0 + IDX_SENSOR_GLOW_PLUG, // 1 + IDX_SENSOR_SOLENOID, // 2 + IDX_SENSOR_FUEL_PUMP, // 3 + IDX_SENSOR_COOLANT_PUMP, // 4 + IDX_SENSOR_FAN1, // 5 + IDX_SENSOR_FAN2, // 6 + IDX_SENSOR_MAX // 7 +} E_IDX_SENSOR; + +typedef struct ClassGeneralOperValue +{ + Uint16 uiFaultOccured; + Uint16 uiDynamicRPM; + Uint16 uiPassword[4]; + Uint16 uiSelfTestCheck; + Uint16 uiSelfTestPass; + Uint16 uiEmergency; + Uint16 uiApuStart; + Uint16 uiApuState; + Uint16 uiAlarmReset; + Uint16 uiMaintenance; + Uint16 uiRetryCrankingCount; + Uint16 uiWriteEepromDataStart; + Uint32 ulTotalOperationHour; + struct + { + Uint16 PlayCmd; + } GcuCommand; + struct + { + Uint16 EngineStart; + Uint16 EngineStop; + Uint16 RpmSetPoint; + Uint16 ActiveOverride; + Uint16 EmergencyStop; + } EcuCommand; + struct + { + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; + } Conection; + struct + { + Uint16 ManualCranking; + Uint16 LampTest; + Uint16 KeyTest; + } Maintenance; +} CGeneralOperValue; + +extern CGeneralOperValue GeneralOperValue; +extern Uint16 PowerOnCheckSensor[IDX_SENSOR_MAX]; + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime); +void COffChipSelect(void); +void CSoftWaitCountClear(Uint16 Index); +Uint32 CGetSoftClock(void); +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond); +void DELAY_USEC(Uint32 ulMicroSeconds); +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx); +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState); + +#endif /* SOURCE_MAIN_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ b/Source/.staticdata/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ new file mode 100644 index 0000000..0bb89df --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/886250910e6bddafd7e95146e1f5f406_ @@ -0,0 +1,167 @@ +// TI File $Revision: /main/9 $ +// Checkin $Date: July 2, 2008 14:31:12 $ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "DSP2833x_GlobalPrototypes.h" +#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ b/Source/.staticdata/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ new file mode 100644 index 0000000..ad554e1 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/9a0ce54b7ac8c23b398b7f623c6ec79f_ @@ -0,0 +1,154 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: July 27, 2009 13:57:25 $ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/Source/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 b/Source/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 new file mode 100644 index 0000000..b445fd3 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/_37542ab4f6589d7027e75c2a30519b32 @@ -0,0 +1,454 @@ +/*****************************************************************************/ +/* string.h */ +/* */ +/* Copyright (c) 1993 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include <_ti_config.h> + +#if defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) +#error "Header file not supported by CLA compiler" +#endif +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T_DECLARED +#define _SIZE_T_DECLARED +#ifdef __clang__ +typedef __SIZE_TYPE__ size_t; +#else +typedef __SIZE_T_TYPE__ size_t; +#endif +#endif + + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)) +#define _OPT_IDECL +#else +#define _OPT_IDECL _IDECL +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL size_t strlen(const char *string); + +_OPT_IDECL char *strcpy(char * __restrict dest, + const char * __restrict src); +_OPT_IDECL char *strncpy(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strcat(char * __restrict string1, + const char * __restrict string2); +_OPT_IDECL char *strncat(char * __restrict dest, + const char * __restrict src, size_t n); +_OPT_IDECL char *strchr(const char *string, int c); +_OPT_IDECL char *strrchr(const char *string, int c); + +_OPT_IDECL int strcmp(const char *string1, const char *string2); +_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n); + +_CODE_ACCESS int strcoll(const char *string1, const char *_string2); +_CODE_ACCESS size_t strxfrm(char * __restrict to, + const char * __restrict from, size_t n); +_CODE_ACCESS char *strpbrk(const char *string, const char *chs); +_CODE_ACCESS size_t strspn(const char *string, const char *chs); +_CODE_ACCESS size_t strcspn(const char *string, const char *chs); +_CODE_ACCESS char *strstr(const char *string1, const char *string2); +_CODE_ACCESS char *strtok(char * __restrict str1, + const char * __restrict str2); +_CODE_ACCESS char *strerror(int _errno); +_CODE_ACCESS char *strdup(const char *string); + + +_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n); + +_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count); + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */ +_CODE_ACCESS void *memcpy(void * __restrict s1, + const void * __restrict s2, size_t n); +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n); +_OPT_IDECL void *memchr(const void *cs, int c, size_t n); + +#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__) +_CODE_ACCESS void *memset(void *mem, int ch, size_t length); +#else +_OPT_IDECL void *memset(void *mem, int ch, size_t length); +#endif + +#if defined(__TMS320C2000__) && !defined(__TI_EABI__) + +#ifndef __cplusplus + +_TI_PROPRIETARY_PRAGMA("diag_push") + +/* keep macros as direct #defines and not function-like macros or function + names surrounded by parentheses to support all original supported use cases + including taking their address through the macros and prefixing with + namespace macros */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +#define far_memcpy __memcpy_ff +#define far_strcpy strcpy_ff + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +size_t far_strlen(const char *s); +char *strcpy_nf(char *s1, const char *s2); +char *strcpy_fn(char *s1, const char *s2); +char *strcpy_ff(char *s1, const char *s2); +char *far_strncpy(char *s1, const char *s2, size_t n); +char *far_strcat(char *s1, const char *s2); +char *far_strncat(char *s1, const char *s2, size_t n); +char *far_strchr(const char *s, int c); +char *far_strrchr(const char *s, int c); +int far_strcmp(const char *s1, const char *s2); +int far_strncmp(const char *s1, const char *s2, size_t n); +int far_strcoll(const char *s1, const char *s2); +size_t far_strxfrm(char *s1, const char *s2, size_t n); +char *far_strpbrk(const char *s1, const char *s2); +size_t far_strspn(const char *s1, const char *s2); +size_t far_strcspn(const char *s1, const char *s2); +char *far_strstr(const char *s1, const char *s2); +char *far_strtok(char *s1, const char *s2); +char *far_strerror(int _errno); +void *far_memmove(void *s1, const void *s2, size_t n); +void *__memcpy_nf (void *_s1, const void *_s2, size_t _n); +void *__memcpy_fn (void *_s1, const void *_s2, size_t _n); +void *__memcpy_ff (void *_s1, const void *_s2, size_t _n); +int far_memcmp(const void *s1, const void *s2, size_t n); +void *far_memchr(const void *s, int c, size_t n); +void *far_memset(void *s, int c, size_t n); +void *far_memlcpy(void *to, const void *from, + unsigned long n); +void *far_memlmove(void *to, const void *from, + unsigned long n); +#else /* __cplusplus */ +long far_memlcpy(long to, long from, unsigned long n); +long far_memlmove(long to, long from, unsigned long n); +#endif /* __cplusplus */ + +#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION) + +#if (defined(_STRING_IMPLEMENTATION) || \ + !(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__)))) + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ + +#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \ + defined(__TMS320C2000__) || \ + defined(__MSP430__))) +#define _OPT_IDEFN +#else +#define _OPT_IDEFN _IDEFN +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */ + +/* MISRA exceptions to avoid changing inline versions of the functions that + would be linked in instead of included inline at different mf levels */ +/* these functions are very well-tested, stable, and efficient; it would + introduce a high risk to implement new, separate MISRA versions just for the + inline headers */ + +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */ +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */ + +#if defined(_INLINE) || defined(_STRLEN) +_OPT_IDEFN size_t strlen(const char *string) +{ + size_t n = (size_t)-1; + const char *s = string; + + do n++; while (*s++); + return n; +} +#endif /* _INLINE || _STRLEN */ + +#if defined(_INLINE) || defined(_STRCPY) +_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src) +{ + char *d = dest; + const char *s = src; + + while ((*d++ = *s++)); + return dest; +} +#endif /* _INLINE || _STRCPY */ + +#if defined(_INLINE) || defined(_STRNCPY) +_OPT_IDEFN char *strncpy(char * __restrict dest, + const char * __restrict src, + size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + while ((*d++ = *s++) && --n); /* COPY STRING */ + if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */ + } + return dest; +} +#endif /* _INLINE || _STRNCPY */ + +#if defined(_INLINE) || defined(_STRCAT) +_OPT_IDEFN char *strcat(char * __restrict string1, + const char * __restrict string2) +{ + char *s1 = string1; + const char *s2 = string2; + + while (*s1) s1++; /* FIND END OF STRING */ + while ((*s1++ = *s2++)); /* APPEND SECOND STRING */ + return string1; +} +#endif /* _INLINE || _STRCAT */ + +#if defined(_INLINE) || defined(_STRNCAT) +_OPT_IDEFN char *strncat(char * __restrict dest, + const char * __restrict src, size_t n) +{ + if (n) + { + char *d = dest; + const char *s = src; + + while (*d) d++; /* FIND END OF STRING */ + + while (n--) + if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */ + *d = 0; + } + return dest; +} +#endif /* _INLINE || _STRNCAT */ + +#if defined(_INLINE) || defined(_STRCHR) +_OPT_IDEFN char *strchr(const char *string, int c) +{ + char tch, ch = c; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) return (char *) s; + if (!tch) return (char *) 0; + s++; + } +} +#endif /* _INLINE || _STRCHR */ + +#if defined(_INLINE) || defined(_STRRCHR) +_OPT_IDEFN char *strrchr(const char *string, int c) +{ + char tch, ch = c; + char *result = 0; + const char *s = string; + + for (;;) + { + if ((tch = *s) == ch) result = (char *) s; + if (!tch) break; + s++; + } + + return result; +} +#endif /* _INLINE || _STRRCHR */ + +#if defined(_INLINE) || defined(_STRCMP) +_OPT_IDEFN int strcmp(const char *string1, const char *string2) +{ + int c1, res; + + for (;;) + { + c1 = (unsigned char)*string1++; + res = c1 - (unsigned char)*string2++; + + if (c1 == 0 || res != 0) break; + } + + return res; +} +#endif /* _INLINE || _STRCMP */ + +#if defined(_INLINE) || defined(_STRNCMP) +_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n) +{ + if (n) + { + const char *s1 = string1; + const char *s2 = string2; + unsigned char cp; + int result; + + do + if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++))) + return result; + while (cp && --n); + } + return 0; +} +#endif /* _INLINE || _STRNCMP */ + +#if defined(_INLINE) || defined(_MEMCMP) +_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n) +{ + if (n) + { + const unsigned char *mem1 = (unsigned char *)cs; + const unsigned char *mem2 = (unsigned char *)ct; + int cp1, cp2; + + while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n); + return cp1 - cp2; + } + return 0; +} +#endif /* _INLINE || _MEMCMP */ + +#if defined(_INLINE) || defined(_MEMCHR) +_OPT_IDEFN void *memchr(const void *cs, int c, size_t n) +{ + if (n) + { + const unsigned char *mem = (unsigned char *)cs; + unsigned char ch = c; + + do + if ( *mem == ch ) return (void *)mem; + else mem++; + while (--n); + } + return NULL; +} +#endif /* _INLINE || _MEMCHR */ + +#if (((defined(_INLINE) || defined(_MEMSET)) && \ + !(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \ + !defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__)) +_OPT_IDEFN void *memset(void *mem, int ch, size_t length) +{ + char *m = (char *)mem; + + while (length--) *m++ = ch; + return mem; +} +#endif /* _INLINE || _MEMSET */ + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */ + +#endif /* (_INLINE || _STRING_IMPLEMENTATION) */ + +/*----------------------------------------------------------------------------*/ +/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */ +/* this file will have already included sys/cdefs.h. */ +/*----------------------------------------------------------------------------*/ +#if __has_include() +#include +#endif + +/*----------------------------------------------------------------------------*/ +/* Include xlocale/_string.h if POSIX is enabled. This will expose the */ +/* xlocale string interface. */ +/*----------------------------------------------------------------------------*/ +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +__BEGIN_DECLS +#include +__END_DECLS +#endif + +#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809 +_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict); +_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t); +#endif + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ! _STRING_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 b/Source/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 new file mode 100644 index 0000000..c46e599 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/_bb64ad2ba728094bd1eb236fd1301908 @@ -0,0 +1,74 @@ +/*****************************************************************************/ +/* linkage.h */ +/* */ +/* Copyright (c) 1998 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef _LINKAGE +#define _LINKAGE + +#pragma diag_push +#pragma CHECK_MISRA("-19.4") /* macros required for implementation */ + +/* No modifiers needed to access code */ + +#define _CODE_ACCESS + +/*--------------------------------------------------------------------------*/ +/* Define _DATA_ACCESS ==> how to access RTS global or static data */ +/*--------------------------------------------------------------------------*/ +#define _DATA_ACCESS +#define _DATA_ACCESS_NEAR + +/*--------------------------------------------------------------------------*/ +/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ +/*--------------------------------------------------------------------------*/ +#ifndef _OPTIMIZE_FOR_SPACE +#define _OPTIMIZE_FOR_SPACE 1 +#endif + +/*--------------------------------------------------------------------------*/ +/* Define _IDECL ==> how inline functions are declared */ +/*--------------------------------------------------------------------------*/ +#ifdef _INLINE +#define _IDECL static __inline +#define _IDEFN static __inline +#else +#define _IDECL extern _CODE_ACCESS +#define _IDEFN _CODE_ACCESS +#endif + +#pragma diag_pop + +#endif /* _LINKAGE */ diff --git a/Source/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc b/Source/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc new file mode 100644 index 0000000..6ad334e --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/_bbbf7244a602c743d7694c03650a07cc @@ -0,0 +1,145 @@ +/*****************************************************************************/ +/* _ti_config.h */ +/* */ +/* Copyright (c) 2017 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ + +#ifndef __TI_CONFIG_H +#define __TI_CONFIG_H + +/*Unsupported pragmas are omitted */ +#ifdef __TI_COMPILER_VERSION__ +# pragma diag_push +# pragma CHECK_MISRA("-19.7") +# pragma CHECK_MISRA("-19.4") +# pragma CHECK_MISRA("-19.1") +# pragma CHECK_MISRA("-19.15") +# define _TI_PROPRIETARY_PRAGMA(arg) _Pragma(arg) +# pragma diag_pop +#else +# define _TI_PROPRIETARY_PRAGMA(arg) +#endif + +_TI_PROPRIETARY_PRAGMA("diag_push") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") +_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")") + +/* Hide uses of the TI proprietary macros behind other macros. + Implementations that don't implement these features should leave + these macros undefined. */ +#ifdef __TI_COMPILER_VERSION__ +# ifdef __TI_STRICT_ANSI_MODE__ +# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# endif + +# ifdef __TI_STRICT_FP_MODE__ +# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__ +# else +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +# endif + +# ifdef __unsigned_chars__ +# define __TI_PROPRIETARY_UNSIGNED_CHARS__ __unsigned_chars__ +# else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# endif +#else +# undef __TI_PROPRIETARY_UNSIGNED_CHARS__ +# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO +# undef __TI_PROPRIETARY_STRICT_FP_MACRO +#endif + +/* Common definitions */ + +#if defined(__cplusplus) +/* C++ */ +# if (__cplusplus >= 201103L) + /* C++11 */ +# define _TI_NORETURN [[noreturn]] +# define _TI_NOEXCEPT noexcept +# else + /* C++98/03 */ +# define _TI_NORETURN __attribute__((noreturn)) +# define _TI_NOEXCEPT throw() +# endif +#else +/* C */ +# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) + /* C11 */ +# define _TI_NORETURN _Noreturn +# else + /* C89/C99 */ +# define _TI_NORETURN __attribute__((noreturn)) +# endif +# define _TI_NOEXCEPT +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201103L) +# define _TI_CPP11LIB 1 +#endif + +#if defined(__cplusplus) && (__cplusplus >= 201402L) +# define _TI_CPP14LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \ + defined(_TI_CPP11LIB) +# define _TI_C99LIB 1 +#endif + +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \ + defined(_TI_CPP14LIB) +# define _TI_C11LIB 1 +#endif + +/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It + is intended to be used for functions like abort and atexit that are supposed + to be declared noexcept only in C++14 mode. */ +#ifdef _TI_CPP14LIB +# define _TI_NOEXCEPT_CPP14 noexcept +#else +# define _TI_NOEXCEPT_CPP14 +#endif + + + +/* Target-specific definitions */ +#include + +_TI_PROPRIETARY_PRAGMA("diag_pop") + +#endif /* ifndef __TI_CONFIG_H */ diff --git a/Source/.staticdata/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ b/Source/.staticdata/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ new file mode 100644 index 0000000..3525283 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/a238f24a12d162e9b2f5ced950871316_ @@ -0,0 +1,270 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:13 $ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ b/Source/.staticdata/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ new file mode 100644 index 0000000..8df44c2 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/ab46c8fc7e4c370330d79d16627736d7_ @@ -0,0 +1,465 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:10 $ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 b/Source/.staticdata/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 new file mode 100644 index 0000000..678488d --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/b5d424479a96c0e4f4fc5ca18a4ffdc3 @@ -0,0 +1,730 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitSystem(void); +static void COledDisplay(void); +static void CInitGeneralOperValue(void); +static void CInitGpio(void); +static void CSystemConfigure(void); +static void CMappingInterrupt(void); +static void CProcessSoftTimer(void); +static void CShutdownProcedure(void); +static Uint16 CPowerOnCheck(void); +static void CSoftTimerWorkProcess(void); +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex); +static void CReloadSoftTimer(Uint16 uiTimerIndex); +static void CInitSoftTimers(void); +static void CInitSoftTimer(void); +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay); +static void CStartSoftTimer(Uint16 uiTimerIndex); +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock); +static void CInitI2C(void); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +Uint16 PowerOnCheckSensor[(Uint16)IDX_SENSOR_MAX] = { 0U }; + +CGeneralOperValue GeneralOperValue; + +static CSoftTimer SoftTimer[TIMER_MAX]; +static CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX]; +static Uint32 ulSoftClock; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +int main(void) +{ + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_BOOT; + + CInitSystem(); + + CInitOled(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_INITIAL; + + AdcOperValue.uiOffsetAdjustStart = 1U; // AD 보정 시작 + + for ( ; ; ) + { + CShutdownProcedure(); + + CSoftTimerWorkProcess(); + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + if (OledOperValue.uiProgressDone == 1U) + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == (Uint16)TIME_OVER) + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_POST; // Adc 보정완료 이 후 POST 시작 + } + } + } + else if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + if (GeneralOperValue.uiSelfTestCheck == 0U) + { + GeneralOperValue.uiSelfTestCheck = 1U; // 한번만 체크하기 위함 + + GeneralOperValue.uiSelfTestPass = CPowerOnCheck(); // 1 : 정상, 0 : 비정상 + } + else + { + if (GeneralOperValue.uiSelfTestPass == 1U) // 1 : 정상 + { + COledBufferReset(); + + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } + } + } + else + { +#ifdef AUX_TEST + if (Rx400.AuxControl.AuxTestStart == 1U) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, (Rx400.AuxControl.EngineHeater != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, (Rx400.AuxControl.GlowPlug != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, (Rx400.AuxControl.Solenoid != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, (Rx400.AuxControl.FuelPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, (Rx400.AuxControl.CoolantPump != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, (Rx400.AuxControl.Fan1 != 0U) ? 1U : 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, (Rx400.AuxControl.Fan2 != 0U) ? 1U : 0U); + } + // 정비 모드가 꺼져있어야 시퀀스 동작. + else if (GeneralOperValue.uiMaintenance == 0U) +#else + if (GeneralOperValue.uiMaintenance == 0U) +#endif + { + if (KeyOperValue.KeyList.MainPower == 0U) // 전원 스위치를 눌러서 shutdown 상태면 프로시저 OFF + { + CApuOperProcedure(); // 엔진 운영 프로시저 + + CLedControlProcedure(); // LED 제어 프로시저 + } + } + else + { + CDebugModeProcedure(); + } + } + } +} + +static void CSoftTimerWorkProcess(void) +{ + Uint16 ui01msExcute; + Uint16 ui10msExcute; + Uint16 ui100msExcute; + + ui01msExcute = CIsStatusSoftTimer(TIMER_01MS); + ui10msExcute = CIsStatusSoftTimer(TIMER_10MS); + ui100msExcute = CIsStatusSoftTimer(TIMER_100MS); + + if (ui01msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_01MS); + + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_POST) // ADC 오프셋 보정 완료 후 감지 + { + CAlarmProcedure(); + CDisplayAlarmPopup(); + } + + // (정비모드:키테스트)가 아니면 키 입력 처리 시작 함. + if (GeneralOperValue.Maintenance.KeyTest == 0U) + { + CKeyCheckProcedure(); + CKeyWaitCount(); + } + } + + if (ui10msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_10MS); + + CSendECanDataB(); + COledDisplay(); + } + + if (ui100msExcute == (Uint16)SOFTTIMER_TIME_OVER) + { + CReloadSoftTimer(TIMER_100MS); + CSendECanDataA(); + CDisplayAntiNoiseRefresh(); + } +} + +static void COledDisplay(void) +{ + static Uint16 RefeshDelay = 0U; + + // 부트 상태 이 후 프로그래스바 화면 표시용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_INITIAL) + { + CInitializePage(); + } + else + { + if (RefeshDelay == 0U) // 10ms 주기를 위함 + { + // POST 상태 표시 용 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_POST) + { + CDisplayPostFail(); + } + else + { + // POST 이 후 화면 표시용 + CSetPage(OledOperValue.uiPageNum); + } + } + RefeshDelay = (RefeshDelay + 1U) % 10U; + } + + COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT); +} + +void CSoftWaitCountClear(Uint16 Index) +{ + WaitTimer[Index].ulCountSoftClock = 0U; + WaitTimer[Index].uiSoftCountTarget = 0U; +} + +static Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex) +{ + Uint16 isRunning = 1U; + + if (SoftTimer[uiTimerIndex].iStart != -1) + { + if (SoftTimer[uiTimerIndex].iStart == 1) + { + if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U) + { + isRunning = (Uint16)SOFTTIMER_TIME_OVER; // Success + } + else + { + isRunning = (Uint16)SOFTTIMER_RUNNING; + } + } + } + + return isRunning; +} + +static void CReloadSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue; + } +} + +Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime) +{ + Uint16 isCountOver = 0U; + + switch (WaitTimer[uiIndex].uiSoftCountTarget) + { + case 0U: + { + WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock(); + WaitTimer[uiIndex].uiSoftCountTarget = 1U; + break; + } + case 1U: + { + if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == (Uint16)SOFTTIMER_TIME_OVER) + { + WaitTimer[uiIndex].uiSoftCountTarget = 2U; + } + break; + } + default: + { + WaitTimer[uiIndex].ulCountSoftClock = 0U; + WaitTimer[uiIndex].uiSoftCountTarget = 0U; + isCountOver = 1U; + break; + } + } + + return isCountOver; +} + +static Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock) +{ + Uint16 isRunning = 1U; + Uint32 ulCpuClock = CGetSoftClock(); + + if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock) + { + isRunning = 0U; + } + + return isRunning; +} + +Uint32 CGetSoftClock(void) +{ + return ulSoftClock; +} + +static void CInitSystem(void) +{ + DINT; + IER = 0x0000; + IFR = 0x0000; + + InitSysCtrl(); + + CInitGpio(); // GPIO Direction and mux + + InitPieCtrl(); + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + InitCpuTimers(); + + ConfigCpuTimer(&CpuTimer0, 150.0F, 100.0F); // 100usec + + CSystemConfigure(); + + EINT; // Enable Global interrupt INTM + ERTM; // Enable Global realtime interrupt DBGM + + CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0 +} + +static void CInitGpio(void) +{ + EALLOW; + + // GPIO MUX Setting + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA + + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA) + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA) + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA) + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA) + + // GPIO Direction Setting '1' Output, '0' Input + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER_SIG_C + GpioCtrlRegs.GPADIR.bit.GPIO25 = 0U; // GPIO_FAIL_SAFE_ENABLE_C + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0U; // GPIO_BATTLEMODE_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U; // GPIO_EMERGENCY_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0U; // GPIO_STOP_CMD_CS + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 0U; // GPIO_START_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR + + GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2 + GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1 + GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS + GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS + GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS + GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA + + // GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous + GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT + GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT + GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT + + GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 1U; // 3 Clk Sampling + + // Gpio Default Value Initial + GpioDataRegs.GPCSET.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + + GpioDataRegs.GPCSET.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT_N + GpioDataRegs.GPCSET.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN_N + GpioDataRegs.GPCSET.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA_N + + EDIS; +} + +void COffChipSelect(void) +{ + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, 0U); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, 0U); + CSetAuxCtrlPin(IDX_CS_SOLENOID, 0U); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 0U); + CSetAuxCtrlPin(IDX_CS_FAN1, 0U); + CSetAuxCtrlPin(IDX_CS_FAN2, 0U); +} + +static interrupt void CMainTimer0Interrupt(void) +{ + // Per 100uSec + + DINT; + + ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME; + + CProcessSoftTimer(); + // Do Something + + AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start + + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + EINT; +} + +static void CSystemConfigure(void) +{ + CMappingInterrupt(); + + CInitGeneralOperValue(); + + CInitAdc(); + CInitEcan(); + + CInitI2C(); + + CInitXintf(); + + CInitSoftTimers(); + + CInitKeyOperValue(); +} + +static void CInitGeneralOperValue(void) +{ + (void)memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue)); + + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] = 0; + GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] = 0; + + GeneralOperValue.EcuCommand.EngineStop = 1U; +} + +static void CMappingInterrupt(void) +{ + EALLOW; + + // Interrupt Vector Remapping + PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0 + PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC + PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA + PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB + + PieVectTable.TINT0 = &CMainTimer0Interrupt; + PieVectTable.ECAN0INTA = &CECanInterruptA; + PieVectTable.ECAN0INTB = &CECanInterruptB; + PieVectTable.ADCINT = &CAdcInterrupt; + + IER = (Uint16)((Uint16)M_INT1 | (Uint16)M_INT9); + + EDIS; +} + +static void CProcessSoftTimer(void) +{ + Uint16 i; + + for (i = 0U; i < (Uint16)TIMER_MAX; i++) + { + if (SoftTimer[i].iTimer != -1) + { + if (SoftTimer[i].iStart == 1) + { + if (SoftTimer[i].ulDecreaseValue > 0UL) + { + SoftTimer[i].ulDecreaseValue--; + } + } + } + } +} + +static void CInitSoftTimers(void) +{ + CInitSoftTimer(); + CConfigSoftTimer(TIMER_01MS, TIME_01MS); + CConfigSoftTimer(TIMER_10MS, TIME_10MS); + CConfigSoftTimer(TIMER_20MS, TIME_20MS); + CConfigSoftTimer(TIMER_50MS, TIME_50MS); + CConfigSoftTimer(TIMER_100MS, TIME_100MS); + CConfigSoftTimer(TIMER_500MS, TIME_500MS); + + CStartSoftTimer(TIMER_01MS); + CStartSoftTimer(TIMER_10MS); + CStartSoftTimer(TIMER_20MS); + CStartSoftTimer(TIMER_50MS); + CStartSoftTimer(TIMER_100MS); + CStartSoftTimer(TIMER_500MS); +} + +static void CStartSoftTimer(Uint16 uiTimerIndex) +{ + if (SoftTimer[uiTimerIndex].iTimer != -1) + { + SoftTimer[uiTimerIndex].iStart = 1; + } +} + +static void CInitSoftTimer(void) +{ + Uint16 i; + + (void)memset(&SoftTimer, 0, sizeof(SoftTimer)); + (void)memset(&WaitTimer, 0, sizeof(WaitTimer)); + + for (i = 0; i < (Uint16)TIMER_MAX; i++) + { + SoftTimer[i].iTimer = -1; + } +} + +static void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay) +{ + SoftTimer[TimerIndex].iTimer = (int16) TimerIndex; + SoftTimer[TimerIndex].ulSetValue = Delay; + SoftTimer[TimerIndex].ulDecreaseValue = Delay; + SoftTimer[TimerIndex].iStart = 0; +} + +static Uint16 CPowerOnCheck(void) +{ + Uint16 result = 1U; + Uint16 uiTemp = 0U; + Uint16 i; + + // Check EngineHeater V/I Sensor + uiTemp = ((Adc_EngineHeater_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_EngineHeater_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER] = uiTemp; + + // Check GlowPlug V/I Sensor + uiTemp = ((Adc_GlowPlug_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_GlowPlug_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG] = uiTemp; + + // Check Solenoid V/I Sensor + uiTemp = ((Adc_Solenoid_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Solenoid_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID] = uiTemp; + + // Check FuelPump V/I Sensor + uiTemp = ((Adc_FuelPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_FuelPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP] = uiTemp; + + // Check CoolantPump V/I Sensor + uiTemp = ((Adc_CoolantPump_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_CoolantPump_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP] = uiTemp; + + // Check Fan1 V/I Sensor + uiTemp = ((Adc_Fan1_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan1_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1] = uiTemp; + + // Check Fan2 V/I Sensor + uiTemp = ((Adc_Fan2_V.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_V.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + uiTemp |= ((Adc_Fan2_I.iAdcValue > SENSOR_LOW_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_HIGH_LIMIT)) ? 0U : 1U; + PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2] = uiTemp; + + for (i = 0U; i < (Uint16)IDX_SENSOR_MAX; i++) + { + if (PowerOnCheckSensor[i] > 0U) + { + result = 0U; + break; + } + } + return result; // '0' 정상 +} + +static void CInitI2C(void) +{ + /* I2C 모듈 리셋 */ + I2caRegs.I2CMDR.bit.IRS = 0U; + + /* + * 1. I2C 프리스케일러 (I2CPSC) 설정 + * SYSCLKOUT = 150MHz 기준 + * 10MHz = 150MHz / (14 + 1) -> I2CPSC = 14 + */ + I2caRegs.I2CPSC.all = 14U; + + /* + * 2. I2C 마스터 클럭 (SCL) 설정 + * 10MHz / 400kHz = 25 -> (I2CCLKL + 5) + (I2CCLKH + 5) = 25 + */ + //I2caRegs.I2CCLKL = 45U; // 100kHz + //I2caRegs.I2CCLKH = 45U; // 100kHz + I2caRegs.I2CCLKL = 8U; // 400kHz + I2caRegs.I2CCLKH = 7U; // 400kHz + + /* + * 3. I2C 핀 설정 (GPIO32/SDAA, GPIO33/SCLA) + */ + EALLOW; + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0U; /* Pull-up 활성화 (SDAA) */ + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0U; /* Pull-up 활성화 (SCLA) */ + + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3U; /* 비동기 입력 설정 */ + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3U; /* 비동기 입력 설정 */ + + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1U; /* GPIO32를 SDAA로 설정 */ + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1U; /* GPIO33을 SCLA로 설정 */ + EDIS; + + /* I2C 모듈 활성화 (리셋 해제 및 기본 설정 적용) */ + I2caRegs.I2CMDR.all = 0x0020U; +} + +static void CShutdownProcedure(void) +{ + if (KeyOperValue.KeyList.MainPower == 1U) + { + // 장치의 전원을 끄기 전 모든 제어상태를 정지 한다. + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + COffChipSelect(); + + if (GeneralOperValue.uiWriteEepromDataStart == 0U) + { + GeneralOperValue.uiWriteEepromDataStart = 1U; + } + + // 최대 3초 경과 후 꺼짐 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, (TIME_1SEC * 3U)) == (Uint16)TIME_OVER) + { + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD + } + } +} + +void CUpdateFault(Uint32 *pData, Uint16 uiIdx, Uint16 uiCond) +{ + Uint32 ulMask; + + if (pData != NULL) + { + ulMask = 1UL << (Uint32)uiIdx; + *pData = (uiCond != 0U) ? (*pData | ulMask) : (*pData & ~ulMask); + } +} + +Uint16 CIsBitSet(Uint32 ulData, Uint16 uiIdx) +{ + Uint32 ulMask; + + ulMask = 1UL << (Uint32)uiIdx; + + return (((ulData & ulMask) != 0UL) ? 1U : 0U); +} + +void DELAY_USEC(Uint32 ulMicroSeconds) +{ + Uint32 ulDelayCount; + + ulDelayCount = (Uint32)((float64)(((((float64)ulMicroSeconds * 1000.0L) / (float64)CPU_RATE) - 9.0L) / 5.0L)); + + DSP28x_usDelay(ulDelayCount); +} + +void CSetAuxCtrlPin(E_AUX_CS_IDX eIdx, Uint16 uiState) +{ + switch (eIdx) + { + case IDX_CS_ENG_HEATER: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO49 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1U; } + break; + } + case IDX_CS_GLOW_PLUG: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO27 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO27 = 1U; } + break; + } + case IDX_CS_SOLENOID: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO48 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1U; } + break; + } + case IDX_CS_FUEL_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPASET.bit.GPIO26 = 1U; } + else { GpioDataRegs.GPACLEAR.bit.GPIO26 = 1U; } + break; + } + case IDX_CS_COOLANT_PUMP: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO52 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1U; } + break; + } + case IDX_CS_FAN1: + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO50 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1U; } + break; + } + default: + { + if (eIdx == IDX_CS_FAN2) + { + if (uiState == 1U) { GpioDataRegs.GPBSET.bit.GPIO51 = 1U; } + else { GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1U; } + } + break; + } + } +} diff --git a/Source/.staticdata/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 b/Source/.staticdata/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 new file mode 100644 index 0000000..5fcdbd5 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/b677a266db0b1d5e23cf54c2eb3101a8 @@ -0,0 +1,696 @@ +#ifndef SOURCE_COMM_H_ +#define SOURCE_COMM_H_ + +typedef struct ClassCommCheck +{ + Uint16 CarComputer; + Uint16 Gcu; + Uint16 Ecu; +} CCommCheck; + +typedef struct ClassTx100 +{ + /* BYTE 0~1 */ + Uint16 Heartbit; + + /* BYTE 2~4 Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CTx100; + +typedef struct ClassTx101 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0~3 bit + + /* BYTE 1 */ + Uint16 DcuState; // bit 0:AlarmOccured, 1:Emergency, 2:PowerSwitch, 3:EcuFailSafe + + /* BYTE 2~7 Reserved */ + +} CTx101; + +typedef struct ClassTx102 +{ + /* BYTE 0 */ + Uint16 GcuCommand; // bit 0~3:PlayCommand, 4:FaultReset, 5:Emergency + + /* BYTE 1~7 Reserved */ + +} CTx102; + + +typedef struct ClassTx103 +{ + /* BYTE 0 */ + Uint16 EngineStart; + + /* BYTE 1 */ + Uint16 EngineStop; + + /* BYTE 2 */ + Uint16 FaultReset; + + /* BYTE 3 Reserved */ + + /* BYTE 4~5 */ + Uint16 RpmSetpoint; + + /* BYTE 6 */ + Uint16 ActiveOverride; + + /* BYTE 7 */ + Uint16 EmergencyStop; + +} CTx103; + +typedef struct ClassTx110 +{ + /* BYTE 0~3 */ + Uint16 DcuFaultB0; + Uint16 DcuFaultB1; + Uint16 DcuFaultB2; + Uint16 DcuFaultB3; + + /* BYTE 4~7 - Reserved */ + +} CTx110; + +typedef struct ClassTx120 +{ + /* BYTE 0 */ + Uint16 AuxTotal; // bit 0:EngineHeater, 1:GlowPlug, 2:Solenoid, 3:FuelPump, 4:CoolantPump, 5:Fan1, 6:Fan2 + + /* BYTE 1~7 - Reserved */ + +} CTx120; + +typedef struct ClassTx121 +{ + /* BYTE 0~1 */ + Uint16 EngHeatVoltage; + + /* BYTE 2~3 */ + Uint16 EngHeatCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx121; + +typedef struct ClassTx122 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx122; + +typedef struct ClassTx123 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx123; + +typedef struct ClassTx124 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx124; + +typedef struct ClassRx200 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2~4 - Reserved */ + + /* BYTE 5 */ + Uint16 VersionMajor; + + /* BYTE 6 */ + Uint16 VersionMinor; + + /* BYTE 7 */ + Uint16 VersionPatch; +} CRx200; + +typedef struct ClassRx201 +{ + /* BYTE 0 */ + Uint16 PlayState; // 0:3 bit PlayState + + /* BYTE 1 */ + Uint16 State; // bit 0:AlarmOccured, 1:Shutdown + + /* BYTE 2~7 - Reserved */ + +} CRx201; + +typedef struct ClassRx210 +{ + /* BYTE 0~1 */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:GenOverHeat1 + * 3:GenOverHeat2 + */ + Uint16 GcuWarning; + + /* BYTE 2~3 */ + /* + * bit description + * 0:HwTrip + * 1:HwIgbt + * 2:HwDc + * 3:GenOverCurrentU + * 4:GenOverCurrentV + * 5:GenOverCurrentW + * 6:DcOverVoltage + * 7:DcOverCurrent + * + * 8:CrankningOverCurrent + * 9:PcbOverHeat + * 10:FetOverHeat + * 11:GenTempOverHeat1 + * 12:GenTempOverHeat2 + * 13:GenOverSpeed + * 14:ResolverIC + * 15:ResolverParity + */ + Uint16 GcuFault; + + /* BYTE 4~7 - Reserved*/ + +} CRx210; + +typedef struct ClassRx220 +{ + /* BYTE 0~1 */ + Uint16 DcVoltage; + + /* BYTE 2~3 */ + Uint16 DcCurrent; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CRx220; + +typedef struct ClassRx221 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 GenTemperature1; + + /* BYTE 3 */ + Uint16 GenTemperature2; + + /* BYTE 4~7 - Reserved */ + +} CRx221; + +typedef struct ClassRx300 +{ + /* BYTE 0 */ + Uint16 VersionMajor; + + /* BYTE 1 */ + Uint16 VersionMinor; + + /* BYTE 2 */ + Uint16 VersionPatch; + + /* BYTE 3~7 - Reserved */ + +} CRx300; + +typedef struct ClassRx301 +{ + + /* BYTE 0 */ + /* + * bit description + * 0:AlarmOccured + * 1~3:PlayState + * 4:OverrideActive + * 5:GlowPlugActive + * 6:HeaterActive + * 7:OilPressureMissing + */ + Uint16 State; + + /* BYTE 1~7 - Reserved */ + +} CRx301; + +typedef struct ClassRx310 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensor + * 7:DefaltValueActive + */ + Uint16 EcuWarning; + + /* BYTE 1 - Reserved */ + + /* BYTE 2 */ + /* + * bit description + * 0:OilPressureMissing + * 1:IntakeOverHeat + * 2:EngineOverHeat + * 3:Actuator + * 4:RpmSignal + * 5:EngineStartFail + * 6:Reserved + * 7:Reserved + */ + Uint16 EcuFault; + + /* BYTE 3~7 - Reserved */ + +} CRx310; + +typedef struct ClassRx320 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CRx320; + +typedef struct ClassRx321 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 BarometricPressure; + + /* BYTE 6~7 - Reserved */ + +} CRx321; + +typedef struct ClassRx322 +{ + /* BYTE 0~1 */ + Uint16 TotalOperTimeL : 16; + + /* BYTE 2~3 */ + Uint16 TotalOperTimeH : 16; + + /* BYTE 4~7 - Reserved*/ + +} CRx322; + +typedef struct ClassTx700 +{ + /* BYTE 0~1 */ + Uint16 HeartBit; + + /* BYTE 2 */ + Uint16 DCUversionMajor; + + /* BYTE 3 */ + Uint16 DCUversionMinor; + + /* BYTE 4 */ + Uint16 GCUversionMajor; + + /* BYTE 5 */ + Uint16 GCUversionMinor; + + /* BYTE 6 */ + Uint16 ECUversionMajor; + + /* BYTE 7 */ + Uint16 ECUversionMinor; +} CTx700; + +typedef struct ClassTx701 +{ + /* BYTE 0 */ + Uint16 DcuPlayState; // bit 0~3:PlayState + + /* BYTE 1 */ + /* + * bit description + * 0:DcuAlarmOccured + * 1:DcuEmergencyStop + * 2:PowerSwitchPush + * 3:EcuFailSafe + */ + Uint16 DcuState; + + /* BYTE 2 */ + Uint16 GcuPlayState; // bit 0~2:GcuPlayState + + /* BYTE 3 */ + /* + * bit description + * 0:GcuAlarmOccured + * 1:GcuShutdown + */ + Uint16 GcuState; + + /* BYTE 4 */ + /* + * bit description + * 0:EcuAlarmOccured + * 1~3:EcuPlayState + * 4:ActiveOverride + * 5:ActiveGlowPlug + * 6:ActiveEngHeater + * 7:OilPressureMissing + */ + Uint16 EcuState; + + /* BYTE 5~7 - Reserved */ + +} CTx701; + +typedef struct ClassTx710 +{ + /* BYTE 0 - GCU Warning */ + /* + * bit description + * 0:PcbOverHeat + * 1:FetOverHeat + * 2:Winding1OverHeat + * 3:Winding2OverHeat + */ + Uint16 GcuWarning; + + /* BYTE 1 - ECU Warning */ + /* + * bit description + * 0:EngineOverHeat + * 1:Reserved + * 2:LoOilPressure + * 3:IntakeOverHeat + * 4:IntakeLoPressure + * 5:EngineLoTemperature + * 6:EngineSensorFault + * 7:DefaultValueActive + */ + Uint16 EcuWarning; + + /* BYTE 2~7 - Reserved */ + +} CTx710; + +typedef struct ClassTx720 +{ + /* BYTE 0~3 - DCU Fault */ + Uint16 DcuFault0; + Uint16 DcuFault1; + Uint16 DcuFault2; + Uint16 DcuFault3; + + /* BYTE 4~5 - GCU Fault */ + Uint16 GcuFault0; + Uint16 GcuFault1; + + /* BYTE 6 - Reserved */ + + /* BYTE 7 */ + Uint16 EcuFault; +} CTx720; + +typedef struct ClassTx730 +{ + /* BYTE 0 */ + /* + * bit description + * 0:EngineHeater + * 1:GlowPlug + * 2:Solenoid + * 3:FuelPump + * 4:CoolantPump + * 5:Fan1 + * 6:Fan2 + * 7:Reserved + */ + Uint16 AuxState; + + /* BYTE 1~7 - Reserved */ + +} CTx730; + +typedef struct ClassTx731 +{ + /* BYTE 0~1 */ + Uint16 EngineHeaterVoltage; + + /* BYTE 2~3 */ + Uint16 EngineHeaterCurrent; + + /* BYTE 4~5 */ + Uint16 GlowPlugVoltage; + + /* BYTE 6~7 */ + Uint16 GlowPlugCurrent; +} CTx731; + +typedef struct ClassTx732 +{ + /* BYTE 0~1 */ + Uint16 SolenoidVoltage; + + /* BYTE 2~3 */ + Uint16 SolenoidCurrent; + + /* BYTE 4~5 */ + Uint16 FuelPumpVoltage; + + /* BYTE 6~7 */ + Uint16 FuelPumpCurrent; +} CTx732; + +typedef struct ClassTx733 +{ + /* BYTE 0~1 */ + Uint16 CoolantPumpVoltage; + + /* BYTE 2~3 */ + Uint16 CoolantPumpCurrent; + + /* BYTE 4~5 */ + Uint16 Fan1Voltage; + + /* BYTE 6~7 */ + Uint16 Fan1Current; +} CTx733; + +typedef struct ClassTx734 +{ + /* BYTE 0~1 */ + Uint16 Fan2Voltage; + + /* BYTE 2~3 */ + Uint16 Fan2Current; + + /* BYTE 4~7 - Reserved */ + +} CTx734; + +typedef struct ClassTx740 +{ + /* BYTE 0~1 */ + Uint16 Voltage; + + /* BYTE 2~3 */ + Uint16 Current; + + /* BYTE 4~5 */ + Uint16 Rpm; + + /* BYTE 6~7 */ + Uint16 Power; +} CTx740; + +typedef struct ClassTx741 +{ + /* BYTE 0 */ + Uint16 PcbTemperature; + + /* BYTE 1 */ + Uint16 FetTemperature; + + /* BYTE 2 */ + Uint16 Winding1Temperature; + + /* BYTE 3 */ + Uint16 Winding2Temperature; + + /* BYTE 4~7 - Reserved */ + +} CTx741; + +typedef struct ClassTx750 +{ + /* BYTE 0~1 */ + Uint16 ActualRpm; + + /* BYTE 2~3 */ + Uint16 SetRpm; + + /* BYTE 4 */ + Uint16 ActualTorque; + + /* BYTE 5 */ + Uint16 SetTorque; + + /* BYTE 6~7 */ + Uint16 SystemVoltage; +} CTx750; + +typedef struct ClassTx751 +{ + /* BYTE 0 */ + Uint16 CoolantTemperature; + + /* BYTE 1 */ + Uint16 Fan1Speed; + + /* BYTE 2 */ + Uint16 Fan2Speed; + + /* BYTE 3 */ + Uint16 CoolantPumpSpeed; + + /* BYTE 4~5 */ + Uint16 Barometric; + + /* BYTE 6~7 - Reserved */ + +} CTx751; + +typedef struct ClassTx752 +{ + /* BYTE 0~1 */ + Uint16 OperationTimeL; + + /* BYTE 2~3 */ + Uint16 OperationTimeH; + + /* BYTE 4~7 - Reserved */ + +} CTx752; + +interrupt void CECanInterruptA(void); +interrupt void CECanInterruptB(void); +void CSendECanDataA(void); +void CSendECanDataB(void); +void CInitEcan(void); + +extern CCommCheck CommCheck; +extern CRx200 Rx200; +extern CRx210 Rx210; +extern CRx220 Rx220; +extern CRx221 Rx221; +extern CRx300 Rx300; +extern CRx301 Rx301; +extern CRx310 Rx310; +extern CRx320 Rx320; +extern CRx321 Rx321; +extern CRx322 Rx322; + +typedef struct ClassRx400 +{ + struct + { + Uint16 BYTE0 : 8; + Uint16 BYTE1 : 8; + Uint16 BYTE2 : 8; + Uint16 BYTE3 : 8; + Uint16 BYTE4 : 8; + Uint16 BYTE5 : 8; + Uint16 BYTE6 : 8; + Uint16 BYTE7 : 8; + } Bytes; + struct + { + Uint16 EngineHeater : 1; + Uint16 GlowPlug : 1; + Uint16 Solenoid : 1; + Uint16 FuelPump : 1; + Uint16 CoolantPump : 1; + Uint16 Fan1 : 1; + Uint16 Fan2 : 1; + Uint16 AuxTestStart : 1; + Uint16 rsvd_padding : 8; + } AuxControl; +} CRx400; + +extern CRx400 Rx400; + +#endif /* SOURCE_COMM_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 b/Source/.staticdata/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 new file mode 100644 index 0000000..e2725c6 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/b8ac7bc4f264e3761eb72b30b777ef06 @@ -0,0 +1,1436 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static CTx100 Tx100; +static CTx101 Tx101; +static CTx102 Tx102; // Command Data +static CTx103 Tx103; // Command Data +static CTx110 Tx110; +static CTx120 Tx120; +static CTx121 Tx121; +static CTx122 Tx122; +static CTx123 Tx123; +static CTx124 Tx124; + +static CTx700 Tx700; +static CTx701 Tx701; +static CTx710 Tx710; +static CTx720 Tx720; +static CTx730 Tx730; +static CTx731 Tx731; +static CTx732 Tx732; +static CTx733 Tx733; +static CTx734 Tx734; +static CTx740 Tx740; +static CTx741 Tx741; +static CTx750 Tx750; +static CTx751 Tx751; +static CTx752 Tx752; + +static CRx201 Rx201; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitECanA(void); +static void CInitECanB(void); +static void CECanASetMbox(void); +static void CECanBSetMbox(void); +static void CInitECanStructure(void); +static inline Uint16 CPackBit(Uint16 data, Uint16 pos); +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +CCommCheck CommCheck; + +// Rx - GCU +CRx200 Rx200; +CRx210 Rx210; +CRx220 Rx220; +CRx221 Rx221; + +// Rx - ECU +CRx300 Rx300; +CRx301 Rx301; +CRx310 Rx310; +CRx320 Rx320; +CRx321 Rx321; +CRx322 Rx322; + +#ifdef AUX_TEST +// Rx - For Aux Test +CRx400 Rx400; +#endif + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +interrupt void CECanInterruptA(void) +{ + struct ECAN_REGS ECanShadow; + ECanShadow.CANRMP.all = ECanaRegs.CANRMP.all; + + GeneralOperValue.Conection.CarComputer = 1U; // 한번이라도 통신이 수신되었다면 해당 장치가 연결되었다고 판단. + CommCheck.CarComputer = 0U; // 송신 시 타임아웃 카운트 클리어 + + ECanaRegs.CANRMP.all = ECanShadow.CANRMP.all; +} + +static inline Uint32 CPackMboxData(Uint16 b0, Uint16 b1, Uint16 b2, Uint16 b3) +{ + return (((Uint32)b0 << 24U) | ((Uint32)b1 << 16U) | ((Uint32)b2 << 8U) | (Uint32)b3); +} + +void CSendECanDataA(void) +{ + Uint16 uiTemp = 0U; + float32 fTemp = 0.0F; + + // --------------------------------------------------------- + // [700h - MBOX0] + // --------------------------------------------------------- + Tx700.HeartBit = (Tx700.HeartBit + 1U) % 65535U; + + // BYTE 0~1(HeartBit), BYTE 2(DCUversionMajor), BYTE 3(DCUversionMinor), BYTE 4(GCUversionMajor), BYTE 5(GCUversionMinor), BYTE 6(ECUversionMajor), BYTE 7(ECUversionMinor) + ECanaMboxes.MBOX0.MDL.all = CPackMboxData((Uint16)((Tx700.HeartBit >> 0U) & 0xFFU), (Uint16)((Tx700.HeartBit >> 8U) & 0xFFU), + (Uint16)FIRMWARE_VERSION_MAJOR, (Uint16)FIRMWARE_VERSION_MINOR); + ECanaMboxes.MBOX0.MDH.all = CPackMboxData(Rx200.VersionMajor, Rx200.VersionMinor, Rx300.VersionMajor, Rx300.VersionMinor); + + // --------------------------------------------------------- + // [701h - MBOX1] + // --------------------------------------------------------- + Tx701.DcuPlayState = (Uint16)(GeneralOperValue.uiApuState & 0x7U); + + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx701.DcuState = uiTemp; + + Tx701.GcuPlayState = Rx201.PlayState; + Tx701.GcuState = Rx201.State; + Tx701.EcuState = Rx301.State; + + // BYTE 0(DcuPlayState), BYTE 1(DcuState), BYTE 2(GcuPlayState), BYTE 3(GcuState), BYTE 4(EcuState), BYTE 5~7(Rsvd) + ECanaMboxes.MBOX1.MDL.all = CPackMboxData(Tx701.DcuPlayState, Tx701.DcuState, Tx701.GcuPlayState, Tx701.GcuState); + ECanaMboxes.MBOX1.MDH.all = CPackMboxData(Tx701.EcuState, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [710h - MBOX5] + // --------------------------------------------------------- + Tx710.GcuWarning = Rx210.GcuWarning; + Tx710.EcuWarning = Rx310.EcuWarning; + + // BYTE 0(GcuWarning), BYTE 1(EcuWarning), BYTE 2~7(Rsvd) + ECanaMboxes.MBOX5.MDL.all = CPackMboxData(Tx710.GcuWarning, Tx710.EcuWarning, 0U, 0U); + ECanaMboxes.MBOX5.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [720h - MBOX10] + // --------------------------------------------------------- + Tx720.DcuFault0 = (Uint16)((ulDcuTotalAlarm >> 0U) & 0xFFU); + Tx720.DcuFault1 = (Uint16)((ulDcuTotalAlarm >> 8U) & 0xFFU); + Tx720.DcuFault2 = (Uint16)((ulDcuTotalAlarm >> 16U) & 0xFFU); + Tx720.DcuFault3 = (Uint16)((ulDcuTotalAlarm >> 24U) & 0xFFU); + + Tx720.GcuFault0 = (Uint16)((Rx210.GcuFault >> 0U) & 0xFFU); + Tx720.GcuFault1 = (Uint16)((Rx210.GcuFault >> 8U) & 0xFFU); + Tx720.EcuFault = Rx310.EcuFault; + + // BYTE 0~3(DcuFault0~3), BYTE 4~5(GcuFault0~1), BYTE 6(Rsvd), BYTE 7(EcuFault) + ECanaMboxes.MBOX10.MDL.all = CPackMboxData(Tx720.DcuFault0, Tx720.DcuFault1, Tx720.DcuFault2, Tx720.DcuFault3); + ECanaMboxes.MBOX10.MDH.all = CPackMboxData(Tx720.GcuFault0, Tx720.GcuFault1, 0U, Tx720.EcuFault); + + // --------------------------------------------------------- + // [730h - MBOX15] + // --------------------------------------------------------- + Tx730.AuxState = (Uint16)GET_ALL_AUX_STATUS(); + + // BYTE 0(AuxState), BYTE 1~7(Rsvd) + ECanaMboxes.MBOX15.MDL.all = CPackMboxData(Tx730.AuxState, 0U, 0U, 0U); + ECanaMboxes.MBOX15.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [731h - MBOX16] + // --------------------------------------------------------- + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx731.EngineHeaterVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx731.EngineHeaterCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx731.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx731.GlowPlugCurrent = (Uint16)fTemp; + + // BYTE 0~1(EngineHeaterVoltage), BYTE 2~3(EngineHeaterCurrent), BYTE 4~5(GlowPlugVoltage), BYTE 6~7(GlowPlugCurrent) + ECanaMboxes.MBOX16.MDL.all = CPackMboxData((Uint16)((Tx731.EngineHeaterVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.EngineHeaterCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.EngineHeaterCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX16.MDH.all = CPackMboxData((Uint16)((Tx731.GlowPlugVoltage >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugVoltage >> 8U) & 0xFFU), + (Uint16)((Tx731.GlowPlugCurrent >> 0U) & 0xFFU), (Uint16)((Tx731.GlowPlugCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [732h - MBOX17] + // --------------------------------------------------------- + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx732.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx732.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx732.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx732.FuelPumpCurrent = (Uint16)fTemp; + + // BYTE 0~1(SolenoidVoltage), BYTE 2~3(SolenoidCurrent), BYTE 4~5(FuelPumpVoltage), BYTE 6~7(FuelPumpCurrent) + ECanaMboxes.MBOX17.MDL.all = CPackMboxData((Uint16)((Tx732.SolenoidVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.SolenoidCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.SolenoidCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX17.MDH.all = CPackMboxData((Uint16)((Tx732.FuelPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx732.FuelPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx732.FuelPumpCurrent >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [733h - MBOX18] + // --------------------------------------------------------- + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx733.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx733.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx733.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx733.Fan1Current = (Uint16)fTemp; + + // BYTE 0~1(CoolantPumpVoltage), BYTE 2~3(CoolantPumpCurrent), BYTE 4~5(Fan1Voltage), BYTE 6~7(Fan1Current) + ECanaMboxes.MBOX18.MDL.all = CPackMboxData((Uint16)((Tx733.CoolantPumpVoltage >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpVoltage >> 8U) & 0xFFU), + (Uint16)((Tx733.CoolantPumpCurrent >> 0U) & 0xFFU), (Uint16)((Tx733.CoolantPumpCurrent >> 8U) & 0xFFU)); + ECanaMboxes.MBOX18.MDH.all = CPackMboxData((Uint16)((Tx733.Fan1Voltage >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Voltage >> 8U) & 0xFFU), + (Uint16)((Tx733.Fan1Current >> 0U) & 0xFFU), (Uint16)((Tx733.Fan1Current >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [734h - MBOX19] + // --------------------------------------------------------- + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx734.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx734.Fan2Current = (Uint16)fTemp; + + // BYTE 0~1(Fan2Voltage), BYTE 2~3(Fan2Current), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX19.MDL.all = CPackMboxData((Uint16)((Tx734.Fan2Voltage >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Voltage >> 8U) & 0xFFU), + (Uint16)((Tx734.Fan2Current >> 0U) & 0xFFU), (Uint16)((Tx734.Fan2Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX19.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [740h - MBOX20] + // --------------------------------------------------------- + Tx740.Voltage = Rx220.DcVoltage; + Tx740.Current = Rx220.DcCurrent; + Tx740.Rpm = Rx220.Rpm; + Tx740.Power = Rx220.Power; + + // BYTE 0~1(Voltage), BYTE 2~3(Current), BYTE 4~5(Rpm), BYTE 6~7(Power) + ECanaMboxes.MBOX20.MDL.all = CPackMboxData((Uint16)((Tx740.Voltage >> 0U) & 0xFFU), (Uint16)((Tx740.Voltage >> 8U) & 0xFFU), + (Uint16)((Tx740.Current >> 0U) & 0xFFU), (Uint16)((Tx740.Current >> 8U) & 0xFFU)); + ECanaMboxes.MBOX20.MDH.all = CPackMboxData((Uint16)((Tx740.Rpm >> 0U) & 0xFFU), (Uint16)((Tx740.Rpm >> 8U) & 0xFFU), + (Uint16)((Tx740.Power >> 0U) & 0xFFU), (Uint16)((Tx740.Power >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [741h - MBOX21] + // --------------------------------------------------------- + Tx741.PcbTemperature = Rx221.PcbTemperature; + Tx741.FetTemperature = Rx221.FetTemperature; + Tx741.Winding1Temperature = Rx221.GenTemperature1; + Tx741.Winding2Temperature = Rx221.GenTemperature2; + + // BYTE 0(PcbTemperature), BYTE 1(FetTemperature), BYTE 2(Winding1Temperature), BYTE 3(Winding2Temperature), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX21.MDL.all = CPackMboxData(Tx741.PcbTemperature, Tx741.FetTemperature, Tx741.Winding1Temperature, Tx741.Winding2Temperature); + ECanaMboxes.MBOX21.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // [750h - MBOX25] + // --------------------------------------------------------- + Tx750.ActualRpm = Rx320.ActualRpm; + Tx750.SetRpm = Rx320.SetRpm; + Tx750.ActualTorque = Rx320.ActualTorque; + Tx750.SetTorque = Rx320.SetTorque; + Tx750.SystemVoltage = Rx320.SystemVoltage; + + // BYTE 0~1(ActualRpm), BYTE 2~3(SetRpm), BYTE 4(ActualTorque), BYTE 5(SetTorque), BYTE 6~7(SystemVoltage) + ECanaMboxes.MBOX25.MDL.all = CPackMboxData((Uint16)((Tx750.ActualRpm >> 0U) & 0xFFU), (Uint16)((Tx750.ActualRpm >> 8U) & 0xFFU), + (Uint16)((Tx750.SetRpm >> 0U) & 0xFFU), (Uint16)((Tx750.SetRpm >> 8U) & 0xFFU)); + ECanaMboxes.MBOX25.MDH.all = CPackMboxData(Tx750.ActualTorque, Tx750.SetTorque, + (Uint16)((Tx750.SystemVoltage >> 0U) & 0xFFU), (Uint16)((Tx750.SystemVoltage >> 8U) & 0xFFU)); + + // --------------------------------------------------------- + // [751h - MBOX26] + // --------------------------------------------------------- + Tx751.CoolantTemperature = Rx321.CoolantTemperature; + Tx751.Fan1Speed = Rx321.Fan1Speed; + Tx751.Fan2Speed = Rx321.Fan2Speed; + Tx751.CoolantPumpSpeed = Rx321.CoolantPumpSpeed; + Tx751.Barometric = Rx321.BarometricPressure; + + // BYTE 0(CoolantTemperature), BYTE 1(Fan1Speed), BYTE 2(Fan2Speed), BYTE 3(CoolantPumpSpeed), BYTE 4~5(Barometric), BYTE 6~7(Rsvd) + ECanaMboxes.MBOX26.MDL.all = CPackMboxData(Tx751.CoolantTemperature, Tx751.Fan1Speed, Tx751.Fan2Speed, Tx751.CoolantPumpSpeed); + ECanaMboxes.MBOX26.MDH.all = CPackMboxData((Uint16)((Tx751.Barometric >> 0U) & 0xFFU), (Uint16)((Tx751.Barometric >> 8U) & 0xFFU), 0U, 0U); + + // --------------------------------------------------------- + // [752h - MBOX27] + // --------------------------------------------------------- + Tx752.OperationTimeL = Rx322.TotalOperTimeL; + Tx752.OperationTimeH = Rx322.TotalOperTimeH; + + // BYTE 0~1(OperationTimeL), BYTE 2~3(OperationTimeH), BYTE 4~7(Rsvd) + ECanaMboxes.MBOX27.MDL.all = CPackMboxData((Uint16)((Tx752.OperationTimeL >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeL >> 8U) & 0xFFU), + (Uint16)((Tx752.OperationTimeH >> 0U) & 0xFFU), (Uint16)((Tx752.OperationTimeH >> 8U) & 0xFFU)); + ECanaMboxes.MBOX27.MDH.all = CPackMboxData(0U, 0U, 0U, 0U); + + // --------------------------------------------------------- + // 송신 메일박스 마스크 설정 및 전송 트리거 + // MBOX 마스크 (0, 1, 5, 10, 15, 16, 17, 18, 19, 20, 21, 25, 26, 27) + // --------------------------------------------------------- + Uint32 ulTxMask = 0x0E3F8423UL; + + ECanaRegs.CANTRS.all = ulTxMask; + ECanaRegs.CANTA.all = ulTxMask; +} + +static void CInitECanA(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanaShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0x00U; // Enable pull-up CANRXA + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0x00U; // Enable pull-up CANTXA + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 0x03U; // Asynch qual for CANRXA + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0x03U; // Configure CANRXA operation + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0x03U; // Configure CANTXA operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; + ECanaShadow.CANTIOC.bit.TXFUNC = 1U; + ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; + + ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; + ECanaShadow.CANRIOC.bit.RXFUNC = 1U; + ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.SCB = 1; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanaRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanaRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanaRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanaRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while(ECanaShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanaShadow.CANBTC.all = 0U; + + // 250 [Kbps] + ECanaShadow.CANBTC.bit.BRPREG = 19U; + ECanaShadow.CANBTC.bit.TSEG1REG = 10U; + ECanaShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanaShadow.CANBTC.bit.SAM = 1U; + ECanaShadow.CANBTC.bit.SJWREG = 2U; + ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; + + ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanaShadow.CANMC.bit.CCR = 0U; + ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; + + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + + do + { + ECanaShadow.CANES.all = ECanaRegs.CANES.all; + } while (ECanaShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanaRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanASetMbox(); +} + +static void CECanASetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanaMboxes.MBOX0.MSGID.bit.IDE = 0U; // ID ECANa 식별자 - 11bit ID 스탠다드 + ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 0x700U; + ECanaMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX0.MDH.all = 0x00000000U; + ECanaMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = 0x701U; + ECanaMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX1.MDH.all = 0x00000000U; + ECanaMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX5.MSGID.bit.STDMSGID = 0x710U; + ECanaMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX5.MDH.all = 0x00000000U; + ECanaMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX10.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX10.MSGID.bit.STDMSGID = 0x720U; + ECanaMboxes.MBOX10.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX10.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX10.MDH.all = 0x00000000U; + ECanaMboxes.MBOX10.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX15.MSGID.bit.STDMSGID = 0x730U; + ECanaMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX15.MDH.all = 0x00000000U; + ECanaMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x731U; + ECanaMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX16.MDH.all = 0x00000000U; + ECanaMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x732U; + ECanaMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX17.MDH.all = 0x00000000U; + ECanaMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x733U; + ECanaMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX18.MDH.all = 0x00000000U; + ECanaMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x734U; + ECanaMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX19.MDH.all = 0x00000000U; + ECanaMboxes.MBOX19.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX20.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x740U; + ECanaMboxes.MBOX20.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX20.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX20.MDH.all = 0x00000000U; + ECanaMboxes.MBOX20.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX21.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x741U; + ECanaMboxes.MBOX21.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX21.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX21.MDH.all = 0x00000000U; + ECanaMboxes.MBOX21.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750U; + ECanaMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX25.MDH.all = 0x00000000U; + ECanaMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX26.MSGID.bit.STDMSGID = 0x751U; + ECanaMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX26.MDH.all = 0x00000000U; + ECanaMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanaMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanaMboxes.MBOX27.MSGID.bit.STDMSGID = 0x752U; + ECanaMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanaMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanaMboxes.MBOX27.MDH.all = 0x00000000U; + ECanaMboxes.MBOX27.MDL.all = 0x00000000U; + + // Transe, Receive, 0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanaRegs.CANMD.all; + ECanShadow.CANMD.all = 0x0U; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanaRegs.CANME.all; + ECanShadow.CANME.all = 0xE3F8413UL; // USE MBOX0, MBOX1, MBOX5, MBOX10, MBOX15, MBOX16, MBOX17, MBOX18, MBOX19, MBOX20, MBOX21, MBOX25, MBOX26, MBOX27 + ECanaRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanaRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanaRegs.CANMC.all = ECanShadow.CANMC.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanaRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanaRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +interrupt void CECanInterruptB(void) +{ + Uint32 ECanRMPbit; + Uint32 uiMBOXMdl = 0UL; + Uint32 uiMBOXMdh = 0UL; + + ECanRMPbit = ECanbRegs.CANRMP.all; + + // --------------------------------------------------------- + // MBOX15 - 200h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 15U)) != 0U) + { + GeneralOperValue.Conection.Gcu = 1U; + CommCheck.Gcu = 0U; // GCU 타임아웃 카운트 초기화 + + uiMBOXMdl = ECanbMboxes.MBOX15.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX15.MDH.all; + + Uint16 uiByte0 = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiByte1 = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + + Rx200.HeartBit = uiByte0 | (uiByte1 << 8U); + + Rx200.VersionMajor = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); // Byte 5 + Rx200.VersionMinor = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); // Byte 6 + Rx200.VersionPatch = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); // Byte 7 + } + + // --------------------------------------------------------- + // MBOX16 - 201h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 16U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX16.MDL.all; + + Rx201.PlayState = (Uint16)((uiMBOXMdl >> 24U) & 0x7U); + Rx201.State = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + } + // --------------------------------------------------------- + // MBOX17 - 210h (비트 필드 매핑 반전) + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 17U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX17.MDL.all; + + Rx210.GcuWarning = (Uint16)(((uiMBOXMdl >> 24U) & 0xFFU) | (((uiMBOXMdl >> 16U) & 0xFFU) << 8U)); + Rx210.GcuFault = (Uint16)(((uiMBOXMdl >> 8U) & 0xFFU) | ((uiMBOXMdl & 0xFFU) << 8U)); + } + + // --------------------------------------------------------- + // MBOX18 - 220h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 18U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX18.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX18.MDH.all; + + // [Reverse] + // Byte 0(>>24), Byte 1(>>16) + Uint16 uiVoltL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiVoltH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx220.DcVoltage = uiVoltL | (uiVoltH << 8U); + + // Byte 2(>>8), Byte 3(>>0) + Uint16 uiCurrL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiCurrH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx220.DcCurrent = uiCurrL | (uiCurrH << 8U); + + // Byte 4(>>24), Byte 5(>>16) + Uint16 uiRpmL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiRpmH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx220.Rpm = uiRpmL | (uiRpmH << 8U); + + // Byte 6(>>24), Byte 7(>>16) + Uint16 uiPwrL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiPwrH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx220.Power = uiPwrL | (uiPwrH << 8U); + } + + // --------------------------------------------------------- + // MBOX19 - 221h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 19U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX19.MDL.all; + + // [Reverse] 0(24), 1(16), 2(8), 3(0) + Rx221.PcbTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx221.FetTemperature = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx221.GenTemperature1 = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx221.GenTemperature2 = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX25 - 300h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 25U)) != 0U) + { + GeneralOperValue.Conection.Ecu = 1U; + CommCheck.Ecu = 0U; // ECU 타임아웃 카운트 초기화 + uiMBOXMdl = ECanbMboxes.MBOX25.MDL.all; + + // [Reverse] + Rx300.VersionMajor = (Uint8)((uiMBOXMdl >> 24U) & 0xFFU); + Rx300.VersionMinor = (Uint8)((uiMBOXMdl >> 16U) & 0xFFU); + Rx300.VersionPatch = (Uint8)((uiMBOXMdl >> 8U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX26 - 301h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 26U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX26.MDL.all; + + // [Reverse] Byte 0 -> >> 24U + Rx301.State = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + } + + // --------------------------------------------------------- + // MBOX27 - 310h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 27U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX27.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx310.EcuWarning = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx310.EcuFault = (Uint16)((uiMBOXMdl >> 8U) & 0x3FU); + } + + // --------------------------------------------------------- + // MBOX28 - 320h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 28U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX28.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX28.MDH.all; + + // [Reverse] Byte 0(>>24), 1(>>16) + Uint16 uiActRpmL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiActRpmH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx320.ActualRpm = uiActRpmL | (uiActRpmH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) + Uint16 uiSetRpmL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiSetRpmH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx320.SetRpm = uiSetRpmL | (uiSetRpmH << 8U); + + // [Reverse] Byte 4(>>24), 5(>>16) (MDH) + Rx320.ActualTorque = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Rx320.SetTorque = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + + // [Reverse] Byte 6(>>8), 7(>>0) + Uint16 uiSysVoltL = (Uint16)((uiMBOXMdh >> 8U) & 0xFFU); + Uint16 uiSysVoltH = (Uint16)((uiMBOXMdh >> 0U) & 0xFFU); + Rx320.SystemVoltage = uiSysVoltL | (uiSysVoltH << 8U); + } + + // --------------------------------------------------------- + // MBOX29 - 321h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 29U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX29.MDL.all; + uiMBOXMdh = ECanbMboxes.MBOX29.MDH.all; + + // [Reverse] + Rx321.CoolantTemperature = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Rx321.Fan1Speed = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx321.Fan2Speed = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Rx321.CoolantPumpSpeed = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + + // Byte 4(>>24), 5(>>16) + Uint16 uiBarL = (Uint16)((uiMBOXMdh >> 24U) & 0xFFU); + Uint16 uiBarH = (Uint16)((uiMBOXMdh >> 16U) & 0xFFU); + Rx321.BarometricPressure = uiBarL | (uiBarH << 8U); + } + + // --------------------------------------------------------- + // MBOX30 - 322h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 30U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX30.MDL.all; + + // [Reverse] Byte 0(>>24), 1(>>16) -> TimeL + Uint16 uiTimeLL = (Uint16)((uiMBOXMdl >> 24U) & 0xFFU); + Uint16 uiTimeLH = (Uint16)((uiMBOXMdl >> 16U) & 0xFFU); + Rx322.TotalOperTimeL = uiTimeLL | (uiTimeLH << 8U); + + // [Reverse] Byte 2(>>8), 3(>>0) -> TimeH + Uint16 uiTimeHL = (Uint16)((uiMBOXMdl >> 8U) & 0xFFU); + Uint16 uiTimeHH = (Uint16)((uiMBOXMdl >> 0U) & 0xFFU); + Rx322.TotalOperTimeH = uiTimeHL | (uiTimeHH << 8U); + } + +#ifdef AUX_TEST + // --------------------------------------------------------- + // MBOX31 - 400h + // --------------------------------------------------------- + if ((ECanRMPbit & (1UL << 31U)) != 0U) + { + uiMBOXMdl = ECanbMboxes.MBOX31.MDL.all; + + // [Reverse] Byte 0 -> >> 24 + Rx400.AuxControl.EngineHeater = (Uint16)((uiMBOXMdl >> 24U) & 0x1U); + Rx400.AuxControl.GlowPlug = (Uint16)((uiMBOXMdl >> 25U) & 0x1U); + Rx400.AuxControl.Solenoid = (Uint16)((uiMBOXMdl >> 26U) & 0x1U); + Rx400.AuxControl.FuelPump = (Uint16)((uiMBOXMdl >> 27U) & 0x1U); + Rx400.AuxControl.CoolantPump = (Uint16)((uiMBOXMdl >> 28U) & 0x1U); + Rx400.AuxControl.Fan1 = (Uint16)((uiMBOXMdl >> 29U) & 0x1U); + Rx400.AuxControl.Fan2 = (Uint16)((uiMBOXMdl >> 30U) & 0x1U); + Rx400.AuxControl.AuxTestStart = (Uint16)((uiMBOXMdl >> 31U) & 0x1U); + } +#endif + + ECanbRegs.CANRMP.all = ECanRMPbit; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; +} + +void CSendECanDataB(void) +{ + struct ECAN_REGS ECanShadow; + static Uint16 uiTxDivid = 0U; // 분산 송신 + float32 fTemp = 0.0F; + Uint16 uiTemp = 0U; + + Uint16 EmergencySig = ((GeneralOperValue.uiEmergency > 0U) || (KeyOperValue.KeyList.Emergency > 0U)) ? 1U : 0U; + + // 10ms + // [101h] + // --- BYTE 0 --- + Tx101.PlayState = GeneralOperValue.uiApuState; + + // --- BYTE 1 --- + uiTemp = 0U; + uiTemp |= CPackBit(GeneralOperValue.uiFaultOccured, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiEmergency, 1U); + uiTemp |= CPackBit(KeyOperValue.KeyList.MainPower, 2U); + uiTemp |= CPackBit((GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U, 3U); + Tx101.DcuState = uiTemp; + + ECanbMboxes.MBOX1.MDL.byte.BYTE0 = Tx101.PlayState; + ECanbMboxes.MBOX1.MDL.byte.BYTE1 = Tx101.DcuState; + ECanbMboxes.MBOX1.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX1.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX1.MDH.byte.BYTE7 = 0x0U; + + // [102h] + // --- BYTE 0 --- + uiTemp = 0U; + uiTemp |= CPackField(GeneralOperValue.GcuCommand.PlayCmd, 0xFU, 0U); + uiTemp |= CPackBit(GeneralOperValue.uiAlarmReset, 4U); + uiTemp |= CPackBit(EmergencySig, 5U); + Tx102.GcuCommand = uiTemp; + + ECanbMboxes.MBOX2.MDL.byte.BYTE0 = Tx102.GcuCommand; + ECanbMboxes.MBOX2.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX2.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX2.MDH.byte.BYTE7 = 0x0U; + + // [103h] + // --- BYTE 0~7 --- + uiTemp = 0U; + Tx103.EngineStart = GeneralOperValue.EcuCommand.EngineStart; + Tx103.EngineStop = GeneralOperValue.EcuCommand.EngineStop; + Tx103.FaultReset = GeneralOperValue.uiAlarmReset; + Tx103.RpmSetpoint = GeneralOperValue.EcuCommand.RpmSetPoint; + Tx103.ActiveOverride = KeyOperValue.KeyList.BattleMode; + Tx103.EmergencyStop = EmergencySig; + + ECanbMboxes.MBOX3.MDL.byte.BYTE0 = Tx103.EngineStart; + ECanbMboxes.MBOX3.MDL.byte.BYTE1 = Tx103.EngineStop; + ECanbMboxes.MBOX3.MDL.byte.BYTE2 = Tx103.FaultReset; + ECanbMboxes.MBOX3.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX3.MDH.byte.BYTE4 = ((Tx103.RpmSetpoint >> 0U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE5 = ((Tx103.RpmSetpoint >> 8U) & 0xFFU); + ECanbMboxes.MBOX3.MDH.byte.BYTE6 = Tx103.ActiveOverride; + ECanbMboxes.MBOX3.MDH.byte.BYTE7 = Tx103.EmergencyStop; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTRS.bit.TRS1 = 1U; // 101h + ECanShadow.CANTRS.bit.TRS2 = 1U; // 102h + ECanShadow.CANTRS.bit.TRS3 = 1U; // 103h + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + ECanShadow.CANTA.bit.TA1 = 1U; // 101h + ECanShadow.CANTA.bit.TA2 = 1U; // 102h + ECanShadow.CANTA.bit.TA3 = 1U; // 103h + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + ECanShadow.CANTRS.all = ECanbRegs.CANTRS.all; + ECanShadow.CANTA.all = ECanbRegs.CANTA.all; + + switch (uiTxDivid) + { + case 0U: + { + // [100h] + Tx100.Heartbit = (Tx100.Heartbit + 1U) % 65535U; + Tx100.VersionMajor = (Uint16)FIRMWARE_VERSION_MAJOR; + Tx100.VersionMinor = (Uint16)FIRMWARE_VERSION_MINOR; + Tx100.VersionPatch = (Uint16)FIRMWARE_VERSION_PATCH; + + ECanbMboxes.MBOX0.MDL.byte.BYTE0 = ((Tx100.Heartbit >> 0U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE1 = ((Tx100.Heartbit >> 8U) & 0xFFU); + ECanbMboxes.MBOX0.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX0.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX0.MDH.byte.BYTE5 = Tx100.VersionMajor; + ECanbMboxes.MBOX0.MDH.byte.BYTE6 = Tx100.VersionMinor; + ECanbMboxes.MBOX0.MDH.byte.BYTE7 = Tx100.VersionPatch; + + ECanShadow.CANTRS.bit.TRS0 = 1U; + ECanShadow.CANTA.bit.TA0 = 1U; + break; + } + case 1U: + { + // [110h] + Tx110.DcuFaultB0 = ((Uint16)(ulDcuTotalAlarm >> 0U) & 0xFFU); // Apu Fault Byte 0 + Tx110.DcuFaultB1 = ((Uint16)(ulDcuTotalAlarm >> 8U) & 0xFFU); // Apu Fault Byte 1 + Tx110.DcuFaultB2 = ((Uint16)(ulDcuTotalAlarm >> 16U) & 0xFFU); // Apu Fault Byte 2 + Tx110.DcuFaultB3 = ((Uint16)(ulDcuTotalAlarm >> 24U) & 0xFFU); // Apu Fault Byte 3 + + ECanbMboxes.MBOX4.MDL.byte.BYTE0 = Tx110.DcuFaultB0; + ECanbMboxes.MBOX4.MDL.byte.BYTE1 = Tx110.DcuFaultB1; + ECanbMboxes.MBOX4.MDL.byte.BYTE2 = Tx110.DcuFaultB2; + ECanbMboxes.MBOX4.MDL.byte.BYTE3 = Tx110.DcuFaultB3; + ECanbMboxes.MBOX4.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX4.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS4 = 1U; + ECanShadow.CANTA.bit.TA4 = 1U; + break; + } + case 2U: + { + // [120h] + Tx120.AuxTotal = (Uint16)GET_ALL_AUX_STATUS(); + + ECanbMboxes.MBOX5.MDL.byte.BYTE0 = Tx120.AuxTotal; + ECanbMboxes.MBOX5.MDL.byte.BYTE1 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE2 = 0x0U; + ECanbMboxes.MBOX5.MDL.byte.BYTE3 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX5.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS5 = 1U; + ECanShadow.CANTA.bit.TA5 = 1U; + break; + } + case 3U: + { + // [121h] + fTemp = Adc_EngineHeater_V.fLpfValue * 10.0F; + Tx121.EngHeatVoltage = (Uint16)fTemp; + + fTemp = Adc_EngineHeater_I.fLpfValue * 10.0F; + Tx121.EngHeatCurrent = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_V.fLpfValue * 10.0F; + Tx121.GlowPlugVoltage = (Uint16)fTemp; + + fTemp = Adc_GlowPlug_I.fLpfValue * 10.0F; + Tx121.GlowPlugCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX6.MDL.byte.BYTE0 = ((Tx121.EngHeatVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE1 = ((Tx121.EngHeatVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE2 = ((Tx121.EngHeatCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDL.byte.BYTE3 = ((Tx121.EngHeatCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE4 = ((Tx121.GlowPlugVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE5 = ((Tx121.GlowPlugVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE6 = ((Tx121.GlowPlugCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX6.MDH.byte.BYTE7 = ((Tx121.GlowPlugCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS6 = 1U; + ECanShadow.CANTA.bit.TA6 = 1U; + break; + } + case 4U: + { + // [122h] + fTemp = Adc_Solenoid_V.fLpfValue * 10.0F; + Tx122.SolenoidVoltage = (Uint16)fTemp; + + fTemp = Adc_Solenoid_I.fLpfValue * 10.0F; + Tx122.SolenoidCurrent = (Uint16)fTemp; + + fTemp = Adc_FuelPump_V.fLpfValue * 10.0F; + Tx122.FuelPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_FuelPump_I.fLpfValue * 10.0F; + Tx122.FuelPumpCurrent = (Uint16)fTemp; + + ECanbMboxes.MBOX7.MDL.byte.BYTE0 = ((Tx122.SolenoidVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE1 = ((Tx122.SolenoidVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE2 = ((Tx122.SolenoidCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDL.byte.BYTE3 = ((Tx122.SolenoidCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE4 = ((Tx122.FuelPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE5 = ((Tx122.FuelPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE6 = ((Tx122.FuelPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX7.MDH.byte.BYTE7 = ((Tx122.FuelPumpCurrent >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS7 = 1U; + ECanShadow.CANTA.bit.TA7 = 1U; + break; + } + case 5U: + { + // [123h] + fTemp = Adc_CoolantPump_V.fLpfValue * 10.0F; + Tx123.CoolantPumpVoltage = (Uint16)fTemp; + + fTemp = Adc_CoolantPump_I.fLpfValue * 10.0F; + Tx123.CoolantPumpCurrent = (Uint16)fTemp; + + fTemp = Adc_Fan1_V.fLpfValue * 10.0F; + Tx123.Fan1Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan1_I.fLpfValue * 10.0F; + Tx123.Fan1Current = (Uint16)fTemp; + + ECanbMboxes.MBOX8.MDL.byte.BYTE0 = ((Tx123.CoolantPumpVoltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE1 = ((Tx123.CoolantPumpVoltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE2 = ((Tx123.CoolantPumpCurrent >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDL.byte.BYTE3 = ((Tx123.CoolantPumpCurrent >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE4 = ((Tx123.Fan1Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE5 = ((Tx123.Fan1Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE6 = ((Tx123.Fan1Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX8.MDH.byte.BYTE7 = ((Tx123.Fan1Current >> 8U) & 0xFFU); + + ECanShadow.CANTRS.bit.TRS8 = 1U; + ECanShadow.CANTA.bit.TA8 = 1U; + break; + } + default: + { + if (uiTxDivid == 6U) + { + // [124h] + fTemp = Adc_Fan2_V.fLpfValue * 10.0F; + Tx124.Fan2Voltage = (Uint16)fTemp; + + fTemp = Adc_Fan2_I.fLpfValue * 10.0F; + Tx124.Fan2Current = (Uint16)fTemp; + + ECanbMboxes.MBOX9.MDL.byte.BYTE0 = ((Tx124.Fan2Voltage >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE1 = ((Tx124.Fan2Voltage >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE2 = ((Tx124.Fan2Current >> 0U) & 0xFFU); + ECanbMboxes.MBOX9.MDL.byte.BYTE3 = ((Tx124.Fan2Current >> 8U) & 0xFFU); + ECanbMboxes.MBOX9.MDH.byte.BYTE4 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE5 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE6 = 0x0U; + ECanbMboxes.MBOX9.MDH.byte.BYTE7 = 0x0U; + + ECanShadow.CANTRS.bit.TRS9 = 1U; + ECanShadow.CANTA.bit.TA9 = 1U; + } + break; + } + } + ECanbRegs.CANTRS.all = ECanShadow.CANTRS.all; + ECanbRegs.CANTA.all = ECanShadow.CANTA.all; + + uiTxDivid = (uiTxDivid + 1U) % 10U; +} + +static void CInitECanB(void) +{ + /* Create a shadow register structure for the CAN control registers. This is + needed, since only 32-bit access is allowed to these registers. 16-bit access + to these registers could potentially corrupt the register contents or return + false data. This is especially true while writing to/reading from a bit + (or group of bits) among bits 16 - 31 */ + + struct ECAN_REGS ECanbShadow = {}; + + EALLOW; // EALLOW enables access to protected bits + + /* Enable internal pull-up for the selected CAN pins */ + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0x00U; // Enable pull-up CANTXB + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0x00U; // Enable pull-up CANRXB + + /* Set qualification for selected CAN pins to asynch only */ + // Inputs are synchronized to SYSCLKOUT by default. + // This will select asynch (no qualification) for the selected pins. + + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0x03U; // Asynch qual for CANRXB + + /* Configure eCAN-A pins using GPIO regs*/ + // This specifies which of the possible GPIO pins will be eCAN functional pins. + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0x03U; // Configure CANTXB operation + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0x03U; // Configure CANRXB operation + + /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ + + ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all; + ECanbShadow.CANTIOC.bit.TXFUNC = 1U; + ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all; + + ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all; + ECanbShadow.CANRIOC.bit.RXFUNC = 1U; + ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all; + + /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ + // HECC mode also enables time-stamping feature + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.SCB = 1; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again + // as a matter of precaution. + + ECanbRegs.CANTA.all = 0xFFFFFFFFU; /* Clear all TAn bits */ + ECanbRegs.CANRMP.all = 0xFFFFFFFFU; /* Clear all RMPn bits */ + ECanbRegs.CANGIF0.all = 0xFFFFFFFFU; /* Clear all interrupt flag bits */ + ECanbRegs.CANGIF1.all = 0xFFFFFFFFU; + + /* Configure bit timing parameters for eCANB*/ + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 1U; // Set CCR = 1 + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while(ECanbShadow.CANES.bit.CCE != 1U); // Wait for CCE bit to be set.. + + ECanbShadow.CANBTC.all = 0U; + + // 250 [kbps] + ECanbShadow.CANBTC.bit.BRPREG = 19U; + ECanbShadow.CANBTC.bit.TSEG1REG = 10U; + ECanbShadow.CANBTC.bit.TSEG2REG = 2U; + + ECanbShadow.CANBTC.bit.SAM = 1U; + ECanbShadow.CANBTC.bit.SJWREG = 2U; + ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all; + + ECanbShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanbShadow.CANMC.bit.CCR = 0U; + ECanbRegs.CANMC.all = ECanbShadow.CANMC.all; + + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + + do + { + ECanbShadow.CANES.all = ECanbRegs.CANES.all; + } while (ECanbShadow.CANES.bit.CCE != 0U); // Wait for CCE bit to be cleared.. + + /* Disable all Mailboxes */ + ECanbRegs.CANME.all = 0U; // Required before writing the MSGIDs + + EDIS; + CECanBSetMbox(); +} + +static void CECanBSetMbox(void) +{ + struct ECAN_REGS ECanShadow = {}; + + /* Tx Can MBox */ + ECanbMboxes.MBOX0.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX0.MSGID.bit.STDMSGID = 0x100U; + ECanbMboxes.MBOX0.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX0.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX0.MDH.all = 0x00000000U; + ECanbMboxes.MBOX0.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX1.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX1.MSGID.bit.STDMSGID = 0x101U; + ECanbMboxes.MBOX1.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX1.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX1.MDH.all = 0x00000000U; + ECanbMboxes.MBOX1.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX2.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX2.MSGID.bit.STDMSGID = 0x102U; + ECanbMboxes.MBOX2.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX2.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX2.MDH.all = 0x00000000U; + ECanbMboxes.MBOX2.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX3.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX3.MSGID.bit.STDMSGID = 0x103U; + ECanbMboxes.MBOX3.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX3.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX3.MDH.all = 0x00000000U; + ECanbMboxes.MBOX3.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX4.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX4.MSGID.bit.STDMSGID = 0x110U; + ECanbMboxes.MBOX4.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX4.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX4.MDH.all = 0x00000000U; + ECanbMboxes.MBOX4.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX5.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX5.MSGID.bit.STDMSGID = 0x120U; + ECanbMboxes.MBOX5.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX5.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX5.MDH.all = 0x00000000U; + ECanbMboxes.MBOX5.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX6.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX6.MSGID.bit.STDMSGID = 0x121U; + ECanbMboxes.MBOX6.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX6.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX6.MDH.all = 0x00000000U; + ECanbMboxes.MBOX6.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX7.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX7.MSGID.bit.STDMSGID = 0x122U; + ECanbMboxes.MBOX7.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX7.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX7.MDH.all = 0x00000000U; + ECanbMboxes.MBOX7.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX8.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX8.MSGID.bit.STDMSGID = 0x123U; + ECanbMboxes.MBOX8.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX8.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX8.MDH.all = 0x00000000U; + ECanbMboxes.MBOX8.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX9.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX9.MSGID.bit.STDMSGID = 0x124U; + ECanbMboxes.MBOX9.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX9.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX9.MDH.all = 0x00000000U; + ECanbMboxes.MBOX9.MDL.all = 0x00000000U; + + /* Rx Can MBox(GCU)*/ + ECanbMboxes.MBOX15.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX15.MSGID.bit.STDMSGID = 0x200U; + ECanbMboxes.MBOX15.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX15.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX15.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX15.MDH.all = 0x00000000U; + ECanbMboxes.MBOX15.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX16.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX16.MSGID.bit.STDMSGID = 0x201U; + ECanbMboxes.MBOX16.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX16.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX16.MDH.all = 0x00000000U; + ECanbMboxes.MBOX16.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX17.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX17.MSGID.bit.STDMSGID = 0x210U; + ECanbMboxes.MBOX17.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX17.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX17.MDH.all = 0x00000000U; + ECanbMboxes.MBOX17.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX18.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX18.MSGID.bit.STDMSGID = 0x220U; + ECanbMboxes.MBOX18.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX18.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX18.MDH.all = 0x00000000U; + ECanbMboxes.MBOX18.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX19.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x221U; + ECanbMboxes.MBOX19.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX19.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX19.MDH.all = 0x00000000U; + ECanbMboxes.MBOX19.MDL.all = 0x00000000U; + + /* Rx Can MBox(ECU)*/ + ECanbMboxes.MBOX25.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x300U; + ECanbMboxes.MBOX25.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX25.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX25.MDH.all = 0x00000000U; + ECanbMboxes.MBOX25.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX26.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x301U; + ECanbMboxes.MBOX26.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX26.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX26.MDH.all = 0x00000000U; + ECanbMboxes.MBOX26.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX27.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX27.MSGID.bit.STDMSGID = 0x310U; + ECanbMboxes.MBOX27.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX27.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX27.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX27.MDH.all = 0x00000000U; + ECanbMboxes.MBOX27.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX28.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX28.MSGID.bit.STDMSGID = 0x320U; + ECanbMboxes.MBOX28.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX28.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX28.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX28.MDH.all = 0x00000000U; + ECanbMboxes.MBOX28.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX29.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX29.MSGID.bit.STDMSGID = 0x321U; + ECanbMboxes.MBOX29.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX29.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX29.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX29.MDH.all = 0x00000000U; + ECanbMboxes.MBOX29.MDL.all = 0x00000000U; + + ECanbMboxes.MBOX30.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX30.MSGID.bit.STDMSGID = 0x322U; + ECanbMboxes.MBOX30.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX30.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX30.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX30.MDH.all = 0x00000000U; + ECanbMboxes.MBOX30.MDL.all = 0x00000000U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanbMboxes.MBOX31.MSGID.bit.IDE = 0U; + ECanbMboxes.MBOX31.MSGID.bit.STDMSGID = 0x400U; + ECanbMboxes.MBOX31.MSGID.bit.AME = 0U; + ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8U; + ECanbMboxes.MBOX31.MSGCTRL.bit.RTR = 0U; + ECanbMboxes.MBOX31.MDH.all = 0x00000000U; + ECanbMboxes.MBOX31.MDL.all = 0x00000000U; +#endif + + //0 is Transe, 1 is Receive + ECanShadow.CANMD.all = ECanbRegs.CANMD.all; + ECanShadow.CANMD.all = 0x7E0F8000UL; // USE MBOX15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMD.bit.MD31 = 1U; +#endif + ECanbRegs.CANMD.all = ECanShadow.CANMD.all; + + // MailBox Enable/Disable, 0 is Disable, 1 is Enable + ECanShadow.CANME.all = ECanbRegs.CANME.all; + ECanShadow.CANME.all = 0x7E0F83FFUL; // USE MBOX0~9, 15~19, 25~30 (31 제외) +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANME.bit.ME31 = 1U; +#endif + ECanbRegs.CANME.all = ECanShadow.CANME.all; + + EALLOW; + ECanShadow.CANMC.all = ECanbRegs.CANMC.all; + ECanShadow.CANMC.bit.STM = 0U; // '1' CAN Self-test Mode ¼³A¤ + ECanShadow.CANMC.bit.ABO = 1U; // '1' CAN Auto Bus On + ECanbRegs.CANMC.all = ECanShadow.CANMC.all; + + // Interrupt Enable(Receive Interrupt), 0 is Disable, 1 is Enable + ECanShadow.CANMIM.all = ECanbRegs.CANMIM.all; + ECanShadow.CANMIM.bit.MIM15 = 1U; + ECanShadow.CANMIM.bit.MIM16 = 1U; + ECanShadow.CANMIM.bit.MIM17 = 1U; + ECanShadow.CANMIM.bit.MIM18 = 1U; + ECanShadow.CANMIM.bit.MIM19 = 1U; + ECanShadow.CANMIM.bit.MIM25 = 1U; + ECanShadow.CANMIM.bit.MIM26 = 1U; + ECanShadow.CANMIM.bit.MIM27 = 1U; + ECanShadow.CANMIM.bit.MIM28 = 1U; + ECanShadow.CANMIM.bit.MIM29 = 1U; + ECanShadow.CANMIM.bit.MIM30 = 1U; +#ifdef AUX_TEST // ! Auxiliary Test + ECanShadow.CANMIM.bit.MIM31 = 1U; +#endif + ECanbRegs.CANMIM.all = ECanShadow.CANMIM.all; + + // Groble Interrupt + ECanShadow.CANGIM.all = ECanbRegs.CANGIM.all; + ECanShadow.CANGIM.bit.I0EN = 1U; // Line 0 Interrupt Enable + ECanShadow.CANGIM.bit.GIL = 0U; // All global interrupts are mapped to the ECAN0INT interrupt line. + ECanbRegs.CANGIM.all = ECanShadow.CANGIM.all; + EDIS; +} + +void CInitEcan(void) +{ + CInitECanA(); + CInitECanB(); + + CInitECanStructure(); +} + +static void CInitECanStructure(void) +{ + // Tx + (void)memset(&Tx100, 0, sizeof(CTx100)); + (void)memset(&Tx101, 0, sizeof(CTx101)); + (void)memset(&Tx102, 0, sizeof(CTx102)); + (void)memset(&Tx103, 0, sizeof(CTx103)); + (void)memset(&Tx110, 0, sizeof(CTx110)); + (void)memset(&Tx120, 0, sizeof(CTx120)); + (void)memset(&Tx121, 0, sizeof(CTx121)); + (void)memset(&Tx122, 0, sizeof(CTx122)); + (void)memset(&Tx123, 0, sizeof(CTx123)); + (void)memset(&Tx124, 0, sizeof(CTx124)); + + (void)memset(&Tx700, 0, sizeof(CTx700)); + (void)memset(&Tx701, 0, sizeof(CTx701)); + (void)memset(&Tx710, 0, sizeof(CTx710)); + (void)memset(&Tx720, 0, sizeof(CTx720)); + (void)memset(&Tx730, 0, sizeof(CTx730)); + (void)memset(&Tx731, 0, sizeof(CTx731)); + (void)memset(&Tx732, 0, sizeof(CTx732)); + (void)memset(&Tx733, 0, sizeof(CTx733)); + (void)memset(&Tx734, 0, sizeof(CTx734)); + (void)memset(&Tx740, 0, sizeof(CTx740)); + (void)memset(&Tx741, 0, sizeof(CTx741)); + (void)memset(&Tx750, 0, sizeof(CTx750)); + (void)memset(&Tx751, 0, sizeof(CTx751)); + (void)memset(&Tx752, 0, sizeof(CTx752)); + + // Rx - GCU + (void)memset(&Rx200, 0, sizeof(CRx200)); + (void)memset(&Rx201, 0, sizeof(CRx201)); + (void)memset(&Rx210, 0, sizeof(CRx210)); + (void)memset(&Rx220, 0, sizeof(CRx220)); + (void)memset(&Rx221, 0, sizeof(CRx221)); + + // Rx - ECU + (void)memset(&Rx300, 0, sizeof(CRx300)); + (void)memset(&Rx301, 0, sizeof(CRx301)); + (void)memset(&Rx310, 0, sizeof(CRx310)); + (void)memset(&Rx320, 0, sizeof(CRx320)); + (void)memset(&Rx321, 0, sizeof(CRx321)); + (void)memset(&Rx322, 0, sizeof(CRx322)); + +#ifdef AUX_TEST // ! Auxiliary Test + // Rx - Auxiliary Test + (void)memset(&Rx400, 0, sizeof(CRx400)); +#endif +} + +static inline Uint16 CPackBit(Uint16 data, Uint16 pos) +{ + Uint16 result = (data != 0U) ? 1U : 0U; + + return result << pos; +} + +static inline Uint16 CPackField(Uint16 data, Uint16 mask, Uint16 pos) +{ + return ((data & mask) << pos); +} diff --git a/Source/.staticdata/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 b/Source/.staticdata/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 new file mode 100644 index 0000000..72f3250 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/bb2b552577535324a3a6c8ae9a094408 @@ -0,0 +1,1979 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#pragma DATA_SECTION(CommandBus,"ZONE6_COM"); +#pragma DATA_SECTION(DataBus,"ZONE6_DAT"); + +#define ASCII_NULL ((int8)0) // NULL '\0' +#define ASCII_BLANK ((int8)32) // 공백 ' ' +#define ASCII_L_PAREN ((int8)40) // 여는 소괄호 '(' +#define ASCII_R_PAREN ((int8)41) // 닫는 소괄호 ')' +#define ASCII_MINUS ((int8)45) // 마이너스 '-' +#define ASCII_DOT ((int8)46) // 소수점 '.' + +#define ASCII_0 ((int8)48) // '0' + +#define ASCII_E ((int8)69) // 'E' +#define ASCII_R ((int8)82) // 'R' +#define ASCII_T ((int8)84) // 'T' +#define ASCII_Y ((int8)89) // 'Y' + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +static volatile Uint16 CommandBus, DataBus; + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CPageApu1(void); +static void CPageApu2(void); +static void CPageMenu1(void); +static void CPageMenu2(void); +static void CPageTemp(void); +static void CPageSensor1(void); +static void CPageSensor2(void); +static void CPageSensor3(void); +static void CPageSensor4(void); +static void CPageWarning1(void); +static void CPageWarning2(void); +static void CPageFault1(void); +static void CPageFault2(void); +static void CPageFault3(void); +static void CPageFault4(void); +static void CPageFault5(void); +static void CPageFault6(void); +static void CPageFault7(void); +static void CPageAlarmReset(void); +static void CPagePassword(void); +static void CPageMaintenance(void); +static void CPageVersion(void); +static void CPageKeyTest(void); +static void CPageShutdown(void); +static Uint16 CStrLen(const int8 *s); +static void CInitOledModule(void); +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type); +static void CInitProgress(void); +static void CDrawStr(Uint16 x, Uint16 y, const int8* str); +static void CTextAlign(int8 *buffer, const int8 *str); +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color); +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h); +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2); +static void CSetDrawRegion(Uint16 x, Uint16 y); +static void CSetPageAddress(Uint16 Address); +static void CSetColumnAddress(Uint16 x); +static void COledWrite(Uint16 Data, Uint16 Command); +static void CInitOledStructure(void); +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size); +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen); +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen); +static void CLineFocus(Uint16 isFocus); +static void CHourToString(int32 num, int8 *str); +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3); +static void CAddLineIndent(int8 *buffer, const int8 *str); +static const int8* CGetApuStateString(Uint16 idx); +static void CDrawTitleBox(Uint16 TitleLen); +static void CDrawCenteredLine(Uint16 y, const int8* text); +static void CCopyStr(int8 *pTarget, const int8 *pSource); +static void CAppendStr(int8 *pTarget, const int8 *pSource); +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str); +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2); +static void CDrawSimpleLine(Uint16 row, const int8* label); +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr); +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr); +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +COledOperValue OledOperValue; + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CDrawPageTitle(const int8* title, const int8* pageNumStr) +{ + Uint16 uiTitleLen = 0U; + + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], title); + CDrawStr(10U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + + if (title != NULL) + { + while ((title[uiTitleLen] != ASCII_NULL) && (uiTitleLen < (Uint16)TXT_MAX_LEN)) + { + uiTitleLen++; + } + } + CDrawTitleBox(uiTitleLen * 6U); + + if (pageNumStr != NULL) + { + CCopyStr(OledOperValue.cStrBuff[IDX_OLED_ROW_0], pageNumStr); + CDrawStr(100U, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + } +} + +static void CDrawPageLine(Uint16 row, const int8* label, const int8* valueStr, const int8* unitStr) +{ + Uint16 drawY; + Uint16 len = 0U; + + drawY = (row == (Uint16)IDX_OLED_ROW_1) ? (Uint16)IDX_OLED_LINE_1 : ((row == (Uint16)IDX_OLED_ROW_2) ? (Uint16)IDX_OLED_LINE_2 : ((row == (Uint16)IDX_OLED_ROW_3) ? (Uint16)IDX_OLED_LINE_3 : (Uint16)IDX_OLED_LINE_4)); + + CCopyStr(OledOperValue.cStrBuff[row], label); + + if (valueStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], valueStr); + } + + if (unitStr != NULL) + { + CAppendStr(OledOperValue.cStrBuff[row], unitStr); + } + + while ((OledOperValue.cStrBuff[row][len] != ASCII_NULL) && (len < (Uint16)(TXT_MAX_LEN - 1U))) + { + len++; + } + + while (len < (Uint16)(TXT_MAX_LEN - 1U)) + { + OledOperValue.cStrBuff[row][len] = ASCII_BLANK; // ' ' + len++; + } + + OledOperValue.cStrBuff[row][len] = ASCII_NULL; + + CDrawLineText(0U, drawY, (const int8*)OledOperValue.cStrBuff[row]); +} + +static void CDrawPageLineFloat(Uint16 row, const int8* label, float32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CFloatToString(value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawPageLineTwoFloat(Uint16 row, const int8* label, float32 value1, float32 value2) +{ + int8 finalBuf[32]; + Uint16 j = 0U; + Uint32 intPart; + Uint32 decPart; + Uint16 uiTmp; /* 복합 수식 연산 결과를 담을 임시 변수 */ + float32 fTmp; /* 부동소수점 연산 결과를 담을 임시 변수 */ + + /* --- Value 1 처리 --- */ + intPart = (Uint32)value1; + fTmp = ((value1 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + /* 구분자들 */ + finalBuf[j] = (int8)86; /* 'V' */ + j++; + finalBuf[j] = (int8)44; /* ',' */ + j++; + finalBuf[j] = ASCII_BLANK; /* ' ' */ + j++; + + + /* --- Value 2 처리 --- */ + intPart = (Uint32)value2; + fTmp = ((value2 - (float32)intPart) * 10.0F) + 0.5F; + decPart = (Uint32)fTmp; + + if (decPart >= 10U) + { + intPart++; + decPart = 0U; + } + + if (intPart > 99U) + { + intPart = 99U; + } + + /* 십의 자리 */ + uiTmp = (Uint16)((intPart / 10U) + 48U); + finalBuf[j] = (intPart >= 10U) ? (int8)uiTmp : ASCII_BLANK; + j++; + + /* 일의 자리 */ + uiTmp = (Uint16)((intPart % 10U) + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_DOT; /* '.' */ + j++; + + /* 소수점 첫째 자리 */ + uiTmp = (Uint16)(decPart + 48U); + finalBuf[j] = (int8)uiTmp; + j++; + + finalBuf[j] = ASCII_NULL; /* '\0' */ + + CDrawPageLine(row, label, finalBuf, (const int8*)"A"); +} + +static void CDrawPageLineInt(Uint16 row, const int8* label, int32 value, const int8* unitStr) +{ + int8 tempBuff[16]; + + CDecToString((int16)value, tempBuff, sizeof(tempBuff)); + CDrawPageLine(row, label, (const int8*)tempBuff, unitStr); +} + +static void CDrawTwoStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + const int8* statusStr1 = (status1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + const int8* statusStr2 = (status2 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 drawY = 0U; + + if (row == (Uint16)IDX_OLED_ROW_1) + { + drawY = (Uint16)IDX_OLED_LINE_1; + } + else if (row == (Uint16)IDX_OLED_ROW_2) + { + drawY = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + drawY = (Uint16)IDX_OLED_LINE_3; + } + else + { + drawY = (Uint16)IDX_OLED_LINE_4; + } + + // Label 1 + CStrncpy(OledOperValue.cStrBuff[row], label1, CStrLen(label1)); + + // Status 1 + CStrncat(OledOperValue.cStrBuff[row], statusStr1, CStrLen(statusStr1)); + + // Spacing + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 7U); + + // Label 2 + CStrncat(OledOperValue.cStrBuff[row], label2, CStrLen(label2)); + + // Status 2 + CStrncat(OledOperValue.cStrBuff[row], statusStr2, CStrLen(statusStr2)); + + CDrawLineText(0U, drawY, OledOperValue.cStrBuff[row]); +} + +static void CPageApu1(void) +{ + static Uint16 uiDummyRun = 1U; + + int16 iTemp; + const int8 *cTemp = (const int8*)""; + float32 fTemp; + + /* TITLE */ + CDrawStatusTitle((const int8*)"APU Status", (const int8*)"1/2"); + + /* LINE 1: DC Voltage */ + fTemp = (float32)Rx220.DcVoltage / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", fTemp, (const int8*)" V"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_1, (const int8*)"DC Voltage ", 0.0F, (const int8*)" V"); + } + + /* LINE 2: Power */ + fTemp = (float32)Rx220.Power / 10.0F; + + //if ((isfinite(fTemp) != 0) && (uiDummyRun == 0U)) + if (1) + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", fTemp, (const int8*)" kW"); + } + else + { + CDrawPageLineFloat(IDX_OLED_ROW_2, (const int8*)"Power ", 0.0F, (const int8*)" kW"); + } + + /* LINE 3: Speed */ + iTemp = (int16)Rx320.ActualRpm; + CDrawPageLineInt(IDX_OLED_ROW_3, (const int8*)"Speed ", (int32)iTemp, (const int8*)" rpm"); + + /* LINE 4: Status */ + cTemp = CGetApuStateString(GeneralOperValue.uiApuState); + + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_4], (const int8*)"Status", CStrLen((const int8*)"Status")); + CAddLineIndent(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp); + + if (cTemp != NULL) + { + CStrncat(OledOperValue.cStrBuff[IDX_OLED_ROW_4], cTemp, CStrLen(cTemp)); + } + + CDrawLineText(0U, (Uint16)IDX_OLED_LINE_4, OledOperValue.cStrBuff[IDX_OLED_ROW_4]); + + uiDummyRun = (uiDummyRun == 1U) ? 0U : uiDummyRun; +} + +static void CPageApu2(void) +{ + int8 tempBuff[16]; + int16 iTemp; + + // TITLE + CDrawStatusTitle("APU Status", "2/2"); + + // LINE 1 + iTemp = CGetEngCoolantTemperature(); + CDrawPageLineInt((Uint16)IDX_OLED_ROW_1, "Coolant ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)Rx320.ActualTorque; + CDrawPageLineInt((Uint16)IDX_OLED_ROW_2, "Torque ", (int32)iTemp, " %"); + + // LINE 3 + GeneralOperValue.ulTotalOperationHour = ((Uint32)Rx322.TotalOperTimeL) | ((Uint32)Rx322.TotalOperTimeH << 16U); + CHourToString((int32)GeneralOperValue.ulTotalOperationHour, tempBuff); + CDrawPageLine((Uint16)IDX_OLED_ROW_3, (const int8*)"ENG.Hour ", (const int8*)tempBuff, (const int8*)" Hr"); +} + +static void CPageMenu1(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"1/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"1. APU Status "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"2. Temperature "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"3. Sensor "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"4. Warning "); +} + +static void CPageMenu2(void) +{ + /* TITLE */ + CDrawStatusTitle((const int8*)"Menu", (const int8*)"2/2"); + + /* LINE 1 */ + CLineFocus((OledOperValue.uiFocusLine == 0U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_1, (const int8*)"5. Fault "); + + /* LINE 2 */ + CLineFocus((OledOperValue.uiFocusLine == 1U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_2, (const int8*)"6. Alarm Reset "); + + /* LINE 3 */ + CLineFocus((OledOperValue.uiFocusLine == 2U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_3, (const int8*)"7. Maintenance "); + + /* LINE 4 */ + CLineFocus((OledOperValue.uiFocusLine == 3U) ? 1U : 0U); + CDrawSimpleLine((Uint16)IDX_OLED_ROW_4, (const int8*)"8. Version "); +} + +static void CPageTemp(void) +{ + int16 iTemp; + + // TITLE + CDrawStatusTitle("Temperature", "1/1"); + + // LINE 1 + iTemp = (int16)((int16)Rx221.PcbTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_1, "PCB Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 2 + iTemp = (int16)((int16)Rx221.FetTemperature - 40); + CDrawPageLineInt(IDX_OLED_ROW_2, "FET Temp. ", (int32)iTemp, " \xA1\xC9"); + + // LINE 3 + iTemp = (int16)((int16)Rx221.GenTemperature1 - 40); + CDrawPageLineInt(IDX_OLED_ROW_3, "Gen.Temp1. ", (int32)iTemp, " \xA1\xC9"); + + // LINE4 + iTemp = (int16)((int16)Rx221.GenTemperature2 - 40); + CDrawPageLineInt(IDX_OLED_ROW_4, "Gen.Temp2. ", (int32)iTemp, " \xA1\xC9"); +} +static void CPageSensor1(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "1/4"); + + // LINE 1 + fTemp1 = (Adc_EngineHeater_V.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_V.fLpfValue; + fTemp2 = (Adc_EngineHeater_I.fLpfValue < 0.0F) ? 0.0F : Adc_EngineHeater_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "EngHeat ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_GlowPlug_V.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_V.fLpfValue; + fTemp2 = (Adc_GlowPlug_I.fLpfValue < 0.0F) ? 0.0F : Adc_GlowPlug_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "GlowPlg ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Solenoid_V.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_V.fLpfValue; + fTemp2 = (Adc_Solenoid_I.fLpfValue < 0.0F) ? 0.0F : Adc_Solenoid_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Solnoid ", fTemp1, fTemp2); + + // LINE 4 + fTemp1 = (Adc_FuelPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_V.fLpfValue; + fTemp2 = (Adc_FuelPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_FuelPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_4, "FuelPmp ", fTemp1, fTemp2); +} + +static void CPageSensor2(void) +{ + float32 fTemp1, fTemp2; + + // TITLE + CDrawSensorTitle("APU Sensor", "2/4"); + + // LINE 1 + fTemp1 = (Adc_CoolantPump_V.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_V.fLpfValue; + fTemp2 = (Adc_CoolantPump_I.fLpfValue < 0.0F) ? 0.0F : Adc_CoolantPump_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_1, "CoolPmp ", fTemp1, fTemp2); + + // LINE 2 + fTemp1 = (Adc_Fan1_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_V.fLpfValue; + fTemp2 = (Adc_Fan1_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan1_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_2, "Fan1 ", fTemp1, fTemp2); + + // LINE 3 + fTemp1 = (Adc_Fan2_V.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_V.fLpfValue; + fTemp2 = (Adc_Fan2_I.fLpfValue < 0.0F) ? 0.0F : Adc_Fan2_I.fLpfValue; + CDrawPageLineTwoFloat(IDX_OLED_ROW_3, "Fan2 ", fTemp1, fTemp2); +} + +static void CPageSensor3(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("ECU Sensor", "3/4"); + + // LINE 1 + iTemp = (int16)Rx321.BarometricPressure; + CDrawPageLineInt(IDX_OLED_ROW_1, "Barometric ", (int32)iTemp, " mb"); + + // LINE 2 + iTemp = (int16)Rx321.Fan1Speed; + CDrawPageLineInt(IDX_OLED_ROW_2, "Fan1 Speed ", (int32)iTemp, " %"); + + // LINE 3 + iTemp = (int16)Rx321.Fan2Speed; + CDrawPageLineInt(IDX_OLED_ROW_3, "Fan2 Speed ", (int32)iTemp, " %"); + + // LINE 4 + iTemp = (int16)Rx321.CoolantPumpSpeed; + CDrawPageLineInt(IDX_OLED_ROW_4, "C.Pump Speed ", (int32)iTemp, " %"); +} + +static void CPageSensor4(void) +{ + int16 iTemp; + + // TITLE + CDrawSensorTitle("GCU Sensor", "4/4"); + + // LINE 1 + iTemp = (int16)Rx220.Rpm; + CDrawPageLineInt(IDX_OLED_ROW_1, "GEN.RPM ", (int32)iTemp, " rpm"); +} +static void CDrawPageLineStatus(Uint16 row, const int8* label, Uint16 status) +{ + const int8* statusStr = (status == 1U) ? (const int8*)"1" : (const int8*)"0"; + CDrawPageLine(row, label, statusStr, NULL); +} + +static void CPageWarning1(void) +{ + // TITLE + CDrawPageTitle("Warning", "1/2"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "PCBOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_PCB_OT), "FETOT:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_FET_OT)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "GEOT1:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING1_OH), "GEOT2:", CIsBitSet((Uint32)Rx210.GcuWarning, (Uint16)IDX_WARNING_GCU_WINDING2_OH)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "ENGOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_OH), "LOILP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_LO_OIL_PRESS)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "INTOT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_OH), "INTLP:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_INTAKE_LO_PRESS)); +} + +static void CPageWarning2(void) +{ + /* TITLE */ + CDrawPageTitle("Warning", "2/2"); + + /* LINE 1 */ + CDrawTwoStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"ENGLT:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_LO_TEMP), (const int8*)"ENGSF:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_ENGINE_SENSOR)); + + /* LINE 2 */ + CDrawPageLineStatus((Uint16)IDX_OLED_ROW_2, (const int8*)"DEFAC:", CIsBitSet((Uint32)Rx310.EcuWarning, (Uint16)IDX_WARNING_ECU_DEFAULT_ACTIVE)); +} + +static void CPageFault1(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "1/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CARCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CAR_COMM), "GCUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GCU_COMM)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "ECUCT:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ECU_COMM), "RPMER:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_RPM_ERR)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OC), "GPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OC)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "SOLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OC), "FPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OC)); +} + +static void CPageFault2(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "2/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "CPLOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OC), "F1LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OC)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "F2LOC:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OC), "EHVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "EHVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_ENGINE_HEAT_OV), "GPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "GPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_GLOW_PLUG_OV), "SLVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_UV)); +} + +static void CPageFault3(void) +{ + // TITLE + CDrawFaultTitle("APU Fault", "3/7"); + + // LINE 1 + CDrawTwoStatusLine(IDX_OLED_ROW_1, "SLVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_SOLENOID_OV), "FPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_UV)); + + // LINE 2 + CDrawTwoStatusLine(IDX_OLED_ROW_2, "FPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FUEL_PUMP_OV), "CPVUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_UV)); + + // LINE 3 + CDrawTwoStatusLine(IDX_OLED_ROW_3, "CPVOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_COOLANT_PUMP_OV), "F1VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_UV)); + + // LINE 4 + CDrawTwoStatusLine(IDX_OLED_ROW_4, "F1VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN1_OV), "F2VUV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_UV)); +} + +static void CPageFault4(void) +{ + /* TITLE */ + CDrawFaultTitle((const int8*)"APU Fault", (const int8*)"4/7"); + + /* LINE 1: */ + CDrawFaultStatusLine((Uint16)IDX_OLED_ROW_1, (const int8*)"F2VOV:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_FAN2_OV), (const int8*)"CRKFL:", CIsBitSet(ulDcuTotalAlarm, (Uint16)IDX_FAULT_DCU_CRANKING_FAIL)); +} + +static void CPageFault5(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "5/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "HTRIP:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWTRIP), "HIGBT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HWIGBT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "HDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_HW_DC), "GNOCU:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCU)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GNOCV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW), "GNOCW:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OCW)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "SDCOV:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OV), "SDCOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_DC_OC)); +} + +static void CPageFault6(void) +{ + // TITLE + CDrawFaultTitle("GCU Fault", "6/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "SMOOC:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_CRANK_OC), "PCBOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_PCB_OT)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "FETOT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_FET_OT), "GW1OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING1_OH)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "GW2OT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_WINDING2_OH), "GENOS:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_GEN_OS)); + + // LINE 4 + CDrawFaultStatusLine(IDX_OLED_ROW_4, "RSICF:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_IC), "RSPRT:", CIsBitSet(ulGcuTotalAlarm, (Uint16)IDX_FAULT_GCU_RES_PRTY)); +} + +static void CPageFault7(void) +{ + // TITLE + CDrawFaultTitle("ECU Fault", "7/7"); + + // LINE 1 + CDrawFaultStatusLine(IDX_OLED_ROW_1, "OILMS:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_OIL_MS), "INTOT:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_INT_OH)); + + // LINE 2 + CDrawFaultStatusLine(IDX_OLED_ROW_2, "ENGOH:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_OH), "ACTUA:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ACTUATOR)); + + // LINE 3 + CDrawFaultStatusLine(IDX_OLED_ROW_3, "RPMSG:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_RPM_SIG), "ENGSF:", CIsBitSet(ulEcuTotalAlarm, (Uint16)IDX_FAULT_ECU_ENG_SF)); +} + +static void CDrawAlarmBox(void) +{ + CDrawLine(5U, 10U, 122U, 10U); // Top + CDrawLine(5U, 10U, 5U, 58U); // Left + CDrawLine(5U, 59U, 122U, 59U); // Bottom + CDrawLine(122U, 10U, 122U, 58U); // Right +} + +static void CDrawPostStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + Uint16 y = 0U; + const int8* pPrintStr = NULL; // 실제 출력할 문자열을 가리킬 포인터 + + OledOperValue.cStrBuff[row][0] = ASCII_NULL; // '\0' + + // Label 1 + Status 1 + if (l1 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], (s1 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 2 + Status 2 + if (l2 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + if (OledOperValue.cStrBuff[row][0] != ASCII_NULL) // '\0' + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + } + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 0U) ? (const int8*)"P" : (const int8*)"F", 1U); + } + + if (row == (Uint16)IDX_OLED_ROW_4) + { + pPrintStr = OledOperValue.cStrBuff[row]; + } + else + { + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[row]); + pPrintStr = OledOperValue.cAlignBuffer; + } + + // Y 좌표 설정 + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + if (pPrintStr != NULL) + { + CDrawLineText(0U, y, (const int8*)pPrintStr); + } +} + +static void CPageAlarmReset(void) +{ + const int8 *cTemp = ""; + + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "Reset all faults?"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "(no clear warnings)"); + + // LINE 3 + cTemp = (OledOperValue.uiResetAlarmAnswer == 1U) ? (int8*)"YES" : (int8*)" NO"; + CDrawCenteredLine((Uint16)IDX_OLED_LINE_3 + 5U, cTemp); + + // BOX + CDrawAlarmBox(); +} + +static void CPagePassword(void) +{ + const int8 *cTemp = ""; + int8 maskBuffer[16]; + Uint16 uiTemp[2] = { 0, '\0' }; + + // TITLE + CDrawStatusTitle("Input Password", NULL); + + switch (OledOperValue.uiFocusDigit) + { + case (Uint16)IDX_OLED_PASS_DIGIT_1: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_1] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[", 2); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*][*]", 10); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_2: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_2] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][", 4); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*][*]", 7); + break; + } + case (Uint16)IDX_OLED_PASS_DIGIT_3: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_3] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][", 7); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "][*]", 4); + break; + } + default: + { + uiTemp[0] = GeneralOperValue.uiPassword[IDX_OLED_PASS_DIGIT_4] + 48U; // 48 : '0' + cTemp = (int8*)uiTemp; + CStrncpy(maskBuffer, "[*][*][*][", 10); + CStrncat(maskBuffer, cTemp, 1); + CStrncat(maskBuffer, "]", 1); + break; + } + } + + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, (const int8*)maskBuffer); +} +static void CPageMaintenance(void) +{ + const int8 *cTemp = ""; + + // TITLE + CDrawStatusTitle("Maintenance", "1/1"); + + // LINE 1 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_1) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.ManualCranking > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_1, "Manual Cranking ", cTemp, NULL); + + // LINE 2 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_2) ? 1U : 0U); + cTemp = (GeneralOperValue.Maintenance.LampTest > 0U) ? (int8*)"ON " : (int8*)"OFF"; + CDrawPageLine(IDX_OLED_ROW_2, "Lamp Test ", cTemp, NULL); + + // LINE 3 + CLineFocus((OledOperValue.uiFocusLine == (Uint16)IDX_OLED_LINE_FOCUS_3) ? 1U : 0U); + CDrawPageLine(IDX_OLED_ROW_3, "Switch Test ", NULL, NULL); +} + +static void CPageVersion(void) +{ + int8 cTemp[16]; + + // TITLE + CDrawStatusTitle("Version", "1/1"); + + // LINE 1 is blank + + // LINE 2 + CMakeVersionString(cTemp, (int16)FIRMWARE_VERSION_MAJOR, (int16)FIRMWARE_VERSION_MINOR, (int16)FIRMWARE_VERSION_PATCH); + CDrawPageLine(IDX_OLED_ROW_2, " DCU : ", cTemp, NULL); + + // LINE 3 + CMakeVersionString(cTemp, (int16)Rx200.VersionMajor, (int16)Rx200.VersionMinor, (int16)Rx200.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_3, " GCU : ", cTemp, NULL); + + // LINE 4 + CMakeVersionString(cTemp, (int16)Rx300.VersionMajor, (int16)Rx300.VersionMinor, (int16)Rx300.VersionPatch); + CDrawPageLine(IDX_OLED_ROW_4, " ECU : ", cTemp, NULL); +} + +static void CDrawCenteredLine(Uint16 y, const int8* text) +{ + CStrncpy(OledOperValue.cStrBuff[IDX_OLED_ROW_0], text, CStrLen(text)); + CTextAlign(OledOperValue.cAlignBuffer, OledOperValue.cStrBuff[IDX_OLED_ROW_0]); + CDrawStr(0U, y, OledOperValue.cAlignBuffer); +} + +static void CDrawKeyTestBox(void) +{ + CDrawLine(0U, 0U, 125U, 0U); // Top + CDrawLine(0U, 0U, 0U, 22U); // Left + CDrawLine(0U, 23U, 2U, 25U); // Left diag + CDrawLine(3U, 25U, 123U, 25U); // Bottom + CDrawLine(124U, 25U, 126U, 23U); // Right diag + CDrawLine(126U, 0U, 126U, 22U); // Right +} + +static void CDrawKeyStatusLine(Uint16 row, const int8* l1, Uint16 s1, const int8* l2, Uint16 s2, const int8* l3, Uint16 s3) +{ + const int8* s1Str = (s1 == 1U) ? (const int8*)"1" : (const int8*)"0"; + Uint16 y = 0U; + + // Label 1 + Status 1 + CStrncpy(OledOperValue.cStrBuff[row], l1, CStrLen(l1)); + CStrncat(OledOperValue.cStrBuff[row], s1Str, 1U); + + // Label 2 + Status 2 + if (l2 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l2, CStrLen(l2)); + CStrncat(OledOperValue.cStrBuff[row], (s2 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Label 3 + Status 3 + if (l3 != NULL) + { + CStrncat(OledOperValue.cStrBuff[row], (const int8*)" ", 1U); + CStrncat(OledOperValue.cStrBuff[row], l3, CStrLen(l3)); + CStrncat(OledOperValue.cStrBuff[row], (s3 == 1U) ? (const int8*)"1" : (const int8*)"0", 1U); + } + + // Determine Y based on row + if (row == (Uint16)IDX_OLED_ROW_2) + { + y = (Uint16)IDX_OLED_LINE_2; + } + else if (row == (Uint16)IDX_OLED_ROW_3) + { + y = (Uint16)IDX_OLED_LINE_3; + } + else + { + if (row == (Uint16)IDX_OLED_ROW_4) + { + y = (Uint16)IDX_OLED_LINE_4; + } + } + + CDrawLineText(0U, y, OledOperValue.cStrBuff[row]); +} + +static void CPageKeyTest(void) +{ + // TITLE1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_TITLE + 2U, "Button input Test"); + + // TITLE2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1 - 1U, "(Back to Up&Down)"); + + // BOX + CDrawKeyTestBox(); + + // LINE 2 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_2, " Stat:", ((GPIO_KEY_START() | GPIO_KEY_REMOTE_START() | GPIO_KEY_REMOTE_STOP()) == 0U) ? 1U : 0U, NULL, 0, NULL, 0); + + // LINE 3 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_3, " Up:", (GPIO_KEY_UP() == 0U) ? 1U : 0U, "Entr:", (GPIO_KEY_ENTER() == 0U) ? 1U : 0U, "Powr:", (GPIO_KEY_POWER() == 0U) ? 1U : 0U); + + // LINE 4 + CDrawKeyStatusLine((Uint16)IDX_OLED_ROW_4, "Down:", (GPIO_KEY_DOWN() == 0U) ? 1U : 0U, "Menu:", (GPIO_KEY_MENU() == 0U) ? 1U : 0U, "Emgc:", ((GPIO_KEY_EMERGENCY() | GPIO_KEY_REMOTE_EMERGENCY()) == 0U) ? 1U : 0U); +} + +static void CPageShutdown(void) +{ + // LINE 1 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_1, "System"); + + // LINE 2 + CDrawCenteredLine((Uint16)IDX_OLED_LINE_2, "Shutting down..."); +} + +void CSetPage(Uint16 PageNum) +{ + static const CPageHandler PageTable[IDX_OLED_PAGE_MAX] = + { + { IDX_OLED_PAGE_APU1, &CPageApu1 }, + { IDX_OLED_PAGE_APU2, &CPageApu2 }, + { IDX_OLED_PAGE_MENU1, &CPageMenu1 }, + { IDX_OLED_PAGE_MENU2, &CPageMenu2 }, + { IDX_OLED_PAGE_TEMP, &CPageTemp }, + { IDX_OLED_PAGE_SENSOR1, &CPageSensor1 }, + { IDX_OLED_PAGE_SENSOR2, &CPageSensor2 }, + { IDX_OLED_PAGE_SENSOR3, &CPageSensor3 }, + { IDX_OLED_PAGE_SENSOR4, &CPageSensor4 }, + { IDX_OLED_PAGE_WARNING1, &CPageWarning1 }, + { IDX_OLED_PAGE_WARNING2, &CPageWarning2 }, + { IDX_OLED_PAGE_FAULT1, &CPageFault1 }, + { IDX_OLED_PAGE_FAULT2, &CPageFault2 }, + { IDX_OLED_PAGE_FAULT3, &CPageFault3 }, + { IDX_OLED_PAGE_FAULT4, &CPageFault4 }, + { IDX_OLED_PAGE_FAULT5, &CPageFault5 }, + { IDX_OLED_PAGE_FAULT6, &CPageFault6 }, + { IDX_OLED_PAGE_FAULT7, &CPageFault7 }, + { IDX_OLED_PAGE_RESET_ALARM, &CPageAlarmReset }, + { IDX_OLED_PAGE_PASSWORD, &CPagePassword }, + { IDX_OLED_PAGE_MAINTENANCE, &CPageMaintenance }, + { IDX_OLED_PAGE_VERSION, &CPageVersion }, + { IDX_OLED_PAGE_KEY_TEST, &CPageKeyTest }, + { IDX_OLED_PAGE_SHUTDOWN, &CPageShutdown } + }; + + Uint16 i; + + if (OledOperValue.uiOldPageNum != PageNum) + { + COledBufferReset(); + OledOperValue.uiOldPageNum = PageNum; + } + + for (i = 0U; i < (Uint16)IDX_OLED_PAGE_MAX; i++) + { + if (OledOperValue.uiPageNum == i) + { + CLineFocus(0U); + PageTable[i].pAction(); // CPageHandler 참조 + } + } +} + +void COledBufferReset(void) +{ + (void)memset(OledOperValue.uiBuff, 0, sizeof(int8) * OLED_WIDTH * OLED_PAGE); + (void)memset(OledOperValue.cStrBuff, 0, sizeof(int8) * TXT_LINE_LEN * TXT_MAX_LEN); +} + +static void CDrawTitleBox(Uint16 TitleLen) +{ + CDrawLine(8U, 0U, 8U, 9U); // 왼쪽 + CDrawLine(8U, 10U, 10U, 12U); // 왼쪽 모서리 + CDrawLine(11U, 12U, (TitleLen + 9U), 12U); // 아래쪽 + CDrawLine((TitleLen + 10U), 12U, (TitleLen + 12U), 10U); // 오른쪽 모서리 + CDrawLine((TitleLen + 12U), 0U, (TitleLen + 12U), 9U); // 오른쪽 + + if (OledOperValue.uiPageNum != (Uint16)IDX_OLED_PAGE_PASSWORD) + { + // 서브 타이틀 박스 + CDrawLine(98U, 0U, 98U, 9U); // 왼쪽 + CDrawLine(98U, 10U, 100U, 12U); // 왼쪽 모서리 + CDrawLine(101U, 12U, 118U, 12U); // 아래쪽 + CDrawLine(119U, 12U, 121U, 10U); // 오른쪽 모서리 + CDrawLine(121U, 0U, 121U, 9U); // 오른쪽 + } +} + +void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height) +{ + Uint16 i, j; + + for (j = (y / 8U); j < ((y + height) / 8U); j++) + { + for (i = x; i < (x + width); i++) + { + CSetPageAddress(j); + CSetColumnAddress(i); + COledWrite(OledOperValue.uiBuff[i][j], MODE_DATA); + } + } +} + +void CInitOled(void) +{ + Uint16 uiPageNum; + Uint16 i; + + CInitOledModule(); + + for(uiPageNum = 0U; uiPageNum < 8U; uiPageNum++) + { + COledWrite((Uint16)(0xB0U | uiPageNum), (Uint16)MODE_COMMAND); + + for(i = 0U; i < (Uint16)OLED_WIDTH; i++) + { + COledWrite((Uint16)0x00, (Uint16)MODE_DATA); + } + } + + CInitProgress(); +} + +static void CInitProgress(void) +{ + OledOperValue.Color.TxtColor = 1U; + + CTextAlign(OledOperValue.cAlignBuffer, "K2 APU"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_TITLE, OledOperValue.cAlignBuffer); + + CDrawBox(OLED_LOAD_PROGRESS_X, OLED_LOAD_PROGRESS_Y, OLED_LOAD_PROGRESS_W, OLED_LOAD_PROGRESS_H); + + (void)memset(OledOperValue.cAlignBuffer, 0, sizeof(char) * TXT_MAX_LEN); + + CTextAlign(OledOperValue.cAlignBuffer, "Initializing System"); + CDrawStr(0, (Uint16)IDX_OLED_LINE_2, OledOperValue.cAlignBuffer); +} + +static void CAddLineIndent(int8 *buffer, const int8 *str) +{ + Uint16 i; + Uint16 uiSpaceNeeded = ((Uint16)TXT_MAX_LEN - 1U) - CStrLen(buffer) - CStrLen(str); + + if (uiSpaceNeeded > 0U) + { + for (i = 0U; i < uiSpaceNeeded; i++) + { + CStrncat(buffer, " ", 1U); + } + } +} + +static void CTextAlign(int8 *buffer, const int8 *str) +{ + Uint16 uiIndent, uiLen, i, j; + + uiLen = 0U; + i = 0U; + + while (str[i] != ASCII_NULL) // str은 int8* 이므로, int8 타입의 널 종료 값(0) 찾음 + { + uiLen++; + i++; + } + + if (uiLen >= (Uint16)TXT_MAX_LEN) + { + uiIndent = 0U; + } + else + { + uiIndent = (((Uint16)TXT_MAX_LEN - 1U) - uiLen) / 2U; + } + + if ((uiIndent > 0U) && (uiIndent < (Uint16)TXT_MAX_LEN)) // 리소스 과도 소비 방지 + { + for (i = 0U; i < uiIndent; i++) + { + buffer[i] = ASCII_BLANK; + } + + for (j = 0U; j < uiLen; j++) + { + buffer[i + j] = str[j]; + } + } + + buffer[i + uiLen] = ASCII_NULL; +} + +static void CDrawBox(Uint16 x, Uint16 y, Uint16 w, Uint16 h) +{ + CDrawLine(x, y, w, y); // 윗변 + CDrawLine(x, (y + 1U), x, (y + h)); // 좌측 막대 + CDrawLine(x, (y + h), w, (y + h)); // 아랫 변 + CDrawLine(w, (y + 1U), w, (h > 0U) ? (y + h - 1U) : y); // 우측 막대 +} + +static void CSetDrawRegion(Uint16 x, Uint16 y) +{ + if (x > OledOperValue.Point.X) + { + OledOperValue.Point.X = x; + } + if (y > OledOperValue.Point.Y) + { + OledOperValue.Point.Y = y; + } +} + +static void CDrawLine(Uint16 x1, Uint16 y1, Uint16 x2, Uint16 y2) +{ + Uint16 uiX1 = x1; + Uint16 uiY1 = y1; + Uint16 uiX2 = x2; + Uint16 uiY2 = y2; + + Uint16 tmp = 0U, x = 0U, y = 0U, dx = 0U, dy = 0U, swapxy = 0U; + Uint16 loop_end = 0U; + Uint16 minor_limit = 0U; /* 보조축(y) 한계값 */ + + int16 err = 0; + int16 ystep = 0; + + dx = uiX2 - uiX1; + dy = (uiY1 > uiY2) ? (uiY1 - uiY2) : (uiY2 - uiY1); + + if (dy > dx) + { + swapxy = 1U; + tmp = dx; dx = dy; dy = tmp; + + tmp = uiX1; uiX1 = uiY1; uiY1 = tmp; + tmp = uiX2; uiX2 = uiY2; uiY2 = tmp; + + loop_end = (Uint16)OLED_HEIGHT - 1U; + minor_limit = (Uint16)OLED_WIDTH - 1U; + } + else + { + loop_end = (Uint16)OLED_WIDTH - 1U; + minor_limit = (Uint16)OLED_HEIGHT - 1U; + } + + if (uiX2 > loop_end) + { + uiX2 = loop_end; + } + + err = (int16)((Uint16)(dx >> 1U)); + ystep = (uiY2 > uiY1) ? (int16)1 : (int16)-1; + y = uiY1; + + if (swapxy == 0U) + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(x, y, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } + else + { + for (x = uiX1; x <= uiX2; x++) + { + if (y > minor_limit) + { + break; + } + + CPutPixel(y, x, OledOperValue.Color.TxtColor); + + err = err - (int16)dy; + if (err < 0) + { + y = (ystep > 0) ? (y + (Uint16)ystep) : (y - (Uint16)(-ystep)); + err = err + (int16)dx; + } + } + } +} + +static inline void CPutPixel(Uint16 x, Uint16 y, Uint16 Color) +{ + Uint16 uiPage; + Uint16 uiOffset; + + if ((x < (Uint16)OLED_WIDTH) && (y < (Uint16)OLED_HEIGHT)) + { + uiPage = y / 8U; + uiOffset = y % 8U; + + if (Color == 1U) + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] | (Uint8)(1U << uiOffset)); + } + else + { + OledOperValue.uiBuff[x][uiPage] = (Uint8)(OledOperValue.uiBuff[x][uiPage] & (Uint8)(~(Uint8)(1U << uiOffset))); + } + } +} + +static void CSetPageAddress(Uint16 Address) +{ + COledWrite((Uint16)(Address | 0xB0U), (Uint16)MODE_COMMAND); +} + +static void CSetColumnAddress(Uint16 x) +{ + Uint16 HighAddress; + Uint16 LowAddress; + + x += 0U; // ER_OLEDM024-1G is +2, ER_OLEDM024-2G is +0 + HighAddress = ((x >> 4) & 0x0FU) | 0x10U; + LowAddress = x & 0x0FU; + + COledWrite(LowAddress, (Uint16)MODE_COMMAND); + COledWrite(HighAddress, (Uint16)MODE_COMMAND); +} + +void CInitXintf(void) +{ + /* for All Zones Timing for all zones based on XTIMCLK = SYSCLKOUT (150MHz) */ + EALLOW; + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + XintfRegs.XINTCNF2.bit.WRBUFF = 0; /* No write buffering */ + XintfRegs.XINTCNF2.bit.CLKOFF = 0; /* XCLKOUT is enabled */ + XintfRegs.XINTCNF2.bit.CLKMODE = 1; /* XCLKOUT = XTIMCLK */ + + /* Zone write timing */ + XintfRegs.XTIMING6.bit.XWRLEAD = 2; + XintfRegs.XTIMING6.bit.XWRACTIVE = 12; + XintfRegs.XTIMING6.bit.XWRTRAIL = 2; + + /* Zone read timing */ + XintfRegs.XTIMING6.bit.XRDLEAD = 2; + XintfRegs.XTIMING6.bit.XRDACTIVE = 12; + XintfRegs.XTIMING6.bit.XRDTRAIL = 2; + + XintfRegs.XTIMING6.bit.X2TIMING = 0; + XintfRegs.XTIMING6.bit.USEREADY = 0; + XintfRegs.XTIMING6.bit.READYMODE = 0; + XintfRegs.XTIMING6.bit.XSIZE = 3; + + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // OLED_D0 XD0 + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // OLED_D1 XD1 + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // OLED_D2 XD2 + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // OLED_D3 XD3 + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // OLED_D4 XD4 + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // OLED_D5 XD5 + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // OLED_D6 XD6 + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // OLED_D7 XD7 + + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // OLED_CS_C XZCS6 + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // OLED_WR_C XWE0 + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // OLED_A0_C XWE1 + + EDIS; +} + +static void CDrawStr(Uint16 x, Uint16 y, const int8* str) +{ + Uint16 i = 0U; + + if (str != NULL) + { + /* 널 문자를 만나거나 최대 한계에 도달할 때까지 그리기 수행 */ + while ((str[i] != ASCII_NULL) && (i < (Uint16)TXT_MAX_LEN)) + { + if (((Uint8)str[i] & 0x80U) != 0U) + { + CDrawChar(x, y, (Uint16)(((Uint16)str[i] << 8U) | (Uint16)str[i + 1U]), TXT_TYPE_ETC); + i++; + x += (TXT_ENG_WIDTH * 2U); + } + else + { + CDrawChar(x, y, (Uint16)str[i], TXT_TYPE_ENG); + x += TXT_ENG_WIDTH; + } + i++; + } + } +} + +static void CDrawChar(Uint16 x, Uint16 y, Uint16 ch, Uint16 type) +{ + // 영문 폰트 테이블 인덱스에 따른 값은 Description\font.txt 참조 + static const Uint16 EngFontTable[96][9] = + { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, { 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, { 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, + { 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, { 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, + { 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, { 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, + { 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, { 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, { 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, + { 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, + { 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, + { 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, { 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, + { 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, { 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, { 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, + { 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, { 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, { 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, + { 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, { 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, + { 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, { 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, { 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, + { 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, { 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, { 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, { 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, + { 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, { 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, + { 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, { 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, + { 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, { 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, + { 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, { 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, { 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, { 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, { 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, + { 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, { 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, + { 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, + { 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, { 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, { 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, + { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, { 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, + { 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, { 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, { 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, + { 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, + { 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, { 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, { 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, + { 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, { 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, { 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, + { 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, { 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, + }; + + static const Uint16 TemperatureFont[18] = { 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }; // ℃, A1C9 + static const Uint16 uiBitMask[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 }; + const Uint16* pFontData; + Uint16 uiFontIndex = 0; + Uint16 i, j; + Uint16 uiCharWidth; + Uint16 uiCh = ch; + + if (type == 0U) // Eng Char + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH; + uiCh -= 0x20U; // font offset + uiCh = (uiCh > 95U) ? 0U : uiCh; + pFontData = EngFontTable[uiCh]; + } + else + { + uiCharWidth = (Uint16)TXT_ENG_WIDTH * 2U; + pFontData = TemperatureFont; + } + + CSetDrawRegion((x + (Uint16)TXT_ENG_WIDTH), (y + (Uint16)TXT_ENG_HEIGHT)); + + for(j = 0U; j < (Uint16)TXT_ENG_HEIGHT; j++) + { + for(i = 0U; i < uiCharWidth; i++) + { + if (((Uint8)pFontData[uiFontIndex / 8U] & uiBitMask[uiFontIndex % 8U]) != 0U) + { + CPutPixel((x + i), (y + j), OledOperValue.Color.TxtColor); + } + else + { + CPutPixel((x + i), (y + j), OledOperValue.Color.BgColor); + } + uiFontIndex++; + } + } +} + +static void CInitOledModule(void) +{ + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + GpioDataRegs.GPBSET.bit.GPIO37 = 1U; // GPIO_OLED_RESET + DELAY_USEC(2000); + + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); // Command Lock + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); // + COledWrite((Uint16)0xAE, (Uint16)MODE_COMMAND); // oled off + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); // 1U segment column address high to low + + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); // COM output scan from high to low + + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); // 1U contrast + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); // oled on + + CInitOledStructure(); + OledOperValue.uiProgressValue = (Uint16)OLED_LOAD_PROGRESS_X + 1U; +} + +void CDisplayAntiNoiseRefresh(void) +{ + COledWrite((Uint16)0xFD, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0x12, (Uint16)MODE_COMMAND); + + /* 화면 방향 및 스캔 방향 재설정 (뒤집힘 방지) */ + COledWrite((Uint16)0xA1, (Uint16)MODE_COMMAND); /* Segment Remap: Column Address high to low */ + COledWrite((Uint16)0xC8, (Uint16)MODE_COMMAND); /* COM Output Scan: high to low */ + + /* 명암비(Contrast) 재설정 */ + COledWrite((Uint16)0x81, (Uint16)MODE_COMMAND); + COledWrite((Uint16)0xFF, (Uint16)MODE_COMMAND); + + /* Display ON 유지 확인 (노이즈로 화면이 꺼졌을 경우) */ + COledWrite((Uint16)0xAF, (Uint16)MODE_COMMAND); +} + +static void COledWrite(Uint16 Data, Uint16 Command) +{ + if (Command == (Uint16)MODE_COMMAND) + { + CommandBus = Data; + } + else + { + DataBus = Data; + } +} + +static void CInitOledStructure(void) +{ + (void)memset(&OledOperValue, 0, sizeof(COledOperValue)); + + OledOperValue.uiResetAlarmAnswer = 1U; +} + +void CInitKeyOperValue(void) +{ + (void)memset(&KeyOperValue, 0, sizeof(CKeyOperValue)); +} + +static Uint16 CStrLen(const int8 *s) +{ + Uint16 uiLen = 0U; + + if (s != NULL) + { + while (s[uiLen] != ASCII_NULL) + { + uiLen++; + } + } + + return uiLen; +} +static void CStrncpy(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiSafeLimit; + + uiSafeLimit = (Size >= TXT_MAX_LEN) ? (TXT_MAX_LEN - 1U) : Size; + + //for (i = 0U; i < uiSafeLimit; i++) + for (i = 0U; (i < uiSafeLimit) && (i < (TXT_MAX_LEN - 1U)); i++) + { + pTarget[i] = pSource[i]; + } + + pTarget[i] = ASCII_NULL; +} + +static void CStrncat(int8 *pTarget, const int8 *pSource, Uint16 Size) +{ + Uint16 i; + Uint16 uiTargetSize; + Uint16 uiRemainSpace; + Uint16 uiSafeLimit; + + uiTargetSize = 0U; + + if (pTarget != NULL) + { + /* 함수를 부르지 않고, 해당 위치에서 직접 널 문자를 찾을 때까지 카운트 (FUNCR 증가 없음) */ + while (pTarget[uiTargetSize] != ASCII_NULL) + { + uiTargetSize++; + } + } + + if (uiTargetSize < (Uint16)(TXT_MAX_LEN - 1U)) + { + uiRemainSpace = (Uint16)((Uint16)(TXT_MAX_LEN - 1U) - uiTargetSize); + + uiSafeLimit = (Size >= uiRemainSpace) ? uiRemainSpace : Size; + + for (i = 0U; (i < uiSafeLimit) && ((uiTargetSize + i) < (Uint16)(TXT_MAX_LEN - 1U)); i++) + { + pTarget[uiTargetSize + i] = pSource[i]; + } + + pTarget[uiTargetSize + i] = ASCII_NULL; + } +} + +static void CDecToString(int16 Data, int8 *Array, Uint16 ArrayLen) +{ + Uint16 uiSign = 0U; // 음수 여부 플래그 (1이면 음수) + Uint16 uiSignLocate = 0U; // '-' 부호가 들어갈 배열 인덱스 위치 + Uint16 i; + Uint16 x = 0U; // cTmp에 추출된 숫자의 개수 (자릿수 카운트) + Uint16 y = 0U; // 최종 문자열 Array에 값을 써넣을 인덱스 + + int32 lData = (int32)Data * 10; + + // 추출된 각 자리의 숫자를 임시로 저장할 버퍼 (역순으로 저장됨) + int8 cTmp[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + + // 출력할 배열 전체를 공백(ASCII 32 = ' ')으로 초기화 + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; + } + + // 음수 판별 및 절대값(양수) 변환 + if (lData < 0) + { + uiSign = 1U; + lData = -lData; + } + + // 1의 자리부터 역순으로 숫자를 추출하여 ASCII 문자(ASCII 48 = '0')로 변환 + while ((lData > 0) && (x < 6U)) + { + cTmp[x] = (int8)((lData % 10) + 48); + x++; + lData /= 10; + } + + // 추출한 숫자를 최종 배열에 배치 (우측 정렬 적용) + if (x == 0U) + { + // 수치가 0인 경우, 지정된 고정 위치(y=3)에 '0' 표시 + y = 4U; + if (y < ArrayLen) + { + Array[y] = ASCII_0; + y++; + } + } + else + { + if (x > 0U) + { + // 앞서 '* 10'으로 부풀리며 추가되었던 최하위 숫자(0)를 버리기 위해 인덱스를 1 감소시킴 + x = (Uint16)(x - 1U); + } + + // 전체 폭(5칸 기준)에서 자릿수를 빼서, 문자가 쓰이기 시작할 시작 위치(y) 계산 + y = (x <= 5U) ? (Uint16)(5U - x) : 0U; + + // 부호('-')가 들어갈 자리 지정 (숫자가 시작되는 곳의 바로 앞 칸) + if (y < 1U) + { + uiSignLocate = 0U; + } + else if (y <= 5U) + { + uiSignLocate = (Uint16)(y - 1U); + } + else + { + uiSignLocate = 0U; + } + + // 계산된 부호 위치에 '-' 또는 공백 삽입 + if (uiSign == 1U) + { + if ((uiSignLocate > 0U) && (uiSignLocate < 6U) && (uiSignLocate < ArrayLen)) + { + Array[uiSignLocate] = ASCII_MINUS; // '-' + } + } + else + { + if (uiSignLocate < ArrayLen) + { + Array[uiSignLocate] = ASCII_BLANK; // ' ' + } + } + + while ((x > 0U) && (x < 6U) && (y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = cTmp[x]; + y++; + x = (Uint16)(x - 1U); // 인덱스 감소 + } + } + + // 문자열의 끝을 알리는 널(NULL, ASCII 0) 문자 삽입하여 문자열 완성 + if ((y < ArrayLen) && (y < TXT_MAX_LEN)) + { + Array[y] = ASCII_NULL; + } + else + { + if (ArrayLen > 0U) + { + Array[(Uint16)(ArrayLen - 1U)] = ASCII_NULL; + } + } +} + +static void CFloatToString(float32 Data, int8 *Array, Uint16 ArrayLen) +{ + int32 iTemp; // 음수 처리를 위해 signed int32 사용 (범위 확보) + Uint16 isNegative = 0U; // 음수 여부 플래그 + int8 cTmp[10]; // 임시 변환 버퍼 + Uint16 len = 0U; // 현재 변환된 문자 길이 + Uint16 i; + Uint16 startIdx; // 최종 배열에 복사할 시작 위치 + + for (i = 0U; (i < ArrayLen) && (i < TXT_MAX_LEN); i++) + { + Array[i] = ASCII_BLANK; // ' ' + } + + // 음수 확인 및 양수 변환 + if (Data < 0.0F) + { + isNegative = 1U; + Data = -Data; // 절대값으로 변환 + } + + // 소수점 1자리 정수로 변환 (예: 12.34 -> 123.4 -> 123) + iTemp = (int32)((float32)((Data * 10.0F) + 0.5F)); + + // 소수점 첫째 자리 추출 + cTmp[len++] = (int8)((int8)(iTemp % 10) + ASCII_0); // '0' + iTemp /= 10; + + // 소수점 문자 추가 + cTmp[len++] = ASCII_DOT; // '.' + + // 정수부 추출 + if (iTemp == 0) + { + cTmp[len++] = ASCII_0; // 0.x 인 경우 정수부 '0' 추가 + } + else + { + while (iTemp > 0) + { + cTmp[len++] = (int8)((int32)(iTemp % 10) + (int32)ASCII_0); + iTemp /= 10; + } + } + + // 부호 추가 + if (isNegative == 1U) + { + cTmp[len++] = ASCII_MINUS; // '-' + } + + // 최종 배열에 복사 (우측 정렬, 총 6자리 제한) + + // 만약 변환된 길이가 6자리를 넘으면 6자리로 자름 + if (len > 6U) + { + len = 6U; + } + + if (ArrayLen >= 7U) // ArrayLen 보호 + { + startIdx = 6U - len; + + for (i = 0U; i < len; i++) + { + Array[startIdx + i] = cTmp[len - 1U - i]; // cTmp는 역순이므로 len-1-i 로 접근 + } + + Array[6] = ASCII_NULL; + } +} + +void CInitializePage(void) +{ + CDrawLine((Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 2U), (Uint16)(OledOperValue.uiProgressValue + 1U), (Uint16)(OLED_LOAD_PROGRESS_Y + 8U)); + if (OledOperValue.uiProgressValue < (Uint16)OLED_LOAD_PROGRESS_W - 3U) // -3은 프로그래스 바의 좌우측 1픽셀 공간 줌. + { + OledOperValue.uiProgressValue++; + } + else + { + OledOperValue.uiProgressDone = 1U; + } +} + +void CDisplayPostFail(void) +{ + CDrawCenteredLine(IDX_OLED_LINE_TITLE, "Power On Self-Test"); + CDrawCenteredLine(IDX_OLED_LINE_1, "(P:PASS F:FAIL)"); + + // LINE 2 + CDrawPostStatusLine(IDX_OLED_ROW_2, "EHT:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_ENGINE_HEATER], "GPL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_GLOW_PLUG], "SOL:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_SOLENOID]); + + // LINE 3 + CDrawPostStatusLine(IDX_OLED_ROW_3, "FUP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FUEL_PUMP], "CLP:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_COOLANT_PUMP], "FN1:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN1]); + + // LINE 4 + // Only FN2 + CDrawPostStatusLine(IDX_OLED_ROW_4, " FN2:", PowerOnCheckSensor[(Uint16)IDX_SENSOR_FAN2], NULL, 0, NULL, 0); +} +static void CLineFocus(Uint16 isFocus) +{ + if (isFocus == 1U) + { + OledOperValue.Color.TxtColor = 0U; + OledOperValue.Color.BgColor = 1U; + } + else + { + OledOperValue.Color.TxtColor = 1U; + OledOperValue.Color.BgColor = 0U; + } +} + +static void CMakeVersionString(int8 Buffer[], int16 v1, int16 v2, int16 v3) +{ + int16 verArray[3]; + int16 i, k; + int16 num; + int8 tempArr[6] = { ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL, ASCII_NULL }; + int16 tempIdx; + Uint16 currentIdx = 0U; // 함수 내부에서 0부터 시작 + + verArray[0] = v1; + verArray[1] = v2; + verArray[2] = v3; + + for (i = 0; i < 3; i++) + { + num = verArray[i]; + tempIdx = 0; + + // 숫자 -> 문자 변환 + if (num == 0) + { + tempArr[tempIdx++] = ASCII_0; // '0' + } + else + { + if (num < 0) { num = -num; } + while (num > 0) + { + tempArr[tempIdx++] = (int8)((num % 10) + ASCII_0); // '0' + num /= 10; + } + } + + // 2. 버퍼에 기록 + for (k = (tempIdx - 1); k >= 0; k--) + { + Buffer[currentIdx++] = tempArr[k]; + } + + // 3. 점(.) 찍기 (마지막 아닐 때만) + if (i < 2) + { + Buffer[currentIdx++] = ASCII_DOT; // '.' + } + } + + // ★ 문자열 끝 처리 (함수 안으로 이동됨) + Buffer[currentIdx] = ASCII_NULL; +} + +static void CHourToString(int32 num, int8 *str) +{ + Uint16 i = 0U; + Uint16 end; + Uint32 temp = (Uint32)num; // 입력받은 값 (예: 1234567 -> "12345.67") + + // 소수점 둘째 자리 (100분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 첫째 자리 (10분의 1) + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + + // 소수점 삽입 + str[i++] = ASCII_DOT; + + // 정수부 변환, 입력이 0이어도 최소 "0"은 찍히도록 do-while 사용 + do + { + str[i++] = (int8)((Uint32)((temp % 10U) + (Uint32)ASCII_0)); + temp = temp / 10U; + } + while (temp != 0U); + + // 공백 채우기 (자리수 맞춤), 정수5자리 + 점1자리 + 소수2자리 = 총 8자리 + while (i < 8U) + { + str[i++] = ASCII_BLANK; + } + + str[i] = ASCII_NULL; // 문자열 끝 + + end = i - 1U; + i = 0U; + + while (i < end) + { + int8 swapTemp = str[i]; + str[i] = str[end]; + str[end] = swapTemp; + i++; + end--; + } +} + +static const int8* CGetApuStateString(Uint16 idx) +{ + static const int8* const strTable[] = + { + "BOOT", // 0 + "INIT", // 1 + "POST", // 2 + "EMERGENCY", // 3 + "STANDBY", // 4 + "READY", // 5 + "PREHEAT", // 6 + "CRANKING", // 7 + "", // 8: RETRY (동적 처리) + "IDLE", // 9 + "GENERATING", // 10 + "COOLDOWN", // 11 + "STOPPING" // 12 + }; + + static int8 strBuffer[12]; + const int8* pRetVal = strTable[idx]; + + if (idx == (Uint16)IDX_APU_OPER_RETRY_CRANKING) + { + Uint16 count = GeneralOperValue.uiRetryCrankingCount + 1U; + + strBuffer[0] = ASCII_R; // 'R' + strBuffer[1] = ASCII_E; // 'E' + strBuffer[2] = ASCII_T; // 'T' + strBuffer[3] = ASCII_R; // 'R' + strBuffer[4] = ASCII_Y; // 'Y' + strBuffer[5] = ASCII_L_PAREN; // '(' + strBuffer[6] = (ASCII_0 + (int8)count); + strBuffer[7] = ASCII_R_PAREN; // ')' + strBuffer[8] = ASCII_NULL; //'\0' + + pRetVal = (const int8*)strBuffer; + } + + return pRetVal; +} + +static void CCopyStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pSource[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i] = pSource[i]; + i++; + } + pTarget[i] = ASCII_NULL; + } +} + +static void CAppendStr(int8 *pTarget, const int8 *pSource) +{ + Uint16 i = 0U; + Uint16 j = 0U; + + if ((pTarget != NULL) && (pSource != NULL)) + { + while ((pTarget[i] != ASCII_NULL) && (i < (Uint16)(TXT_MAX_LEN - 1U))) + { + i++; + } + + while ((pSource[j] != ASCII_NULL) && ((i + j) < (Uint16)(TXT_MAX_LEN - 1U))) + { + pTarget[i + j] = pSource[j]; + j++; + } + pTarget[i + j] = ASCII_NULL; + } +} + +static void CDrawLineText(Uint16 x, Uint16 y, const int8* str) +{ + CDrawStr(x, y, str); +} + +static void CDrawFaultStatusLine(Uint16 row, const int8* label1, Uint16 status1, const int8* label2, Uint16 status2) +{ + CDrawTwoStatusLine(row, label1, status1, label2, status2); +} + +static void CDrawSimpleLine(Uint16 row, const int8* label) +{ + CDrawPageLine(row, label, NULL, NULL); +} + +static void CDrawStatusTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawSensorTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} + +static void CDrawFaultTitle(const int8* title, const int8* pageNumStr) +{ + CDrawPageTitle(title, pageNumStr); +} diff --git a/Source/.staticdata/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ b/Source/.staticdata/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ new file mode 100644 index 0000000..3c5a7c3 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/beb797cd9bcae5c0ce186c9071f47086_ @@ -0,0 +1,195 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:52:24 $ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ b/Source/.staticdata/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ new file mode 100644 index 0000000..20cec0d --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/c3ce07430b9437ddee99bdc151b20aae_ @@ -0,0 +1,255 @@ +// TI File $Revision: /main/4 $ +// Checkin $Date: March 20, 2007 15:33:42 $ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ b/Source/.staticdata/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ new file mode 100644 index 0000000..284b30c --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/d0b4282a2e158286ab30bf0c1acd95ac_ @@ -0,0 +1,251 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: March 1, 2007 15:57:02 $ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 b/Source/.staticdata/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 new file mode 100644 index 0000000..f54e5d3 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/d4d10244d3cbba60805c13f0c6e2a0c2 @@ -0,0 +1,586 @@ +/* ========================================================================= */ +/* 1. Includes */ +/* ========================================================================= */ +#include "main.h" + +/* ========================================================================= */ +/* 2. Local Macros & Constants (내부 전용 매크로 및 상수) */ +/* ========================================================================= */ +#define ENGINE_MAXIMUM_SPEED (2800U) +#define ENGINE_OPERATION_SPEED (2400U) +#define ENGINE_DIFF_SPEED (400U) // 2800 - 2400 + +#define LED_OFF (0U) +#define LED_ON (1U) +#define LED_BLINK (2U) + +/* ========================================================================= */ +/* 3. Local Typedefs & Structures (내부 전용 사용자 정의 자료형) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* 4. Internal Linkage Function Declarations (내부 동작용 Static 함수 선언) */ +/* ========================================================================= */ +static void CInitialStandby(void); +static void CEmergencyStop(void); +static void CProcessApuStateReady(void); +static void CProcessApuStatePreheat(void); +static void CProcessApuStateCranking(void); +static void CProcessApuStateRetryCranking(void); +static void CProcessApuStateEngineIdle(void); +static void CProcessApuStateGenerating(void); +static void CProcessApuStateCooldown(void); +static void CProcessApuStateStopping(void); +static void CProcessApuStateTransition(void); // 비상/시동/정지 전이 판별용 +static void CSetEngineActualRpm(Uint16 Rpm); +static float32 CGetGcuLoadPower(void); +static Uint16 CDynamicRpmControl(void); +static void CLedControl(Uint16 idx, Uint16 state); + +/* ========================================================================= */ +/* 5. Global Variables & Structure Initialization (전역 변수 및 구조체 초기화) */ +/* ========================================================================= */ +// No Code + +/* ========================================================================= */ +/* Function Definitions */ +/* ========================================================================= */ +static void CProcessApuStateReady(void) +{ + // 냉각수 펌프 및 냉각팬 시작 + CSetAuxCtrlPin(IDX_CS_COOLANT_PUMP, 1U); + CSetAuxCtrlPin(IDX_CS_FAN1, 1U); + CSetAuxCtrlPin(IDX_CS_FAN2, 1U); + + // ECU 동작 명령 송신, 2400 RPM 설정 + CSetEcuCommand((Uint16)IDX_ECU_CMD_START); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_PREHEAT; +} + +static void CProcessApuStatePreheat(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_STARTING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + } + else + { + // PRE HEAT 상태가 60초 이상 지속 될 경우 알람처리 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_PREHEAT, TIME_60SEC) == (Uint16)TIME_OVER) + { + // 알람처리를 할지 무기한 대기 할 지 검토 필요 + } + } +} + +static void CProcessApuStateCranking(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_IDLE) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_ENGINE_IDLE; + GeneralOperValue.uiRetryCrankingCount = 0U; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + else + { + // 10초간 시동 시도 → 5초 동안 휴식 → 3회 반복 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_CRANKING, TIME_10SEC) == (Uint16)TIME_OVER) + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP_CRANKING); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_RETRY_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + } + } +} + +static void CProcessApuStateRetryCranking(void) +{ + if (GeneralOperValue.uiRetryCrankingCount < 3U) + { + // 5초 대기 후 재시도 + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_RETRY_CRANKING, (TIME_1SEC * 5UL)) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiRetryCrankingCount++; + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_CRANKING; + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + } + } + else + { + ulDcuTotalAlarm = (1UL << (Uint32)(Uint16)IDX_FAULT_DCU_CRANKING_FAIL); + } +} + +static void CProcessApuStateEngineIdle(void) +{ + if (((Rx301.State >> 1U) & 0x07U) == (Uint16)IDX_ECU_STAT_OPERATION) + { + // 보조엔진제어기의 상태가 OPERATION이고 보조엔진의 속도가 2300 RPM 이상 5초 유지 시 발전상태로 전환 + if (CGetEngineActualRpm() >= (ENGINE_OPERATION_SPEED - 100U)) // 2300 RPM + { + if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_OPERATION, TIME_5SEC) == (Uint16)TIME_OVER) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_GENERATING; + } + } + else + { + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + } + } +} + +static void CProcessApuStateGenerating(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_GENERATING); // 발전 명령 송신 + GeneralOperValue.uiDynamicRPM = CDynamicRpmControl(); + CSetEngineActualRpm(GeneralOperValue.uiDynamicRPM); // RPM 가변 제어 시작 +} + +static void CProcessApuStateCooldown(void) +{ + Uint16 IsRpmZero; + Uint16 IsTimeout; + + // 쿨다운: 발전 중지 -> 엔진 IDLE로 변경 + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + IsRpmZero = (CGetEngineActualRpm() == 0U) ? 1U : 0U; + IsTimeout = (CSoftWaitCountProcedure(SOFTTIMER_WAIT_AFTER_COOLDOWN, TIME_60SEC) == 1U) ? 1U : 0U; + + if ((IsRpmZero == 1U) || (IsTimeout == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } +} + +static void CProcessApuStateStopping(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STOPPING) + { + CInitialStandby(); + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + } +} + +static void CProcessApuStateTransition(void) +{ + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_EMERGENCY) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STANDBY; + CInitialStandby(); + } + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_STANDBY) + { + if (KeyOperValue.KeyList.EngineStartStop == 1U) + { + GeneralOperValue.uiRetryCrankingCount = 0U; + if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_READY; + } + else + { + CommCheck.Gcu = (GeneralOperValue.Conection.Gcu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + CommCheck.Ecu = (GeneralOperValue.Conection.Ecu == 0U) ? COMM_TIME_OUT_COUNT : 0U; + } + } + } + else + { + if ((GeneralOperValue.uiApuState >= (Uint16)IDX_APU_OPER_READY) && (GeneralOperValue.uiApuState <= (Uint16)IDX_APU_OPER_GENERATING)) + { + if (KeyOperValue.KeyList.EngineStartStop == 0U) + { + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_COOLDOWN; + } + else + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_STOPPING; + } + } + } + } +} + +void CApuOperProcedure(void) +{ + // 입력 신호 Lo Active + Uint16 EngineHeaterSig = (GPIO_ENGINE_HEATER_ACTIVE() == false) ? 1U : 0U; + Uint16 FuelPumpSig = (GPIO_FUEL_PUMP_ACTIVE() == false) ? 1U : 0U; + Uint16 GlowPlugSig = (GPIO_GLOW_PLUG_ACTIVE() == false) ? 1U : 0U; + Uint16 SolenoidSig = (GPIO_SOLENOID_ACTIVE() == false) ? 1U : 0U; + Uint16 FailSafeSig = (GPIO_FAIL_SAFE_READ() == false) ? 1U : 0U; + + // 비상 상황 체크 + if ((GeneralOperValue.uiFaultOccured > 0U) || (KeyOperValue.KeyList.Emergency == 1U) || (FailSafeSig == 1U)) + { + GeneralOperValue.uiApuState = (Uint16)IDX_APU_OPER_EMERGENCY; + CEmergencyStop(); + } + else + { + // 외부 조작에 의한 상태 변경 확인 + CProcessApuStateTransition(); + + // ECU Aux Bypass 제어 + if (GeneralOperValue.uiApuState > (Uint16)IDX_APU_OPER_STANDBY) + { + CSetAuxCtrlPin(IDX_CS_ENG_HEATER, EngineHeaterSig); + CSetAuxCtrlPin(IDX_CS_GLOW_PLUG, GlowPlugSig); + CSetAuxCtrlPin(IDX_CS_SOLENOID, SolenoidSig); + CSetAuxCtrlPin(IDX_CS_FUEL_PUMP, FuelPumpSig); + } + + // 각 상태별 동작 수행 + switch (GeneralOperValue.uiApuState) + { + case (Uint16)IDX_APU_OPER_READY: + { + CProcessApuStateReady(); + break; + } + case (Uint16)IDX_APU_OPER_PREHEAT: + { + CProcessApuStatePreheat(); + break; + } + case (Uint16)IDX_APU_OPER_CRANKING: + { + CProcessApuStateCranking(); + break; + } + case (Uint16)IDX_APU_OPER_RETRY_CRANKING: + { + CProcessApuStateRetryCranking(); + break; + } + case (Uint16)IDX_APU_OPER_ENGINE_IDLE: + { + CProcessApuStateEngineIdle(); + break; + } + case (Uint16)IDX_APU_OPER_GENERATING: + { + CProcessApuStateGenerating(); + break; + } + case (Uint16)IDX_APU_OPER_COOLDOWN: + { + CProcessApuStateCooldown(); + break; + } + default: + { + CProcessApuStateStopping(); + break; + } + } + } +} + +static Uint16 CDynamicRpmControl(void) +{ + float32 TargetRPM; + Uint16 ReturnRpm; + + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + // 0.0kW~17.0kW 부하량에 따라 목표 RPM 실시간 계산 + TargetRPM = (float32)ENGINE_OPERATION_SPEED + ((CGetGcuLoadPower() * 0.058823F) * (float32)ENGINE_DIFF_SPEED); // 0.058823 = 1/17kw + + ReturnRpm = (Uint16)((float32)(TargetRPM + 0.5F)); // 소수점 반올림 + } + else + { + // 발전 상태가 아닐 때는 기본 2400 RPM 반환 + ReturnRpm = ENGINE_OPERATION_SPEED; + } + + ReturnRpm = (ENGINE_MAXIMUM_SPEED > ReturnRpm) ? ReturnRpm : ENGINE_MAXIMUM_SPEED; + + return ReturnRpm; +} + +static void CInitialStandby(void) +{ + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_STOP); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_PREHEAT); + + CSoftWaitCountClear(SOFTTIMER_WAIT_OPERATION); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 0U; + + GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD +} + +static void CEmergencyStop(void) +{ + KeyOperValue.KeyList.EngineStartStop = 0U; // 비상정지 상황에서는 시동/정지 키 초기화 + + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + + CSetEcuCommand((Uint16)IDX_ECU_CMD_EMERGENCY); + + COffChipSelect(); + + CSoftWaitCountClear(SOFTTIMER_WAIT_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_RETRY_CRANKING); + + CSoftWaitCountClear(SOFTTIMER_WAIT_AFTER_COOLDOWN); + + GeneralOperValue.uiEmergency = 1U; + + GpioDataRegs.GPBSET.bit.GPIO55 = 1U; //GPIO_FAULT_CMD +} + +static void CSetEngineActualRpm(Uint16 Rpm) +{ + GeneralOperValue.EcuCommand.RpmSetPoint = Rpm; +} + +Uint16 CGetEngineActualRpm(void) +{ + return (Uint16)Rx320.ActualRpm; +} + +static float32 CGetGcuLoadPower(void) +{ + float32 power = ((float32)Rx220.Power * 0.1F); + + // 범위를 0.0 ~ 17.0 으로 제한 + if (power > 17.0F) + { + power = 17.0F; + } + else + { + if (power < 0.0F) + { + power = 0.0; + } + } + return power; +} + +Uint16 CGetGeneratorRpm(void) +{ + return Rx220.Rpm; +} + +void CSetGcuCommand(Uint16 Command) +{ + GeneralOperValue.GcuCommand.PlayCmd = Command; +} + +void CSetEcuCommand(Uint16 Command) +{ + if ((Command == (Uint16)IDX_ECU_CMD_STOP) || (Command == (Uint16)IDX_ECU_CMD_EMERGENCY)) + { + GeneralOperValue.EcuCommand.EngineStart = 0U; + GeneralOperValue.EcuCommand.EngineStop = 1U; + CSetEngineActualRpm(0U); + } + else + { + // [ECU_OPER_CMD_START] + GeneralOperValue.EcuCommand.EngineStart = 1U; + GeneralOperValue.EcuCommand.EngineStop = 0U; +#if 0 // RPM 테스트 + CSetEngineActualRpm(Rx400.SetRPM.PCAN_RPM); +#else + CSetEngineActualRpm(2400U); +#endif + } +} + +int16 CGetEngCoolantTemperature(void) +{ + return (int16) Rx321.CoolantTemperature - 40; // 온도 오프셋 -40도 +} + +void CDebugModeProcedure(void) +{ + if (GeneralOperValue.Maintenance.ManualCranking == 1U) + { + if (GeneralOperValue.uiFaultOccured == 0U) + { + // 알람이 없을 경우만 동작 하도록 함. + CSetGcuCommand((Uint16)IDX_GCU_CMD_CRANKING); + } + } + else + { + CSetGcuCommand((Uint16)IDX_GCU_CMD_STOP); + } + + if (GeneralOperValue.Maintenance.LampTest == 1U) + { + CLedControl(0U, 1U); + CLedControl(1U, 1U); + CLedControl(2U, 1U); + } + else + { + CLedControl(0U, 0U); + CLedControl(1U, 0U); + CLedControl(2U, 0U); + } + + if (GeneralOperValue.Maintenance.KeyTest == 1U) + { + Uint16 uiKeyUp = (GPIO_KEY_UP() == 0U) ? 1U : 0U; + Uint16 uiKeyDn = (GPIO_KEY_DOWN() == 0U) ? 1U : 0U; + + if ((uiKeyUp == 1U) && (uiKeyDn == 1U)) + { + GeneralOperValue.Maintenance.KeyTest = 0U; + OledOperValue.uiPageNum = (Uint16)IDX_OLED_PAGE_MAINTENANCE; + } + } +} + +void CLedControlProcedure(void) +{ + static const CLedPattern APU_LED_TABLE[] = // LED 룩업 테이블 + { + // FAULT, OPER, STOP + {LED_OFF, LED_OFF, LED_ON }, // 0: BOOT + {LED_OFF, LED_OFF, LED_ON }, // 1: INITIAL + {LED_OFF, LED_OFF, LED_ON }, // 2: POST + {LED_ON, LED_OFF, LED_ON }, // 3: EMERGENCY + {LED_OFF, LED_OFF, LED_ON }, // 4: STANDBY + + // --- OPER 깜빡임 구간 (준비~예열) --- + {LED_OFF, LED_BLINK, LED_OFF }, // 5: READY + {LED_OFF, LED_BLINK, LED_OFF }, // 6: PREPARE_START + {LED_OFF, LED_BLINK, LED_OFF }, // 7: CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 8: RETRY_CRANKING + {LED_OFF, LED_BLINK, LED_OFF }, // 9: ENGINE_WARM_UP + + {LED_OFF, LED_ON, LED_OFF }, // 10: GENERATING (정상 운전) + + // --- STOP 깜빡임 구간 (APU 정지 시) --- + {LED_OFF, LED_ON, LED_BLINK }, // 11: COOLDOWN (STOP 깜빡임, OPER는 켜둠) + {LED_OFF, LED_ON, LED_BLINK } // 12: STOPPING (COOLDWON이 순식간에 지나가기 때문에 점멸로 수정) + }; + + CLedPattern TargetLeds = {0, 0, 0}; + + Uint64 SoftClock = CGetSoftClock(); + Uint16 IsBlinkOn = ((SoftClock % 10000U) < 5000U) ? 1U : 0U; // 0.5s 점멸을 위함 + Uint16 WarningValue = 0U; + + TargetLeds = APU_LED_TABLE[GeneralOperValue.uiApuState]; + + // 발전상태에서 경고 발생시 FAULT LED 깜빡이도록 설정 + if (GeneralOperValue.uiApuState == (Uint16)IDX_APU_OPER_GENERATING) + { + WarningValue = ((((Uint16)Rx210.GcuWarning & (Uint16)MASK_LOW_NIBBLE) | ((Uint16)Rx310.EcuWarning & 0xFDU)) > 0U) ? 1U : 0U; + } + + // 비상정지 상태가 아닌 경우에만 경고비트에 점멸 대응 + if ((GeneralOperValue.uiApuState != (Uint16)IDX_APU_OPER_EMERGENCY) && (WarningValue == 1U)) + { + TargetLeds.Fault = (Uint16)LED_BLINK; + } + + // FAULT LED 제어 + if (TargetLeds.Fault == (Uint16)LED_BLINK) + { + CLedControl(0U, IsBlinkOn); + } + else + { + CLedControl(0U, TargetLeds.Fault); + } + + // OPERATION LED 제어 + if (TargetLeds.Operation == (Uint16)LED_BLINK) + { + CLedControl(1U, IsBlinkOn); + } + else + { + CLedControl(1U, TargetLeds.Operation); + } + + // STOP LED 제어 + if (TargetLeds.Stop == (Uint16)LED_BLINK) + { + CLedControl(2U, IsBlinkOn); + } + else + { + CLedControl(2U, TargetLeds.Stop); + } +} + +static void CLedControl(Uint16 idx, Uint16 state) +{ + /* + * idx + * 0 : FAULT LED + * 1 : OPER LED + * 2 : STOP LED + */ + + if (idx == 0U) + { + // GPIO_CPU_LED_FAULT + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO14 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO14 = 1U; + } + } + else if (idx == 1U) + { + // GPIO_CPU_LED_OPERATION + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO13 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO13 = 1U; + } + } + else + { + // GPIO_CPU_LED_STOP + if (state == 0U) + { + GpioDataRegs.GPACLEAR.bit.GPIO12 = 1U; + } + else + { + GpioDataRegs.GPASET.bit.GPIO12 = 1U; + } + } +} diff --git a/Source/.staticdata/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ b/Source/.staticdata/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ new file mode 100644 index 0000000..3245a1d --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/d75fd8a9a8f6a4d86ed87452f4b37e5e_ @@ -0,0 +1,206 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:45:37 $ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ b/Source/.staticdata/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ new file mode 100644 index 0000000..b8d0bbd --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/dd8d114f9d4090743a4f2678af8cc2dd_ @@ -0,0 +1,484 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 12, 2008 09:34:58 $ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ b/Source/.staticdata/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ new file mode 100644 index 0000000..410cdc7 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/df9f62d7db349a76fb310a1817f88d02_ @@ -0,0 +1,139 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: August 14, 2007 16:32:29 $ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ b/Source/.staticdata/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ new file mode 100644 index 0000000..24dd005 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/f4c48238da22647d03d8d119102df0e8_ @@ -0,0 +1,285 @@ +// TI File $Revision: /main/1 $ +// Checkin $Date: August 18, 2006 13:51:50 $ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ b/Source/.staticdata/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ new file mode 100644 index 0000000..3fb50a3 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/f6434e593997cc3ef7afd8427bf5a52c_ @@ -0,0 +1,807 @@ +// TI File $Revision: /main/5 $ +// Checkin $Date: May 14, 2008 16:30:31 $ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/Source/.staticdata/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ b/Source/.staticdata/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ new file mode 100644 index 0000000..bb1cb9a --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/fe4f1419c3c067e59d2698ac4835fd68_ @@ -0,0 +1,397 @@ +// TI File $Revision: /main/11 $ +// Checkin $Date: June 23, 2008 11:34:15 $ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: 2833x/2823x Header Files V1.32 $ +// $Release Date: June 28, 2010 $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/Source/.staticdata/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ b/Source/.staticdata/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ new file mode 100644 index 0000000..a369808 --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/ff6e8e0283a44c228de251de2977635d_ @@ -0,0 +1,53 @@ + +// TI File $Revision: /main/1 $ +// Checkin $Date: April 22, 2008 14:35:56 $ +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// $Copyright: +// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/Source/.staticdata/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 b/Source/.staticdata/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 new file mode 100644 index 0000000..d11e0da --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/ffd39a99ec5176ce64cc758f34a11f56 @@ -0,0 +1,219 @@ +#ifndef SOURCE_STATE_H_ +#define SOURCE_STATE_H_ + +#define COMM_TIME_OUT_COUNT (3000U) // 3sec + +typedef enum +{ + IDX_ADC_ENGINE_HEATER_V = 0U, // 0 + IDX_ADC_GLOW_PLUG_V, // 1 + IDX_ADC_SOLENOID_V, // 2 + IDX_ADC_FUEL_PUMP_V, // 3 + IDX_ADC_COOLANT_PUMP_V, // 4 + IDX_ADC_FAN1_V, // 5 + IDX_ADC_FAN2_V, // 6 + IDX_ADC_ENGINE_HEATER_I, // 7 + IDX_ADC_GLOW_PLUG_I, // 8 + IDX_ADC_SOLENOID_I, // 9 + IDX_ADC_FUEL_PUMP_I, // 10 + IDX_ADC_COOLANT_PUMP_I, // 11 + IDX_ADC_FAN1_I, // 12 + IDX_ADC_FAN2_I, // 13 + IDX_ADC_MAX +} E_IDX_ADC; + +typedef enum +{ + IDX_WARNING_GCU_PCB_OT = 0U, + IDX_WARNING_GCU_FET_OT, + IDX_WARNING_GCU_WINDING1_OH, + IDX_WARNING_GCU_WINDING2_OH, + IDX_WARNING_GCU_MAX +} E_IDX_WARNING_GCU; + +typedef enum +{ + IDX_WARNING_ECU_ENGINE_OH = 0U, + IDX_WARNING_ECU_RESERVED, + IDX_WARNING_ECU_LO_OIL_PRESS, + IDX_WARNING_ECU_INTAKE_OH, + IDX_WARNING_ECU_INTAKE_LO_PRESS, + IDX_WARNING_ECU_ENGINE_LO_TEMP, + IDX_WARNING_ECU_ENGINE_SENSOR, + IDX_WARNING_ECU_DEFAULT_ACTIVE, + IDX_WARNING_ECU_MAX +} E_IDX_WARNING_ECU; + +typedef enum +{ + IDX_FAULT_DCU_CAR_COMM = 0U, // 0 + IDX_FAULT_DCU_GCU_COMM, // 1 + IDX_FAULT_DCU_ECU_COMM, // 2 + IDX_FAULT_DCU_RPM_ERR, // 3 + IDX_FAULT_DCU_ENGINE_HEAT_OC, // 4 + IDX_FAULT_DCU_GLOW_PLUG_OC, // 5 + IDX_FAULT_DCU_SOLENOID_OC, // 6 + IDX_FAULT_DCU_FUEL_PUMP_OC, // 7 + IDX_FAULT_DCU_COOLANT_PUMP_OC, // 8 + IDX_FAULT_DCU_FAN1_OC, // 9 + IDX_FAULT_DCU_FAN2_OC, // 10 + IDX_FAULT_DCU_ENGINE_HEAT_UV, // 11 + IDX_FAULT_DCU_ENGINE_HEAT_OV, // 12 + IDX_FAULT_DCU_GLOW_PLUG_UV, // 13 + IDX_FAULT_DCU_GLOW_PLUG_OV, // 14 + IDX_FAULT_DCU_SOLENOID_UV, // 15 + IDX_FAULT_DCU_SOLENOID_OV, // 16 + IDX_FAULT_DCU_FUEL_PUMP_UV, // 17 + IDX_FAULT_DCU_FUEL_PUMP_OV, // 18 + IDX_FAULT_DCU_COOLANT_PUMP_UV, // 19 + IDX_FAULT_DCU_COOLANT_PUMP_OV, // 20 + IDX_FAULT_DCU_FAN1_UV, // 21 + IDX_FAULT_DCU_FAN1_OV, // 22 + IDX_FAULT_DCU_FAN2_UV, // 23 + IDX_FAULT_DCU_FAN2_OV, // 24 + IDX_FAULT_DCU_CRANKING_FAIL, // 25 + IDX_FAULT_DCU_MAX +} E_IDX_DCU_FAULT; + +typedef enum +{ + IDX_FAULT_GCU_HWTRIP = 0U, // 0 + IDX_FAULT_GCU_HWIGBT, // 1 + IDX_FAULT_GCU_HW_DC, // 2 + IDX_FAULT_GCU_GEN_OCU, // 3 + IDX_FAULT_GCU_GEN_OCV, // 4 + IDX_FAULT_GCU_GEN_OCW, // 5 + IDX_FAULT_GCU_DC_OV, // 6 + IDX_FAULT_GCU_DC_OC, // 7 + + IDX_FAULT_GCU_CRANK_OC, // 8 + IDX_FAULT_GCU_PCB_OT, // 9 + IDX_FAULT_GCU_FET_OT, // 10 + IDX_FAULT_GCU_WINDING1_OH, // 11 + IDX_FAULT_GCU_WINDING2_OH, // 12 + IDX_FAULT_GCU_GEN_OS, // 13 + IDX_FAULT_GCU_RES_IC, // 14 + IDX_FAULT_GCU_RES_PRTY, // 15 + IDX_FAULT_GCU_MAX +} E_IDX_GCU_FAULT; + +typedef enum +{ + IDX_FAULT_ECU_OIL_MS = 0U, // 0 + IDX_FAULT_ECU_INT_OH, // 1 + IDX_FAULT_ECU_ENG_OH, // 2 + IDX_FAULT_ECU_ACTUATOR, // 3 + IDX_FAULT_ECU_RPM_SIG, // 4 + IDX_FAULT_ECU_ENG_SF, // 5 + IDX_FAULT_MAX +} E_IDX_ECU_FAULT; + +typedef enum +{ + IDX_KEY_MAIN_POWER = 0U, // 0 + IDX_KEY_ARR_UP, // 1 + IDX_KEY_ARR_DOWN, // 2 + IDX_KEY_ENTER, // 3 + IDX_KEY_MENU, // 4 + IDX_KEY_ENG_START_STOP, // 5 + IDX_KEY_EMERGENCY, // 6 + IDX_KEY_REMOTE_START, // 7 + IDX_KEY_REMOTE_STOP, // 8 + IDX_KEY_REMOTE_EMERGENCY, // 9 + IDX_KEY_BATTLE_MODE, // 10 + IDX_KEY_MAX // 11 +} E_IDX_KEY; + +typedef struct ClassKeyHandler +{ + E_IDX_KEY eKey; + void (*pAction) (void); +} CKeyHandler; + +typedef struct ClassAdcOperValue +{ + Uint16 uiAdcOffsetIndex; + Uint16 uiOffsetAdjustStart; +} CAdcOperValue; + +typedef struct ClassAdcCalcValue +{ + float32 fLpfValue; + float32 fSampledValue; + float32 fSampledSum; + float32 fTempAdcOffset; + float32 fGain; + float32 fOffset; + Uint16 uiSamplingCount; + int16 iAdcValue; +} CAdcCalcValue; + +typedef struct ClassWarningOperValue +{ + float32 fCheckLimit; // 경고 한계 값 + Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중 + Uint16 uiDetectCount; // 경고 검출 카운터 + Uint16 uiReleaseCount; // 경고 해제 카운터 + Uint16 uiCheckTime; +} CWarningOperValue; + +typedef struct ClassAlarmOperValue +{ + float32 fCheckLimit; + float32 fFaultValue; + Uint16 uiCheck; + Uint16 uiCheckCount; + Uint16 uiCheckTime; +} CAlarmOperValue; + +typedef struct ClassKeyList +{ + Uint16 MainPower; + Uint16 ArrowUp; + Uint16 ArrowDown; + Uint16 Enter; + Uint16 Menu; + Uint16 EngineStartStop; + Uint16 Emergency; + Uint16 BattleMode; +} CKeyList; + +typedef struct ClassKeyOperValue +{ + Uint16 uiKeyWaitCount; + Uint16 uiPreviousKey; + Uint16 uiKeyWait; + CKeyList KeyList; +} CKeyOperValue; + +extern CAdcCalcValue Adc_EngineHeater_V; +extern CAdcCalcValue Adc_GlowPlug_V; +extern CAdcCalcValue Adc_Solenoid_V; +extern CAdcCalcValue Adc_FuelPump_V; +extern CAdcCalcValue Adc_CoolantPump_V; +extern CAdcCalcValue Adc_Fan1_V; +extern CAdcCalcValue Adc_Fan2_V; + +extern CAdcCalcValue Adc_EngineHeater_I; +extern CAdcCalcValue Adc_GlowPlug_I; +extern CAdcCalcValue Adc_Solenoid_I; +extern CAdcCalcValue Adc_FuelPump_I; +extern CAdcCalcValue Adc_CoolantPump_I; +extern CAdcCalcValue Adc_Fan1_I; +extern CAdcCalcValue Adc_Fan2_I; + +extern CAdcOperValue AdcOperValue; +extern CKeyOperValue KeyOperValue; + +extern Uint32 ulDcuTotalAlarm; +extern Uint32 ulGcuTotalAlarm; +extern Uint32 ulEcuTotalAlarm; + +interrupt void CAdcInterrupt(void); +void CAlarmProcedure(void); +void CInitAdc(void); +void CKeyCheckProcedure(void); +void CKeyWaitCount(void); +void CDisplayAlarmPopup(void); + +#endif /* SOURCE_STATE_H_ */ diff --git a/Source/.staticdata/K2DCU/fs/fs_hash_map.json b/Source/.staticdata/K2DCU/fs/fs_hash_map.json new file mode 100644 index 0000000..4e1da2b --- /dev/null +++ b/Source/.staticdata/K2DCU/fs/fs_hash_map.json @@ -0,0 +1,282 @@ +{ + "C:/TI/C2000/C2000WARE_4_03_00_00/DEVICE_SUPPORT/F2833X/HEADERS/INCLUDE/DSP2833X_XINTF.H": [ + "9a0ce54b7ac8c23b398b7f623c6ec79f_", + false, + true, + "ebb2e298", + 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N 입니다.\n\nCLEAN_MODE=N\n\n;UTF-8로 인코딩된 파일도 인스펙션이 가능하도록 설정하는 옵션입니다.\n\n; default 값은 N 입니다.\n\nAUTO_ENCODING_UTF8=N\n\n\n\n; 프로젝트 DB 에 대한 초기화 쿼리\n\nINIT_QUERY=PRAGMA mmap_size=2147418112;\n\n\n\n; 람다 코드를 CFG에 포함할지 여부입니다. \n\n; 초기 값은 'N' 입니다.\n\nDISABLE_LAMBDA_CFG=N\n\n\n\n\n\n; 멀티 쓰레드 환경에서 refined 디렉토리를 유일하게 생성\n\n; 초기 값은 'Y' 입니다.\n\nMAKE_UNIQUE_REFINED_DIR=Y\n\n;\n\n;-------------------------------------------------------------------------\n\n;Violation 테이블에 violation 삽입 전에 인덱싱을 삭제하고 삽입 후에 다시 인덱싱 할지를 결정합니다.\n\n;default 값은 Y 입니다.\n\n[CI]\n\nREINDEX_MODE=Y\n\n\n\n;\n\n;\n\n; DFA 의 설정입니다.\n\n;\n\n;-------------------------------------------------------------------------\n\n[DFA]\n\nDFA_ENABLE=Y\n\nSCFG_OUT=N\n\nLIMIT_ITER=N\n\nRESULT_OUT=N\n\nITER_OUT=N\n\nTRANSFER_OUT=N\n\nFYCYC_ITER=40\n\n;\n\n;\n\n; Abstract Interpreter 설정\n\n;-------------------------------------------------------------------------\n\n[ABSINT]\n\n; ENABLE WHEN CI\n\nABSINT_ENABLE=Y\n\n; MUST | MAY\n\nABSINT_STRATEGY=MUST\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; ExtendedDeclarations를 db에 저장할지 결정합니다.\n\n; db에 저장된 정보는 linking time에 사용됩니다.\n\n; default 값은 Y 입니다(Y or N).\n\n; \n\n;-------------------------------------------------------------------------\n\n[ExtendedDeclaration]\n\nSAVE_TO_PROJECT_REPOSITORY=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; Report 시에 매크로 또는 시스템 매크로를 제외할 지 결정합니다.\n\n; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE 이 옵션으로 가능합니다.\n\n; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\\.h\n\n; default 값은 SKIP_SYSTEM_MACRO 입니다.\n\n; \n\n;-------------------------------------------------------------------------\n\n[REPORT]\n\nMACRO_SKIP_MODE=SKIP_SYSTEM_MACRO\n\n\n\n;-------------------------------------------------------------------------\n\n; 전처리 과정과 파싱 과정이 동시에 수행되는 경우,\n\n; 전처리 파일을 생성할지 여부.\n\n; 전처리 과정을 따로 수행하는 경우 이 key와 무관하게 항상 생성함.\n\n; default 값은 Y이고, 특별한 경우(용량 문제 등)가 아닌 이상 항상 생성함.\n\n; 이 key가 없는 경우에도 Y로 동작함.\n\nGEN_PP_OUTPUT=Y\n\n\n\n;-------------------------------------------------------------------------\n\n;\n\n; 아래는 FunctionUnit 들에 대해 옵션들입니다.\n\n; 특별한 경우가 아니라면 아래의 옵션들은 전문가의 손길이 필요합니다^^.\n\n; \n\n; \n\n;-------------------------------------------------------------------------\n\n[FunctionMapBuilder]\n\nSYMBOL_MAPPER=default\n\n;SYMBOL_MAPPER=physical\n\n; default \n\n; physical (헤더 파일내 static 함수를 물리적 파일 관점에서 보고, Translation Unit 이 달라도 동일한 것으로 처리)\n\n\n\n\n\n;-------------------------------------------------------------------------\n\n[CFGWriter]\n\n; debugging purpose - 각 함수에 대한 GML 표현을 Working Directory 에 기록합니다. yEd 를 이용하여 볼 수 있습니다.\n\nGML_OUT=N\n\n\n\n;-------------------------------------------------------------------------\n\n[MetricGenerator]\n\n; FUNCR 을 물리적인 관점에서 추출할지 여부에 대한 설정입니다. 기본값 N\n\nPHYSICAL_FUNCR=N\n\n\n\n;-------------------------------------------------------------------------\n\n[TestValidator]\n\n; debugging purpose - 저장된 Database 레코드의 참조 무결성을 확인합니다.\n\nCHECK_ALL=N\n\nCHECK_FUNCTION_MAP=N\n\nCHECK_CFG=N\n\nCHECK_FUNCTION_INFO=N\n\nCHECK_TYPE_INFO=N\n\nCHECK_USE_DEF=N\n\nTYPE_INFO_GML_OUT=N\n\n;-------------------------------------------------------------------------\n\n[ANALYSIS]\n\n; RTE annoatation 설정입니다. 초기 값은 'Y' 입니다.\n\nANNOTATION=Y\n\n; psionic 엔진 수행 설정입니다. 초기 값은 'Y' 입니다.\n\nRUN_PSIONIC=Y\n\n; 분석기에서 type 이름을 짧게 납기는 옵션입니다.\n\nOPTIMIZE=Y\n\n; 시스템 코드를 제외한 사용자 코드만 변환하는 옵션입니다. 초기 값은 'N' 입니다.\n\nUSER_CODE_ONLY=N\n\n; CAL 전처리기를 사용해서 CAL 의 사이즈를 줄입니다.\n\nRUN_PREPROC=Y\n\n; 특정 라이브러리에 대한 Over-Approximation 을 적용합니다.\n\n; ';' 를 구분자로 여러항목을 입력할 수 있습니다.\n\nOVER_APPROXIMATION=std::vector\n\n;-------------------------------------------------------------------------\n\n[ASTFactory]\n\n; AST를 생성할 때 lambda를 unknown expression 으로 취급할지 여부\n\n; 초기 값은 'N' 입니다.\n\nENABLE_LAMBDA_AS_UNKNOWN=N\n\n\n\n;현재 IniLoader 에 버그가 있어 마지막 줄은 읽지 않습니다. 반드시 마지막줄에 공백라인을 추가해주시기 바랍니다.\n", + "psionic_ini": "; CODESCROLL STATIC(2023/04/14)\n\n\n\n; ===================================\n\n; ENGINE VERSION\n\n; ===================================\n\n; Specify one of semantic analysis engine versions(default: latest)\n\n; eg) 2.1, 2.2, 2.2.1, 2.2.2, ...\n\nPSIONIC_ENGINE_VERSION=latest\n\n\n\n; ===================================\n\n; REPORTING POLICY\n\n; ===================================\n\n; Report only defects with a confidence level of 50% or higher.\n\n;PSIONIC_MIN_SCORE=50\n\n\n\n; Rank strategy (default: 0)\n\n; - 1: new ranking strategy\n\n;PSIONIC_RANK_SYSTEM_VERSION=0\n\n\n\n; Whether to report unused function arguments (default: true)\n\nPSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N\n\n\n\n; Report only ranking n error (rank starts 1 to 5, default: 1)\n\n; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0\n\n;PSIONIC_REPORT_ILL_MALLOC_RANK=1\n\n\n\n; Report when malloc size over n (default: 65535)\n\n;PSIONIC_INVALID_MALLOC_SIZE=65535\n\n\n\n; __________________________________\n\n; LIMITATION HANDLING\n\n; Some source code features not considered in this analyzer,\n\n; how can I handle when reaching the limit.\n\n;\n\n; in Second\n\n; 60s * 60 = 1 hour(3600)\n\n; 1day(24hour) = 86400 sec\n\n; 6hour = 21600 sec\n\n; 12hour = 43200 sec\n\n;\n\n; (default: unlimited)\n\n; __________________________________\n\n;PSIONIC_TIMEOUT=86400\n\n;PSIONIC_TIMEOUT_MEMORY=21600\n\n;PSIONIC_TIMEOUT_VALUE=21600\n\n;PSIONIC_MAX_MEMORY=20480\n\n\n\n; ===================================\n\n; TUNING ANALYSIS POWER\n\n; DO NOT MODIFY BELOW WITHOUT EXPERTS\n\n; IT WAS WELL TUNED FOR VARIOUS CODES\n\n; ===================================\n\n;PSIONIC_ENABLE_ROBUST=true\n\n;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200\n\n\n\n; __________________________________\n\n; Common Scalability\n\n; __________________________________\n\n;PSIONIC_CLUSTER_MAX_SIZE=999999999\n\n;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true\n\n;PSIONIC_CLUSTER_COUNT=20\n\n;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true\n\n\n\n; __________________________________\n\n; Value Analysis Precision\n\n; >> Default(Always Widening)\n\n; __________________________________\n\n;PSIONIC_WIDENING_LIMIT=0\n\n;PSIONIC_NARROWING_LIMIT=5\n\n;PSIONIC_VALUE_MAX_VISIT=1000\n\n;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1\n\n\n\n; Collect relations only directed relation in expression (less precise)\n\n;PSIONIC_ENABLE_VAR_CLUSTER=false\n\n\n\n; The main trade-off for precision and speed\n\n; 1, interval analysis (default)\n\n; 2, pentagon analysis\n\n; 3, octagon analysis\n\n;PSIONIC_ANALYSIS_POWER=1\n\n\n\n\n\n;ENABLE_RESIZE_CHAR_ARRAY=true\n\n\n\n; __________________________________\n\n; FixPoint Strategy for a Memory\n\n; Analysis (WTO, Worklist)\n\n; >> Default(Worklist)\n\n; __________________________________\n\n;PSIONIC_WITH_MEM_WTO=false\n\n\n\n; __________________________________\n\n; Memory Analysis Precision\n\n; __________________________________\n\n;PSIONIC_MEM_MAX_VISIT=10\n\n;PSIONIC_MEM_MAX_STATE=2048\n\n\n\n\n\n; __________________________________\n\n; Dataflow Analysis Precision\n\n; __________________________________\n\n;PSIONIC_DATAFLOW_MAX_VISIT=100000\n\n\n\n\n\n; __________________________________\n\n; Memory Analysis Scalability\n\n; __________________________________\n\n;PSIONIC_MEM_CALLEE_BOUND=50\n\n\n\n\n\n;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false\n\n;\n\n;ENABLE_MEM_GLOBAL_POINTER_NULL=true\n\n;ENABLE_MEM_GLOBAL_ROBUSTNESS=true\n\n;\n\n;\n\n; __________________________________\n\n; Control Engine Runtime\n\n; __________________________________\n\n; Analysis specific target cluster only\n\n;PSIONIC_TARGET_CLUSTER=10\n\n;PSIONIC_EXCEPT_CLUSTER\n\n\n\n; Value Only = 3, Memory Only = 2, Enable All = 4\n\n;PSIONIC_RUN_LEVEL=4\n", + "spec": "[\n {\n NAME: Default\n COMMON_COMPILE_FLAG: -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\" -I \"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"\n SOURCES:\n [\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Comm.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Display.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: Oper.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: State.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n {\n SOURCE_FILE_HANDLER: file\n SEARCH_DIR: ${THIS}\n FILENAME: main.c\n COMPILE_FLAG: inherit\n BUILD_DIR: ${THIS}\n }\n ]\n }\n]", + "static-client": "{\n\n \"capture_setting\": {\n\n \"build_hooking\": false,\n\n \"prebuildCommandEncoding\": \"euc-kr\",\n\n \"preprocessor\": \"original\"\n\n },\n\n \"last_validation_time\": \"2026-01-13T00:04:02.857Z\",\n\n \"last_capture_time\": \"2026-04-02T08:37:05.176Z\"\n\n}" +} \ No newline at end of file diff --git a/Source/.staticdata/artifacts.zip b/Source/.staticdata/artifacts.zip new file mode 100644 index 0000000..10a35a7 Binary files /dev/null and b/Source/.staticdata/artifacts.zip differ diff --git a/Source/.staticdata/cstrace.json b/Source/.staticdata/cstrace.json new file mode 100644 index 0000000..f3a4b1b --- /dev/null +++ b/Source/.staticdata/cstrace.json @@ -0,0 +1,87 @@ +{ + "1": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Comm.1.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "2": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Display.2.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "3": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\Oper.3.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "4": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\State.4.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + }, + "5": { + "execve": [ + "gcc", + [ + "gcc", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\common\\include\"", + "-I", + "\"C:\\ti\\c2000\\C2000Ware_4_03_00_00\\device_support\\f2833x\\headers\\include\"", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.c", + "-c", + "-o", + "C:\\ti\\Project\\K2APU_DCU_v019\\Source\\main.5.o" + ], + "C:\\ti\\Project\\K2APU_DCU_v019\\Source" + ] + } +} \ No newline at end of file diff --git a/Source/.staticdata/error.json b/Source/.staticdata/error.json new file mode 100644 index 0000000..9e26dfe --- /dev/null +++ b/Source/.staticdata/error.json @@ -0,0 +1 @@ +{} \ No newline at end of file diff --git a/Source/.staticdata/exclude_project.json b/Source/.staticdata/exclude_project.json new file mode 100644 index 0000000..2dba8e4 --- /dev/null +++ b/Source/.staticdata/exclude_project.json @@ -0,0 +1,12 @@ +{ + "schemaVersion": "1.0", + "modules": [ + { + "name": "Default", + "linkFlags": "", + "linkType": "execute", + "sources": [], + "dependencies": [] + } + ] +} \ No newline at end of file diff --git a/Source/.staticdata/preinclude/gnu_preinclude.h b/Source/.staticdata/preinclude/gnu_preinclude.h new file mode 100644 index 0000000..e69de29 diff --git a/Source/.staticdata/preinclude/recent_preinclude_c.h b/Source/.staticdata/preinclude/recent_preinclude_c.h new file mode 100644 index 0000000..2d6e90f --- /dev/null +++ b/Source/.staticdata/preinclude/recent_preinclude_c.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/.staticdata/preinclude/recent_preinclude_cpp.h b/Source/.staticdata/preinclude/recent_preinclude_cpp.h new file mode 100644 index 0000000..54df4a0 --- /dev/null +++ b/Source/.staticdata/preinclude/recent_preinclude_cpp.h @@ -0,0 +1,2 @@ +extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_cpp; +extern unsigned int codescroll_built_in_line_macro; diff --git a/Source/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf b/Source/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf new file mode 100644 index 0000000..dd05b14 --- /dev/null +++ b/Source/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf @@ -0,0 +1,112 @@ +[ + { + "language": "c", + "compiler": "TI C2000 6.2", + "linker": "not-used", + "archive": "not-used", + "conf": [ + "cs_builtin_declaration=", + "cs_ignore_single_keyword=far", + "cs_ignore_single_keyword=__far", + "cs_ignore_single_keyword=cregister", + "cs_ignore_single_keyword=interrupt", + "cs_ignore_single_keyword=__interrupt", + "cs_paren_asm=__asm", + "cs_paren_asm=asm", + "cs_define_macro_value=__signed_chars__;1", + "cs_define_macro_value=__DATE__;", + "cs_define_macro_value=__TIME__;", + "cs_define_macro_value=__STDC__;1", + "cs_define_macro_value=__STDC_VERSION__;199409L", + "cs_define_macro_value=__edg_front_end__;1", + "cs_define_macro_value=__EDG_VERSION__;404", + "cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long", + "cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long", + "cs_define_macro_value=__TI_COMPILER_VERSION__;6002000", + "cs_define_macro_value=__COMPILER_VERSION__;6002000", + "cs_define_macro_value=__TMS320C2000__;1", + "cs_define_macro_value=_TMS320C2000;1", + "cs_define_macro_value=__TMS320C28XX__;1", + "cs_define_macro_value=_TMS320C28XX;1", + "cs_define_macro_value=__TMS320C28X__;1", + "cs_define_macro_value=_TMS320C28X;1", + "cs_define_macro_value=__TMS320C28XX_FPU32__;1", + "cs_define_macro_value=__LARGE_MODEL__;1", + "cs_define_macro_value=__SIZE_T_TYPE__;unsigned long", + "cs_define_macro_value=__PTRDIFF_T_TYPE__;long", + "cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int", + "cs_define_macro_value=__little_endian__;1", + "cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1", + "cs_define_macro_value=__TI_WCHAR_T_BITS__;16", + "cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0", + "cs_define_macro_value=__TI_STRICT_FP_MODE__;1", + "cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1", + "cs_set_type_size=int;2", + "cs_set_type_size=long;4", + "cs_set_type_size=pointer;2", + "cs_set_type_size=float;4", + "cs_set_type_size=double;4", + "cs_plain_char=signed", + "cs_plain_bit_field=unsigned", + "cs_for_init_scope=outer", + "cs_using_std=disable", + "gnu_version=40702" + ], + "include": [] + }, + { + "language": "cpp", + "compiler": "TI C2000 6.2", + "linker": "not-used", + "archive": "not-used", + "conf": [ + "cs_builtin_declaration=", + "cs_ignore_single_keyword=far", + "cs_ignore_single_keyword=__far", + "cs_ignore_single_keyword=cregister", + "cs_ignore_single_keyword=interrupt", + "cs_ignore_single_keyword=__interrupt", + "cs_paren_asm=__asm", + "cs_paren_asm=asm", + "cs_define_macro_value=__signed_chars__;1", + "cs_define_macro_value=__DATE__;", + "cs_define_macro_value=__TIME__;", + "cs_define_macro_value=__STDC__;1", + "cs_define_macro_value=__STDC_VERSION__;199409L", + "cs_define_macro_value=__edg_front_end__;1", + "cs_define_macro_value=__EDG_VERSION__;404", + "cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long", + "cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long", + "cs_define_macro_value=__TI_COMPILER_VERSION__;6002000", + "cs_define_macro_value=__COMPILER_VERSION__;6002000", + "cs_define_macro_value=__TMS320C2000__;1", + "cs_define_macro_value=_TMS320C2000;1", + "cs_define_macro_value=__TMS320C28XX__;1", + "cs_define_macro_value=_TMS320C28XX;1", + "cs_define_macro_value=__TMS320C28X__;1", + "cs_define_macro_value=_TMS320C28X;1", + "cs_define_macro_value=__TMS320C28XX_FPU32__;1", + "cs_define_macro_value=__LARGE_MODEL__;1", + "cs_define_macro_value=__SIZE_T_TYPE__;unsigned long", + "cs_define_macro_value=__PTRDIFF_T_TYPE__;long", + "cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int", + "cs_define_macro_value=__little_endian__;1", + "cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1", + "cs_define_macro_value=__TI_WCHAR_T_BITS__;16", + "cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0", + "cs_define_macro_value=__TI_STRICT_FP_MODE__;1", + "cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1", + "cs_set_type_size=int;2", + "cs_set_type_size=long;4", + "cs_set_type_size=pointer;2", + "cs_set_type_size=float;4", + "cs_set_type_size=double;4", + "cs_plain_char=signed", + "cs_plain_bit_field=unsigned", + "cs_for_init_scope=outer", + "cs_using_std=disable", + "gnu_version=40702" + ], + "include": [] + } +] \ No newline at end of file diff --git a/Source/ci.ini b/Source/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/Source/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/Source/psionic.ini b/Source/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/Source/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/Source/static-client.json b/Source/static-client.json new file mode 100644 index 0000000..9fb15e4 --- /dev/null +++ b/Source/static-client.json @@ -0,0 +1,9 @@ +{ + "capture_setting": { + "build_hooking": false, + "prebuildCommandEncoding": "euc-kr", + "preprocessor": "original" + }, + "last_validation_time": "2026-01-13T00:04:02.857Z", + "last_capture_time": "2026-04-02T08:37:05.176Z" +} \ No newline at end of file diff --git a/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf b/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf new file mode 100644 index 0000000..dd05b14 --- /dev/null +++ b/TI_C2000_6.2_TMS320F28x_Host_CCPP.sconf @@ -0,0 +1,112 @@ +[ + { + "language": "c", + "compiler": "TI C2000 6.2", + "linker": "not-used", + "archive": "not-used", + "conf": [ + "cs_builtin_declaration=", + "cs_ignore_single_keyword=far", + "cs_ignore_single_keyword=__far", + "cs_ignore_single_keyword=cregister", + "cs_ignore_single_keyword=interrupt", + "cs_ignore_single_keyword=__interrupt", + "cs_paren_asm=__asm", + "cs_paren_asm=asm", + "cs_define_macro_value=__signed_chars__;1", + "cs_define_macro_value=__DATE__;", + "cs_define_macro_value=__TIME__;", + "cs_define_macro_value=__STDC__;1", + "cs_define_macro_value=__STDC_VERSION__;199409L", + "cs_define_macro_value=__edg_front_end__;1", + "cs_define_macro_value=__EDG_VERSION__;404", + "cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long", + "cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long", + "cs_define_macro_value=__TI_COMPILER_VERSION__;6002000", + "cs_define_macro_value=__COMPILER_VERSION__;6002000", + "cs_define_macro_value=__TMS320C2000__;1", + "cs_define_macro_value=_TMS320C2000;1", + "cs_define_macro_value=__TMS320C28XX__;1", + "cs_define_macro_value=_TMS320C28XX;1", + "cs_define_macro_value=__TMS320C28X__;1", + "cs_define_macro_value=_TMS320C28X;1", + "cs_define_macro_value=__TMS320C28XX_FPU32__;1", + "cs_define_macro_value=__LARGE_MODEL__;1", + "cs_define_macro_value=__SIZE_T_TYPE__;unsigned long", + "cs_define_macro_value=__PTRDIFF_T_TYPE__;long", + "cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int", + "cs_define_macro_value=__little_endian__;1", + "cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1", + "cs_define_macro_value=__TI_WCHAR_T_BITS__;16", + "cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0", + "cs_define_macro_value=__TI_STRICT_FP_MODE__;1", + "cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1", + "cs_set_type_size=int;2", + "cs_set_type_size=long;4", + "cs_set_type_size=pointer;2", + "cs_set_type_size=float;4", + "cs_set_type_size=double;4", + "cs_plain_char=signed", + "cs_plain_bit_field=unsigned", + "cs_for_init_scope=outer", + "cs_using_std=disable", + "gnu_version=40702" + ], + "include": [] + }, + { + "language": "cpp", + "compiler": "TI C2000 6.2", + "linker": "not-used", + "archive": "not-used", + "conf": [ + "cs_builtin_declaration=", + "cs_ignore_single_keyword=far", + "cs_ignore_single_keyword=__far", + "cs_ignore_single_keyword=cregister", + "cs_ignore_single_keyword=interrupt", + "cs_ignore_single_keyword=__interrupt", + "cs_paren_asm=__asm", + "cs_paren_asm=asm", + "cs_define_macro_value=__signed_chars__;1", + "cs_define_macro_value=__DATE__;", + "cs_define_macro_value=__TIME__;", + "cs_define_macro_value=__STDC__;1", + "cs_define_macro_value=__STDC_VERSION__;199409L", + "cs_define_macro_value=__edg_front_end__;1", + "cs_define_macro_value=__EDG_VERSION__;404", + "cs_define_macro_value=__EDG_SIZE_TYPE__;unsigned long", + "cs_define_macro_value=__EDG_PTRDIFF_TYPE__;long", + "cs_define_macro_value=__TI_COMPILER_VERSION__;6002000", + "cs_define_macro_value=__COMPILER_VERSION__;6002000", + "cs_define_macro_value=__TMS320C2000__;1", + "cs_define_macro_value=_TMS320C2000;1", + "cs_define_macro_value=__TMS320C28XX__;1", + "cs_define_macro_value=_TMS320C28XX;1", + "cs_define_macro_value=__TMS320C28X__;1", + "cs_define_macro_value=_TMS320C28X;1", + "cs_define_macro_value=__TMS320C28XX_FPU32__;1", + "cs_define_macro_value=__LARGE_MODEL__;1", + "cs_define_macro_value=__SIZE_T_TYPE__;unsigned long", + "cs_define_macro_value=__PTRDIFF_T_TYPE__;long", + "cs_define_macro_value=__WCHAR_T_TYPE__;unsigned int", + "cs_define_macro_value=__little_endian__;1", + "cs_define_macro_value=__TI_STRICT_ANSI_MODE__;1", + "cs_define_macro_value=__TI_WCHAR_T_BITS__;16", + "cs_define_macro_value=__TI_GNU_ATTRIBUTE_SUPPORT__;0", + "cs_define_macro_value=__TI_STRICT_FP_MODE__;1", + "cs_define_macro_value=_OPTIMIZE_FOR_SPACE;1", + "cs_set_type_size=int;2", + "cs_set_type_size=long;4", + "cs_set_type_size=pointer;2", + "cs_set_type_size=float;4", + "cs_set_type_size=double;4", + "cs_plain_char=signed", + "cs_plain_bit_field=unsigned", + "cs_for_init_scope=outer", + "cs_using_std=disable", + "gnu_version=40702" + ], + "include": [] + } +] \ No newline at end of file diff --git a/ci.ini b/ci.ini new file mode 100644 index 0000000..fb0274a --- /dev/null +++ b/ci.ini @@ -0,0 +1,140 @@ +; +; +; PA Դϴ. +; +;------------------------------------------------------------------------- +[PA] +; PA ÿ ̺ ڵ带 PA ˴ϴ. +; default N Դϴ. +CLEAN_MODE=N +;UTF-8 ڵ ϵ ν ϵ ϴ ɼԴϴ. +; default N Դϴ. +AUTO_ENCODING_UTF8=N + +; Ʈ DB ʱȭ +INIT_QUERY=PRAGMA mmap_size=2147418112; + +; ڵ带 CFG Դϴ. +; ʱ 'N' Դϴ. +DISABLE_LAMBDA_CFG=N + + +; Ƽ ȯ濡 refined 丮 ϰ +; ʱ 'Y' Դϴ. +MAKE_UNIQUE_REFINED_DIR=Y +; +;------------------------------------------------------------------------- +;Violation ̺ violation ε ϰ Ŀ ٽ ε մϴ. +;default Y Դϴ. +[CI] +REINDEX_MODE=Y + +; +; +; DFA Դϴ. +; +;------------------------------------------------------------------------- +[DFA] +DFA_ENABLE=Y +SCFG_OUT=N +LIMIT_ITER=N +RESULT_OUT=N +ITER_OUT=N +TRANSFER_OUT=N +FYCYC_ITER=40 +; +; +; Abstract Interpreter +;------------------------------------------------------------------------- +[ABSINT] +; ENABLE WHEN CI +ABSINT_ENABLE=Y +; MUST | MAY +ABSINT_STRATEGY=MUST + + +;------------------------------------------------------------------------- +; +; ExtendedDeclarations db մϴ. +; db linking time ˴ϴ. +; default Y Դϴ(Y or N). +; +;------------------------------------------------------------------------- +[ExtendedDeclaration] +SAVE_TO_PROJECT_REPOSITORY=Y + +;------------------------------------------------------------------------- +; +; Report ÿ ũ Ǵ ý ũθ մϴ. +; SKIP_SYSTEM_MACRO, SKIP_ALL_MACRO, SKIP_NONE, SKIP_DEFINED_IN_FILE ɼ մϴ. +; MACRO_SKIP_MODE=SKIP_DEFINED_IN_FILE:.*_Math\.h +; default SKIP_SYSTEM_MACRO Դϴ. +; +;------------------------------------------------------------------------- +[REPORT] +MACRO_SKIP_MODE=SKIP_SYSTEM_MACRO + +;------------------------------------------------------------------------- +; ó Ľ ÿ Ǵ , +; ó . +; ó ϴ key ϰ ׻ . +; default Y̰, Ư (뷮 ) ƴ ̻ ׻ . +; key 쿡 Y . +GEN_PP_OUTPUT=Y + +;------------------------------------------------------------------------- +; +; Ʒ FunctionUnit 鿡 ɼǵԴϴ. +; Ư 찡 ƴ϶ Ʒ ɼǵ ձ ʿմϴ^^. +; +; +;------------------------------------------------------------------------- +[FunctionMapBuilder] +SYMBOL_MAPPER=default +;SYMBOL_MAPPER=physical +; default +; physical ( ϳ static Լ , Translation Unit ޶ ó) + + +;------------------------------------------------------------------------- +[CFGWriter] +; debugging purpose - Լ GML ǥ Working Directory մϴ. yEd ̿Ͽ ֽϴ. +GML_OUT=N + +;------------------------------------------------------------------------- +[MetricGenerator] +; FUNCR ο Դϴ. ⺻ N +PHYSICAL_FUNCR=N + +;------------------------------------------------------------------------- +[TestValidator] +; debugging purpose - Database ڵ Ἲ Ȯմϴ. +CHECK_ALL=N +CHECK_FUNCTION_MAP=N +CHECK_CFG=N +CHECK_FUNCTION_INFO=N +CHECK_TYPE_INFO=N +CHECK_USE_DEF=N +TYPE_INFO_GML_OUT=N +;------------------------------------------------------------------------- +[ANALYSIS] +; RTE annoatation Դϴ. ʱ 'Y' Դϴ. +ANNOTATION=Y +; psionic Դϴ. ʱ 'Y' Դϴ. +RUN_PSIONIC=Y +; м⿡ type ̸ ª ɼԴϴ. +OPTIMIZE=Y +; ý ڵ带 ڵ常 ȯϴ ɼԴϴ. ʱ 'N' Դϴ. +USER_CODE_ONLY=N +; CAL ó⸦ ؼ CAL  Դϴ. +RUN_PREPROC=Y +; Ư ̺귯 Over-Approximation մϴ. +; ';' ڷ ׸ Է ֽϴ. +OVER_APPROXIMATION=std::vector +;------------------------------------------------------------------------- +[ASTFactory] +; AST lambda unknown expression +; ʱ 'N' Դϴ. +ENABLE_LAMBDA_AS_UNKNOWN=N + +; IniLoader װ ־ ʽϴ. ݵ ٿ ֽ߰ñ ٶϴ. diff --git a/psionic.ini b/psionic.ini new file mode 100644 index 0000000..27b16dc --- /dev/null +++ b/psionic.ini @@ -0,0 +1,125 @@ +; CODESCROLL STATIC(2023/04/14) + +; =================================== +; ENGINE VERSION +; =================================== +; Specify one of semantic analysis engine versions(default: latest) +; eg) 2.1, 2.2, 2.2.1, 2.2.2, ... +PSIONIC_ENGINE_VERSION=latest + +; =================================== +; REPORTING POLICY +; =================================== +; Report only defects with a confidence level of 50% or higher. +;PSIONIC_MIN_SCORE=50 + +; Rank strategy (default: 0) +; - 1: new ranking strategy +;PSIONIC_RANK_SYSTEM_VERSION=0 + +; Whether to report unused function arguments (default: true) +PSIONIC_REPORT_UNUSED_FORMAL_PARAMETER=N + +; Report only ranking n error (rank starts 1 to 5, default: 1) +; *notice* Ranking 3..5 only works when PSIONIC_MIN_SCORE is 0 +;PSIONIC_REPORT_ILL_MALLOC_RANK=1 + +; Report when malloc size over n (default: 65535) +;PSIONIC_INVALID_MALLOC_SIZE=65535 + +; __________________________________ +; LIMITATION HANDLING +; Some source code features not considered in this analyzer, +; how can I handle when reaching the limit. +; +; in Second +; 60s * 60 = 1 hour(3600) +; 1day(24hour) = 86400 sec +; 6hour = 21600 sec +; 12hour = 43200 sec +; +; (default: unlimited) +; __________________________________ +;PSIONIC_TIMEOUT=86400 +;PSIONIC_TIMEOUT_MEMORY=21600 +;PSIONIC_TIMEOUT_VALUE=21600 +;PSIONIC_MAX_MEMORY=20480 + +; =================================== +; TUNING ANALYSIS POWER +; DO NOT MODIFY BELOW WITHOUT EXPERTS +; IT WAS WELL TUNED FOR VARIOUS CODES +; =================================== +;PSIONIC_ENABLE_ROBUST=true +;PSIONIC_ANALYSIS_PROGRESS_INTERVAL=200 + +; __________________________________ +; Common Scalability +; __________________________________ +;PSIONIC_CLUSTER_MAX_SIZE=999999999 +;PSIONIC_CLUSTER_ONLY_HIGH_PORTION=true +;PSIONIC_CLUSTER_COUNT=20 +;PSIONIC_ENABLE_VIRTUAL_CALL_ANALYSIS=true + +; __________________________________ +; Value Analysis Precision +; >> Default(Always Widening) +; __________________________________ +;PSIONIC_WIDENING_LIMIT=0 +;PSIONIC_NARROWING_LIMIT=5 +;PSIONIC_VALUE_MAX_VISIT=1000 +;PSIONIC_CONTEXT_SENSITIVITY_BOUND=1 + +; Collect relations only directed relation in expression (less precise) +;PSIONIC_ENABLE_VAR_CLUSTER=false + +; The main trade-off for precision and speed +; 1, interval analysis (default) +; 2, pentagon analysis +; 3, octagon analysis +;PSIONIC_ANALYSIS_POWER=1 + + +;ENABLE_RESIZE_CHAR_ARRAY=true + +; __________________________________ +; FixPoint Strategy for a Memory +; Analysis (WTO, Worklist) +; >> Default(Worklist) +; __________________________________ +;PSIONIC_WITH_MEM_WTO=false + +; __________________________________ +; Memory Analysis Precision +; __________________________________ +;PSIONIC_MEM_MAX_VISIT=10 +;PSIONIC_MEM_MAX_STATE=2048 + + +; __________________________________ +; Dataflow Analysis Precision +; __________________________________ +;PSIONIC_DATAFLOW_MAX_VISIT=100000 + + +; __________________________________ +; Memory Analysis Scalability +; __________________________________ +;PSIONIC_MEM_CALLEE_BOUND=50 + + +;PSIONIC_ENABLE_MEM_GLOBAL_VAR=false +; +;ENABLE_MEM_GLOBAL_POINTER_NULL=true +;ENABLE_MEM_GLOBAL_ROBUSTNESS=true +; +; +; __________________________________ +; Control Engine Runtime +; __________________________________ +; Analysis specific target cluster only +;PSIONIC_TARGET_CLUSTER=10 +;PSIONIC_EXCEPT_CLUSTER + +; Value Only = 3, Memory Only = 2, Enable All = 4 +;PSIONIC_RUN_LEVEL=4 diff --git a/static-client.json b/static-client.json new file mode 100644 index 0000000..bf6b751 --- /dev/null +++ b/static-client.json @@ -0,0 +1,9 @@ +{ + "capture_setting": { + "build_hooking": false, + "prebuildCommandEncoding": "euc-kr", + "preprocessor": "original" + }, + "last_validation_time": "2026-01-13T00:04:02.857Z", + "last_capture_time": "2026-01-13T00:06:33.760Z" +} \ No newline at end of file diff --git a/targetConfigs/TMS320F28335.ccxml b/targetConfigs/TMS320F28335.ccxml new file mode 100644 index 0000000..d3c5eea --- /dev/null +++ b/targetConfigs/TMS320F28335.ccxml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targetConfigs/readme.txt b/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file