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HosuKim
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// TI File $Revision: /main/4 $
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// Checkin $Date: July 27, 2009 13:57:25 $
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//###########################################################################
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//
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// FILE: DSP2833x_Xintf.h
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//
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// TITLE: DSP2833x Device External Interface Register Definitions.
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//
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//###########################################################################
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// $TI Release: 2833x/2823x Header Files V1.32 $
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// $Release Date: June 28, 2010 $
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// $Copyright:
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// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef DSP2833x_XINTF_H
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#define DSP2833x_XINTF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// XINTF timing register bit definitions
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//
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struct XTIMING_BITS { // bits description
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Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
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Uint16 XWRACTIVE:3; // 4:2 Write access active timing
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Uint16 XWRLEAD:2; // 6:5 Write access lead timing
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Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
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Uint16 XRDACTIVE:3; // 11:9 Read access active timing
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Uint16 XRDLEAD:2; // 13:12 Read access lead timing
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Uint16 USEREADY:1; // 14 Extend access using HW waitstates
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Uint16 READYMODE:1; // 15 Ready mode
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Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
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Uint16 rsvd1:4; // 21:18 reserved
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Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
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Uint16 rsvd3:9; // 31:23 reserved
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};
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union XTIMING_REG {
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Uint32 all;
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struct XTIMING_BITS bit;
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};
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//
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// XINTF control register bit definitions
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//
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struct XINTCNF2_BITS { // bits description
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Uint16 WRBUFF:2; // 1:0 Write buffer depth
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Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
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Uint16 CLKOFF:1; // 3 Disable XCLKOUT
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Uint16 rsvd1:2; // 5:4 reserved
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Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
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Uint16 rsvd2:1; // 8 reserved
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Uint16 HOLD:1; // 9 Hold enable/disable
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Uint16 HOLDS:1; // 10 Current state of HOLDn input
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Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
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Uint16 rsvd3:4; // 15:12 reserved
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Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
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Uint16 rsvd4:13; // 31:19 reserved
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};
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union XINTCNF2_REG {
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Uint32 all;
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struct XINTCNF2_BITS bit;
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};
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//
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// XINTF bank switching register bit definitions
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//
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struct XBANK_BITS { // bits description
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Uint16 BANK:3; // 2:0 Zone for which banking is enabled
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Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
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Uint16 rsvd:10; // 15:6 reserved
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};
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union XBANK_REG {
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Uint16 all;
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struct XBANK_BITS bit;
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};
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struct XRESET_BITS {
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Uint16 XHARDRESET:1;
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Uint16 rsvd1:15;
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};
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union XRESET_REG {
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Uint16 all;
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struct XRESET_BITS bit;
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};
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//
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// XINTF Register File
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//
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struct XINTF_REGS {
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union XTIMING_REG XTIMING0;
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Uint32 rsvd1[5];
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union XTIMING_REG XTIMING6;
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union XTIMING_REG XTIMING7;
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Uint32 rsvd2[2];
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union XINTCNF2_REG XINTCNF2;
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Uint32 rsvd3;
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union XBANK_REG XBANK;
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Uint16 rsvd4;
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Uint16 XREVISION;
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Uint16 rsvd5[2];
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union XRESET_REG XRESET;
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};
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//
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// XINTF External References & Function Declarations
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//
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extern volatile struct XINTF_REGS XintfRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_XINTF_H definition
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//
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// End of File
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//
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