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HosuKim
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#ifndef SOURCE_STATE_H_
#define SOURCE_STATE_H_
#define ALARM_UNDER_CHECK (0U)
#define ALARM_OVER_CHECK (1U)
#define PI2 (6.283185f)
#define ADC_FREQ (10000.0f) // 10kHz = 0.0001sec
#define ADC_LPF_COFF_TEMP (0.2f)
#define ADC_LPF_GAIN_TEMP (0.00012566f) //(PI2 * ADC_LPF_COFF_TEMP * (1.0f / ADC_FREQ))
#define ADC_LPF_COFF (30.0f)
#define ADC_LPF_GAIN (0.01884955f) //(PI2 * ADC_LPF_COFF * (1.0f / ADC_FREQ))
#define LONG_KEY_TIME (1000UL)
#define KEY_POWER_MASK (0x00000001UL)
#define COMM_TIME_OUT_COUNT (30U)
enum
{
IDX_ADC_ENGINE_HEATER_I = 0U, // 0
IDX_ADC_GLOW_PLUG_I, // 1
IDX_ADC_SOLENOID_I, // 2
IDX_ADC_FUEL_PUMP_I, // 3
IDX_ADC_COOLANT_PUMP_I, // 4
IDX_ADC_FAN1_I, // 5
IDX_ADC_FAN2_I, // 6
IDX_ADC_MAX
};
typedef enum
{
IDX_FAULT_CAR_COMM = 0U, // 0
IDX_FAULT_GCU_COMM, // 1
IDX_FAULT_ECU_COMM, // 2
IDX_FAULT_RPM_ERR, // 3
IDX_FAULT_ENGINE_HEAT_OC, // 4
IDX_FAULT_GLOW_PLUG_OC, // 5
IDX_FAULT_SOLENOID_OC, // 6
IDX_FAULT_FUEL_PUMP_OC, // 7
IDX_FAULT_COOLANT_PUMP_OC, // 8
IDX_FAULT_FAN1_OC, // 9
IDX_FAULT_FAN2_OC, // 10
IDX_FAULT_ENGINE_HEAT_LINE_OPEN, // 11
IDX_FAULT_GLOW_PLUG_LINE_OPEN, // 12
IDX_FAULT_SOLENOID_LINE_OPEN, // 13
IDX_FAULT_FUEL_PUMP_LINE_OPEN, // 14
IDX_FAULT_COOLANT_PUMP_LINE_OPEN, // 15
IDX_FAULT_FAN1_LINE_OPEN, // 16
IDX_FAULT_FAN2_LINE_OPEN, // 17
IDX_FAULT_MAX
} ALARM_TYPE;
typedef struct ClassAdcOperValue
{
Uint16 uiAdcOffsetIndex;
Uint16 uiOffsetAdjustStart;
} CAdcOperValue;
typedef struct ClassAdcCalcValue
{
float32 fOffset;
float32 fLpfValue;
float32 fSampledValue;
float32 fGain;
float32 fSampledSum;
float32 fTempAdcOffset;
int16 iAdcValue;
Uint16 uiSamplingCount;
} CAdcCalcValue;
typedef union ClassFaultBitValue
{
Uint32 ulTotal;
struct
{
Uint16 CarCommTimeout : 1;
Uint16 GcuCommTimeout : 1;
Uint16 EcuCommTimeOut : 1;
Uint16 RpmError : 1;
Uint16 EngineHeatOverCurrent : 1;
Uint16 GlowPlugOverCurrent : 1;
Uint16 SolenoidOverCurrent : 1;
Uint16 FuelPumpOverCurrent : 1;
Uint16 CoolantPumpOverCurrent : 1;
Uint16 Fan1OverCurrent : 1;
Uint16 Fan2OverCurrent : 1;
Uint16 EngineHeatOpen : 1;
Uint16 GlowPlugOpen : 1;
Uint16 SolenoidOpen : 1;
Uint16 FuelPumpOpen : 1;
Uint16 CoolantPumpOpen : 1;
Uint16 Fan1Open : 1;
Uint16 Fan2Open : 1;
Uint16 rsvd_padding1 : 6;
Uint16 rsvd_padding2 : 8;
} bit;
} CFaultBitValue;
typedef struct ClassWarningOperValue
{
float32 fCheckLimit; // 경고 한계 값
Uint16 uiWarning; // 0: 정상, 1: 경고 발생 중
Uint16 uiDetectCount; // 경고 검출 카운터
Uint16 uiReleaseCount; // 경고 해제 카운터
Uint16 uiCheckTime;
} CWarningOperValue;
typedef struct ClassAlarmOperValue
{
float32 fCheckLimit;
float32 fFaultValue;
Uint16 uiCheck;
Uint16 uiCheckCount;
Uint16 uiCheckTime;
} CAlarmOperValue;
typedef enum
{
IDX_KEY_MAIN_POWER = 0U,
IDX_KEY_ARR_UP,
IDX_KEY_ARR_DOWN,
IDX_KEY_ENTER,
IDX_KEY_MENU,
IDX_KEY_ENG_START_STOP,
IDX_KEY_EMERGENCY,
IDX_KEY_MAX
} EKeyIndex;
typedef struct ClassKeyHandler
{
EKeyIndex eKey;
void (*pAction) (void);
} CKeyHandler;
typedef union ClassKeyList
{
Uint16 uiTotal;
struct
{
Uint16 MainPower : 1;
Uint16 ArrowUp : 1;
Uint16 ArrowDown : 1;
Uint16 Enter : 1;
Uint16 Menu : 1;
Uint16 EngineStartStop : 1;
Uint16 Emergency : 1;
} bit;
} CKeyList;
typedef struct ClassKeyOperValue
{
Uint16 uiKeyWaitCount;
Uint16 uiPreviousKey;
Uint16 uiKeyWait;
CKeyList KeyList;
} CKeyOperValue;
interrupt void CAdcInterrupt(void);
void CAlarmProcedure(void);
void CInitAdc(void);
void CKeyCheckProcedure(void);
void CKeyWaitCount(void);
void CDisplayAlarmPopup(void);
extern CAdcCalcValue Adc_EngineHeater_I;
extern CAdcCalcValue Adc_GlowPlug_I;
extern CAdcCalcValue Adc_Solenoid_I;
extern CAdcCalcValue Adc_FuelPump_I;
extern CAdcCalcValue Adc_CoolantPump_I;
extern CAdcCalcValue Adc_Fan1_I;
extern CAdcCalcValue Adc_Fan2_I;
extern CAdcOperValue AdcOperValue;
extern CFaultBitValue FaultBitValue;
extern CKeyOperValue KeyOperValue;
#endif /* SOURCE_STATE_H_ */

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:39 $
//###########################################################################
//
// FILE: DSP2833x_EPwm_defines.h
//
// TITLE: #defines used in ePWM examples examples
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_EPWM_DEFINES_H
#define DSP2833x_EPWM_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// TBCTL (Time-Base Control)
//
// CTRMODE bits
//
#define TB_COUNT_UP 0x0
#define TB_COUNT_DOWN 0x1
#define TB_COUNT_UPDOWN 0x2
#define TB_FREEZE 0x3
//
// PHSEN bit
//
#define TB_DISABLE 0x0
#define TB_ENABLE 0x1
//
// PRDLD bit
//
#define TB_SHADOW 0x0
#define TB_IMMEDIATE 0x1
//
// SYNCOSEL bits
//
#define TB_SYNC_IN 0x0
#define TB_CTR_ZERO 0x1
#define TB_CTR_CMPB 0x2
#define TB_SYNC_DISABLE 0x3
//
// HSPCLKDIV and CLKDIV bits
//
#define TB_DIV1 0x0
#define TB_DIV2 0x1
#define TB_DIV4 0x2
//
// PHSDIR bit
//
#define TB_DOWN 0x0
#define TB_UP 0x1
//
// CMPCTL (Compare Control)
//
// LOADAMODE and LOADBMODE bits
//
#define CC_CTR_ZERO 0x0
#define CC_CTR_PRD 0x1
#define CC_CTR_ZERO_PRD 0x2
#define CC_LD_DISABLE 0x3
//
// SHDWAMODE and SHDWBMODE bits
//
#define CC_SHADOW 0x0
#define CC_IMMEDIATE 0x1
//
// AQCTLA and AQCTLB (Action Qualifier Control)
//
// ZRO, PRD, CAU, CAD, CBU, CBD bits
//
#define AQ_NO_ACTION 0x0
#define AQ_CLEAR 0x1
#define AQ_SET 0x2
#define AQ_TOGGLE 0x3
//
// DBCTL (Dead-Band Control)
//
// OUT MODE bits
//
#define DB_DISABLE 0x0
#define DBB_ENABLE 0x1
#define DBA_ENABLE 0x2
#define DB_FULL_ENABLE 0x3
//
// POLSEL bits
//
#define DB_ACTV_HI 0x0
#define DB_ACTV_LOC 0x1
#define DB_ACTV_HIC 0x2
#define DB_ACTV_LO 0x3
//
// IN MODE
//
#define DBA_ALL 0x0
#define DBB_RED_DBA_FED 0x1
#define DBA_RED_DBB_FED 0x2
#define DBB_ALL 0x3
//
// CHPCTL (chopper control)
//
// CHPEN bit
//
#define CHP_DISABLE 0x0
#define CHP_ENABLE 0x1
//
// CHPFREQ bits
//
#define CHP_DIV1 0x0
#define CHP_DIV2 0x1
#define CHP_DIV3 0x2
#define CHP_DIV4 0x3
#define CHP_DIV5 0x4
#define CHP_DIV6 0x5
#define CHP_DIV7 0x6
#define CHP_DIV8 0x7
//
// CHPDUTY bits
//
#define CHP1_8TH 0x0
#define CHP2_8TH 0x1
#define CHP3_8TH 0x2
#define CHP4_8TH 0x3
#define CHP5_8TH 0x4
#define CHP6_8TH 0x5
#define CHP7_8TH 0x6
//
// TZSEL (Trip Zone Select)
//
// CBCn and OSHTn bits
//
#define TZ_DISABLE 0x0
#define TZ_ENABLE 0x1
//
// TZCTL (Trip Zone Control)
//
// TZA and TZB bits
//
#define TZ_HIZ 0x0
#define TZ_FORCE_HI 0x1
#define TZ_FORCE_LO 0x2
#define TZ_NO_CHANGE 0x3
//
// ETSEL (Event Trigger Select)
//
#define ET_CTR_ZERO 0x1
#define ET_CTR_PRD 0x2
#define ET_CTRU_CMPA 0x4
#define ET_CTRD_CMPA 0x5
#define ET_CTRU_CMPB 0x6
#define ET_CTRD_CMPB 0x7
//
// ETPS (Event Trigger Pre-scale)
//
// INTPRD, SOCAPRD, SOCBPRD bits
//
#define ET_DISABLE 0x0
#define ET_1ST 0x1
#define ET_2ND 0x2
#define ET_3RD 0x3
//
// HRPWM (High Resolution PWM)
//
// HRCNFG
//
#define HR_Disable 0x0
#define HR_REP 0x1
#define HR_FEP 0x2
#define HR_BEP 0x3
#define HR_CMP 0x0
#define HR_PHS 0x1
#define HR_CTR_ZERO 0x0
#define HR_CTR_PRD 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:13 $
//###########################################################################
//
// FILE: DSP2833x_EQep.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_EQEP_H
#define DSP2833x_EQEP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Capture decoder control register bit definitions
//
struct QDECCTL_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 QSP:1; // 5 QEPS input polarity
Uint16 QIP:1; // 6 QEPI input polarity
Uint16 QBP:1; // 7 QEPB input polarity
Uint16 QAP:1; // 8 QEPA input polarity
Uint16 IGATE:1; // 9 Index pulse gating option
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
Uint16 XCR:1; // 11 External clock rate
Uint16 SPSEL:1; // 12 Sync output pin select
Uint16 SOEN:1; // 13 Enable position compare sync
Uint16 QSRC:2; // 15:14 Position counter source
};
union QDECCTL_REG {
Uint16 all;
struct QDECCTL_BITS bit;
};
//
// QEP control register bit definitions
//
struct QEPCTL_BITS { // bits description
Uint16 WDE:1; // 0 QEP watchdog enable
Uint16 UTE:1; // 1 QEP unit timer enable
Uint16 QCLM:1; // 2 QEP capture latch mode
Uint16 QPEN:1; // 3 Quadrature position counter enable
Uint16 IEL:2; // 5:4 Index event latch
Uint16 SEL:1; // 6 Strobe event latch
Uint16 SWI:1; // 7 Software init position counter
Uint16 IEI:2; // 9:8 Index event init of position count
Uint16 SEI:2; // 11:10 Strobe event init
Uint16 PCRM:2; // 13:12 Position counter reset
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union QEPCTL_REG {
Uint16 all;
struct QEPCTL_BITS bit;
};
//
// Quadrature capture control register bit definitions
//
struct QCAPCTL_BITS { // bits description
Uint16 UPPS:4; // 3:0 Unit position pre-scale
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
Uint16 rsvd1:8; // 14:7 reserved
Uint16 CEN:1; // 15 Enable QEP capture
};
union QCAPCTL_REG {
Uint16 all;
struct QCAPCTL_BITS bit;
};
//
// Position compare control register bit definitions
//
struct QPOSCTL_BITS { // bits description
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
Uint16 PCE:1; // 12 Position compare enable/disable
Uint16 PCPOL:1; // 13 Polarity of sync output
Uint16 PCLOAD:1; // 14 Position compare of shadow load
Uint16 PCSHDW:1; // 15 Position compare shadow enable
};
union QPOSCTL_REG {
Uint16 all;
struct QPOSCTL_BITS bit;
};
//
// QEP interrupt control register bit definitions
//
struct QEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 QPE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QEINT_REG {
Uint16 all;
struct QEINT_BITS bit;
};
//
// QEP interrupt status register bit definitions
//
struct QFLG_BITS { // bits description
Uint16 INT:1; // 0 Global interrupt
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFLG_REG {
Uint16 all;
struct QFLG_BITS bit;
};
//
// QEP interrupt force register bit definitions
//
struct QFRC_BITS { // bits description
Uint16 reserved:1; // 0 Reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFRC_REG {
Uint16 all;
struct QFRC_BITS bit;
};
//
// V1.1 Added UPEVNT (bit 7) This reflects changes
// made as of F2833x Rev A devices
//
//
// QEP status register bit definitions
//
struct QEPSTS_BITS { // bits description
Uint16 PCEF:1; // 0 Position counter error
Uint16 FIMF:1; // 1 First index marker
Uint16 CDEF:1; // 2 Capture direction error
Uint16 COEF:1; // 3 Capture overflow error
Uint16 QDLF:1; // 4 QEP direction latch
Uint16 QDF:1; // 5 Quadrature direction
Uint16 FIDF:1; // 6 Direction on first index marker
Uint16 UPEVNT:1; // 7 Unit position event flag
Uint16 rsvd1:8; // 15:8 reserved
};
union QEPSTS_REG {
Uint16 all;
struct QEPSTS_BITS bit;
};
struct EQEP_REGS {
Uint32 QPOSCNT; // Position counter
Uint32 QPOSINIT; // Position counter init
Uint32 QPOSMAX; // Maximum position count
Uint32 QPOSCMP; // Position compare
Uint32 QPOSILAT; // Index position latch
Uint32 QPOSSLAT; // Strobe position latch
Uint32 QPOSLAT; // Position latch
Uint32 QUTMR; // Unit timer
Uint32 QUPRD; // Unit period
Uint16 QWDTMR; // QEP watchdog timer
Uint16 QWDPRD; // QEP watchdog period
union QDECCTL_REG QDECCTL; // Quadrature decoder control
union QEPCTL_REG QEPCTL; // QEP control
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
union QPOSCTL_REG QPOSCTL; // Position compare control
union QEINT_REG QEINT; // QEP interrupt control
union QFLG_REG QFLG; // QEP interrupt flag
union QFLG_REG QCLR; // QEP interrupt clear
union QFRC_REG QFRC; // QEP interrupt force
union QEPSTS_REG QEPSTS; // QEP status
Uint16 QCTMR; // QEP capture timer
Uint16 QCPRD; // QEP capture period
Uint16 QCTMRLAT; // QEP capture latch
Uint16 QCPRDLAT; // QEP capture period latch
Uint16 rsvd1[30]; // reserved
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EQEP_H definition
//
// End of file
//

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// TI File $Revision: /main/2 $
// Checkin $Date: March 22, 2007 10:40:22 $
//###########################################################################
//
// FILE: DSP2833x_I2c.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_I2C_H
#define DSP2833x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
//
// I2C interrupt vector register bit definitions
//
struct I2CISRC_BITS { // bits description
Uint16 INTCODE:3; // 2:0 Interrupt code
Uint16 rsvd1:13; // 15:3 reserved
};
union I2CISRC_REG {
Uint16 all;
struct I2CISRC_BITS bit;
};
//
// I2C interrupt mask register bit definitions
//
struct I2CIER_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 AAS:1; // 6 Address as slave
Uint16 rsvd:9; // 15:7 reserved
};
union I2CIER_REG {
Uint16 all;
struct I2CIER_BITS bit;
};
//
// I2C status register bit definitions
//
struct I2CSTR_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 rsvd1:2; // 7:6 reserved
Uint16 AD0:1; // 8 Address Zero
Uint16 AAS:1; // 9 Address as slave
Uint16 XSMT:1; // 10 XMIT shift empty
Uint16 RSFULL:1; // 11 Recieve shift full
Uint16 BB:1; // 12 Bus busy
Uint16 NACKSNT:1; // 13 A no ack sent
Uint16 SDIR:1; // 14 Slave direction
Uint16 rsvd2:1; // 15 reserved
};
union I2CSTR_REG {
Uint16 all;
struct I2CSTR_BITS bit;
};
//
// I2C mode control register bit definitions
//
struct I2CMDR_BITS { // bits description
Uint16 BC:3; // 2:0 Bit count
Uint16 FDF:1; // 3 Free data format
Uint16 STB:1; // 4 Start byte
Uint16 IRS:1; // 5 I2C Reset not
Uint16 DLB:1; // 6 Digital loopback
Uint16 RM:1; // 7 Repeat mode
Uint16 XA:1; // 8 Expand address
Uint16 TRX:1; // 9 Transmitter/reciever
Uint16 MST:1; // 10 Master/slave
Uint16 STP:1; // 11 Stop condition
Uint16 rsvd1:1; // 12 reserved
Uint16 STT:1; // 13 Start condition
Uint16 FREE:1; // 14 Emulation mode
Uint16 NACKMOD:1; // 15 No Ack mode
};
union I2CMDR_REG {
Uint16 all;
struct I2CMDR_BITS bit;
};
//
// I2C extended mode control register bit definitions
//
struct I2CEMDR_BITS { // bits description
Uint16 BCM:1; // 0 Backward compatibility mode
Uint16 rsvd:15; // 15 reserved
};
union I2CEMDR_REG {
Uint16 all;
struct I2CEMDR_BITS bit;
};
//
// I2C pre-scaler register bit definitions
//
struct I2CPSC_BITS { // bits description
Uint16 IPSC:8; // 7:0 pre-scaler
Uint16 rsvd1:8; // 15:8 reserved
};
union I2CPSC_REG {
Uint16 all;
struct I2CPSC_BITS bit;
};
//
// TX FIFO control register bit definitions
//
struct I2CFFTX_BITS { // bits description
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 TXFFINTCLR:1; // 6 FIFO clear
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
Uint16 TXFFST:5; // 12:8 FIFO level status
Uint16 TXFFRST:1; // 13 FIFO reset
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
Uint16 rsvd1:1; // 15 reserved
};
union I2CFFTX_REG {
Uint16 all;
struct I2CFFTX_BITS bit;
};
//
// RX FIFO control register bit definitions
//
struct I2CFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 RXFFINTCLR:1; // 6 FIFO clear
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
Uint16 RXFFST:5; // 12:8 FIFO level
Uint16 RXFFRST:1; // 13 FIFO reset
Uint16 rsvd1:2; // 15:14 reserved
};
union I2CFFRX_REG {
Uint16 all;
struct I2CFFRX_BITS bit;
};
struct I2C_REGS {
Uint16 I2COAR; // Own address register
union I2CIER_REG I2CIER; // Interrupt enable
union I2CSTR_REG I2CSTR; // Interrupt status
Uint16 I2CCLKL; // Clock divider low
Uint16 I2CCLKH; // Clock divider high
Uint16 I2CCNT; // Data count
Uint16 I2CDRR; // Data recieve
Uint16 I2CSAR; // Slave address
Uint16 I2CDXR; // Data transmit
union I2CMDR_REG I2CMDR; // Mode
union I2CISRC_REG I2CISRC; // Interrupt source
union I2CEMDR_REG I2CEMDR; // Extended Mode
union I2CPSC_REG I2CPSC; // Pre-scaler
Uint16 rsvd2[19]; // reserved
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
};
//
// External References & Function Declarations
//
extern volatile struct I2C_REGS I2caRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_I2C_H definition
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: April 22, 2008 14:35:56 $
//###########################################################################
//
// FILE: DSP28x_Project.h
//
// TITLE: DSP28x Project Headerfile and Examples Include File
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP28x_PROJECT_H
#define DSP28x_PROJECT_H
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#endif // end of DSP28x_PROJECT_H definition

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// TI File $Revision: /main/4 $
// Checkin $Date: March 20, 2007 15:33:42 $
//###########################################################################
//
// FILE: DSP2833x_CpuTimers.h
//
// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
//
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
// other realtime operating systems.
//
// Do not use these two timers in your application if you ever plan
// on integrating DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two
// timers if using DSP-BIOS or another realtime OS.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_CPU_TIMERS_H
#define DSP2833x_CPU_TIMERS_H
#ifdef __cplusplus
extern "C" {
#endif
//
// CPU Timer Register Bit Definitions
//
//
// TCR: Control register bit definitions
//
struct TCR_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 TSS:1; // 4 Timer Start/Stop
Uint16 TRB:1; // 5 Timer reload
Uint16 rsvd2:4; // 9:6 reserved
Uint16 SOFT:1; // 10 Emulation modes
Uint16 FREE:1; // 11
Uint16 rsvd3:2; // 12:13 reserved
Uint16 TIE:1; // 14 Output enable
Uint16 TIF:1; // 15 Interrupt flag
};
union TCR_REG {
Uint16 all;
struct TCR_BITS bit;
};
//
// TPR: Pre-scale low bit definitions
//
struct TPR_BITS { // bits description
Uint16 TDDR:8; // 7:0 Divide-down low
Uint16 PSC:8; // 15:8 Prescale counter low
};
union TPR_REG {
Uint16 all;
struct TPR_BITS bit;
};
//
// TPRH: Pre-scale high bit definitions
//
struct TPRH_BITS { // bits description
Uint16 TDDRH:8; // 7:0 Divide-down high
Uint16 PSCH:8; // 15:8 Prescale counter high
};
union TPRH_REG {
Uint16 all;
struct TPRH_BITS bit;
};
//
// TIM, TIMH: Timer register definitions
//
struct TIM_REG {
Uint16 LSW;
Uint16 MSW;
};
union TIM_GROUP {
Uint32 all;
struct TIM_REG half;
};
//
// PRD, PRDH: Period register definitions
//
struct PRD_REG {
Uint16 LSW;
Uint16 MSW;
};
union PRD_GROUP {
Uint32 all;
struct PRD_REG half;
};
//
// CPU Timer Register File
//
struct CPUTIMER_REGS {
union TIM_GROUP TIM; // Timer counter register
union PRD_GROUP PRD; // Period register
union TCR_REG TCR; // Timer control register
Uint16 rsvd1; // reserved
union TPR_REG TPR; // Timer pre-scale low
union TPRH_REG TPRH; // Timer pre-scale high
};
//
// CPU Timer Support Variables
//
struct CPUTIMER_VARS {
volatile struct CPUTIMER_REGS *RegsAddr;
Uint32 InterruptCount;
float CPUFreqInMHz;
float PeriodInUSec;
};
//
// Function prototypes and external definitions
//
void InitCpuTimers(void);
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
extern struct CPUTIMER_VARS CpuTimer0;
//
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS.
// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
//
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
extern struct CPUTIMER_VARS CpuTimer1;
extern struct CPUTIMER_VARS CpuTimer2;
//
// Defines for useful Timer Operations:
//
//
// Start Timer
//
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
//
// Stop Timer
//
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
//
// Reload Timer With period Value
//
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
//
// Read 32-Bit Timer Value
//
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
//
// Read 32-Bit Period Value
//
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
//
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
// Do not use these two timers if you ever plan on integrating
// DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two timers
// if using DSP-BIOS or another realtime OS.
//
//
// Start Timer
//
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
//
// Stop Timer
//
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
//
// Reload Timer With period Value
//
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
//
// Read 32-Bit Timer Value
//
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
//
// Read 32-Bit Period Value
//
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_CPU_TIMERS_H definition
//
// End of file
//

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extern unsigned char SURESOFT_CODESCROLL_STATIC_DUMMY_VARIABLE_c;
extern unsigned int codescroll_built_in_line_macro;

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// TI File $Revision: /main/4 $
// Checkin $Date: November 15, 2007 09:58:53 $
//###########################################################################
//
// FILE: DSP2833x_Gpio.h
//
// TITLE: DSP2833x General Purpose I/O Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_GPIO_H
#define DSP2833x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
//
// GPIO A control register bit definitions
//
struct GPACTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24 Qual period
};
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit;
};
//
// GPIO B control register bit definitions
//
struct GPBCTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24
};
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit;
};
//
// GPIO A Qual/MUX select register bit definitions
//
struct GPA1_BITS { // bits description
Uint16 GPIO0:2; // 1:0 GPIO0
Uint16 GPIO1:2; // 3:2 GPIO1
Uint16 GPIO2:2; // 5:4 GPIO2
Uint16 GPIO3:2; // 7:6 GPIO3
Uint16 GPIO4:2; // 9:8 GPIO4
Uint16 GPIO5:2; // 11:10 GPIO5
Uint16 GPIO6:2; // 13:12 GPIO6
Uint16 GPIO7:2; // 15:14 GPIO7
Uint16 GPIO8:2; // 17:16 GPIO8
Uint16 GPIO9:2; // 19:18 GPIO9
Uint16 GPIO10:2; // 21:20 GPIO10
Uint16 GPIO11:2; // 23:22 GPIO11
Uint16 GPIO12:2; // 25:24 GPIO12
Uint16 GPIO13:2; // 27:26 GPIO13
Uint16 GPIO14:2; // 29:28 GPIO14
Uint16 GPIO15:2; // 31:30 GPIO15
};
struct GPA2_BITS { // bits description
Uint16 GPIO16:2; // 1:0 GPIO16
Uint16 GPIO17:2; // 3:2 GPIO17
Uint16 GPIO18:2; // 5:4 GPIO18
Uint16 GPIO19:2; // 7:6 GPIO19
Uint16 GPIO20:2; // 9:8 GPIO20
Uint16 GPIO21:2; // 11:10 GPIO21
Uint16 GPIO22:2; // 13:12 GPIO22
Uint16 GPIO23:2; // 15:14 GPIO23
Uint16 GPIO24:2; // 17:16 GPIO24
Uint16 GPIO25:2; // 19:18 GPIO25
Uint16 GPIO26:2; // 21:20 GPIO26
Uint16 GPIO27:2; // 23:22 GPIO27
Uint16 GPIO28:2; // 25:24 GPIO28
Uint16 GPIO29:2; // 27:26 GPIO29
Uint16 GPIO30:2; // 29:28 GPIO30
Uint16 GPIO31:2; // 31:30 GPIO31
};
struct GPB1_BITS { // bits description
Uint16 GPIO32:2; // 1:0 GPIO32
Uint16 GPIO33:2; // 3:2 GPIO33
Uint16 GPIO34:2; // 5:4 GPIO34
Uint16 GPIO35:2; // 7:6 GPIO35
Uint16 GPIO36:2; // 9:8 GPIO36
Uint16 GPIO37:2; // 11:10 GPIO37
Uint16 GPIO38:2; // 13:12 GPIO38
Uint16 GPIO39:2; // 15:14 GPIO39
Uint16 GPIO40:2; // 17:16 GPIO40
Uint16 GPIO41:2; // 19:16 GPIO41
Uint16 GPIO42:2; // 21:20 GPIO42
Uint16 GPIO43:2; // 23:22 GPIO43
Uint16 GPIO44:2; // 25:24 GPIO44
Uint16 GPIO45:2; // 27:26 GPIO45
Uint16 GPIO46:2; // 29:28 GPIO46
Uint16 GPIO47:2; // 31:30 GPIO47
};
struct GPB2_BITS { // bits description
Uint16 GPIO48:2; // 1:0 GPIO48
Uint16 GPIO49:2; // 3:2 GPIO49
Uint16 GPIO50:2; // 5:4 GPIO50
Uint16 GPIO51:2; // 7:6 GPIO51
Uint16 GPIO52:2; // 9:8 GPIO52
Uint16 GPIO53:2; // 11:10 GPIO53
Uint16 GPIO54:2; // 13:12 GPIO54
Uint16 GPIO55:2; // 15:14 GPIO55
Uint16 GPIO56:2; // 17:16 GPIO56
Uint16 GPIO57:2; // 19:18 GPIO57
Uint16 GPIO58:2; // 21:20 GPIO58
Uint16 GPIO59:2; // 23:22 GPIO59
Uint16 GPIO60:2; // 25:24 GPIO60
Uint16 GPIO61:2; // 27:26 GPIO61
Uint16 GPIO62:2; // 29:28 GPIO62
Uint16 GPIO63:2; // 31:30 GPIO63
};
struct GPC1_BITS { // bits description
Uint16 GPIO64:2; // 1:0 GPIO64
Uint16 GPIO65:2; // 3:2 GPIO65
Uint16 GPIO66:2; // 5:4 GPIO66
Uint16 GPIO67:2; // 7:6 GPIO67
Uint16 GPIO68:2; // 9:8 GPIO68
Uint16 GPIO69:2; // 11:10 GPIO69
Uint16 GPIO70:2; // 13:12 GPIO70
Uint16 GPIO71:2; // 15:14 GPIO71
Uint16 GPIO72:2; // 17:16 GPIO72
Uint16 GPIO73:2; // 19:18 GPIO73
Uint16 GPIO74:2; // 21:20 GPIO74
Uint16 GPIO75:2; // 23:22 GPIO75
Uint16 GPIO76:2; // 25:24 GPIO76
Uint16 GPIO77:2; // 27:26 GPIO77
Uint16 GPIO78:2; // 29:28 GPIO78
Uint16 GPIO79:2; // 31:30 GPIO79
};
struct GPC2_BITS { // bits description
Uint16 GPIO80:2; // 1:0 GPIO80
Uint16 GPIO81:2; // 3:2 GPIO81
Uint16 GPIO82:2; // 5:4 GPIO82
Uint16 GPIO83:2; // 7:6 GPIO83
Uint16 GPIO84:2; // 9:8 GPIO84
Uint16 GPIO85:2; // 11:10 GPIO85
Uint16 GPIO86:2; // 13:12 GPIO86
Uint16 GPIO87:2; // 15:14 GPIO87
Uint16 rsvd:16; // 31:16 reserved
};
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};
union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};
union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
union GPC1_REG {
Uint32 all;
struct GPC1_BITS bit;
};
union GPC2_REG {
Uint32 all;
struct GPC2_BITS bit;
};
//
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions
//
struct GPADAT_BITS { // bits description
Uint16 GPIO0:1; // 0 GPIO0
Uint16 GPIO1:1; // 1 GPIO1
Uint16 GPIO2:1; // 2 GPIO2
Uint16 GPIO3:1; // 3 GPIO3
Uint16 GPIO4:1; // 4 GPIO4
Uint16 GPIO5:1; // 5 GPIO5
Uint16 GPIO6:1; // 6 GPIO6
Uint16 GPIO7:1; // 7 GPIO7
Uint16 GPIO8:1; // 8 GPIO8
Uint16 GPIO9:1; // 9 GPIO9
Uint16 GPIO10:1; // 10 GPIO10
Uint16 GPIO11:1; // 11 GPIO11
Uint16 GPIO12:1; // 12 GPIO12
Uint16 GPIO13:1; // 13 GPIO13
Uint16 GPIO14:1; // 14 GPIO14
Uint16 GPIO15:1; // 15 GPIO15
Uint16 GPIO16:1; // 16 GPIO16
Uint16 GPIO17:1; // 17 GPIO17
Uint16 GPIO18:1; // 18 GPIO18
Uint16 GPIO19:1; // 19 GPIO19
Uint16 GPIO20:1; // 20 GPIO20
Uint16 GPIO21:1; // 21 GPIO21
Uint16 GPIO22:1; // 22 GPIO22
Uint16 GPIO23:1; // 23 GPIO23
Uint16 GPIO24:1; // 24 GPIO24
Uint16 GPIO25:1; // 25 GPIO25
Uint16 GPIO26:1; // 26 GPIO26
Uint16 GPIO27:1; // 27 GPIO27
Uint16 GPIO28:1; // 28 GPIO28
Uint16 GPIO29:1; // 29 GPIO29
Uint16 GPIO30:1; // 30 GPIO30
Uint16 GPIO31:1; // 31 GPIO31
};
struct GPBDAT_BITS { // bits description
Uint16 GPIO32:1; // 0 GPIO32
Uint16 GPIO33:1; // 1 GPIO33
Uint16 GPIO34:1; // 2 GPIO34
Uint16 GPIO35:1; // 3 GPIO35
Uint16 GPIO36:1; // 4 GPIO36
Uint16 GPIO37:1; // 5 GPIO37
Uint16 GPIO38:1; // 6 GPIO38
Uint16 GPIO39:1; // 7 GPIO39
Uint16 GPIO40:1; // 8 GPIO40
Uint16 GPIO41:1; // 9 GPIO41
Uint16 GPIO42:1; // 10 GPIO42
Uint16 GPIO43:1; // 11 GPIO43
Uint16 GPIO44:1; // 12 GPIO44
Uint16 GPIO45:1; // 13 GPIO45
Uint16 GPIO46:1; // 14 GPIO46
Uint16 GPIO47:1; // 15 GPIO47
Uint16 GPIO48:1; // 16 GPIO48
Uint16 GPIO49:1; // 17 GPIO49
Uint16 GPIO50:1; // 18 GPIO50
Uint16 GPIO51:1; // 19 GPIO51
Uint16 GPIO52:1; // 20 GPIO52
Uint16 GPIO53:1; // 21 GPIO53
Uint16 GPIO54:1; // 22 GPIO54
Uint16 GPIO55:1; // 23 GPIO55
Uint16 GPIO56:1; // 24 GPIO56
Uint16 GPIO57:1; // 25 GPIO57
Uint16 GPIO58:1; // 26 GPIO58
Uint16 GPIO59:1; // 27 GPIO59
Uint16 GPIO60:1; // 28 GPIO60
Uint16 GPIO61:1; // 29 GPIO61
Uint16 GPIO62:1; // 30 GPIO62
Uint16 GPIO63:1; // 31 GPIO63
};
struct GPCDAT_BITS { // bits description
Uint16 GPIO64:1; // 0 GPIO64
Uint16 GPIO65:1; // 1 GPIO65
Uint16 GPIO66:1; // 2 GPIO66
Uint16 GPIO67:1; // 3 GPIO67
Uint16 GPIO68:1; // 4 GPIO68
Uint16 GPIO69:1; // 5 GPIO69
Uint16 GPIO70:1; // 6 GPIO70
Uint16 GPIO71:1; // 7 GPIO71
Uint16 GPIO72:1; // 8 GPIO72
Uint16 GPIO73:1; // 9 GPIO73
Uint16 GPIO74:1; // 10 GPIO74
Uint16 GPIO75:1; // 11 GPIO75
Uint16 GPIO76:1; // 12 GPIO76
Uint16 GPIO77:1; // 13 GPIO77
Uint16 GPIO78:1; // 14 GPIO78
Uint16 GPIO79:1; // 15 GPIO79
Uint16 GPIO80:1; // 16 GPIO80
Uint16 GPIO81:1; // 17 GPIO81
Uint16 GPIO82:1; // 18 GPIO82
Uint16 GPIO83:1; // 19 GPIO83
Uint16 GPIO84:1; // 20 GPIO84
Uint16 GPIO85:1; // 21 GPIO85
Uint16 GPIO86:1; // 22 GPIO86
Uint16 GPIO87:1; // 23 GPIO87
Uint16 rsvd1:8; // 31:24 reserved
};
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
union GPCDAT_REG {
Uint32 all;
struct GPCDAT_BITS bit;
};
//
// GPIO Xint1/XINT2/XNMI select register bit definitions
//
struct GPIOXINT_BITS { // bits description
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
Uint16 rsvd1:11; // 15:5 reserved
};
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
//
// GPIO A Qualifier Select 1 Register (GPIO0 to 15)
//
union GPA1_REG GPAQSEL1;
//
// GPIO A Qualifier Select 2 Register (GPIO16 to 31)
//
union GPA2_REG GPAQSEL2;
//
// GPIO A Mux 1 Register (GPIO0 to 15)
//
union GPA1_REG GPAMUX1;
//
// GPIO A Mux 2 Register (GPIO16 to 31)
//
union GPA2_REG GPAMUX2;
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
//
// GPIO A Pull Up Disable Register (GPIO0 to 31)
//
union GPADAT_REG GPAPUD;
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
//
// GPIO B Qualifier Select 1 Register (GPIO32 to 47)
//
union GPB1_REG GPBQSEL1;
//
// GPIO B Qualifier Select 2 Register (GPIO48 to 63)
//
union GPB2_REG GPBQSEL2;
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
//
// GPIO B Pull Up Disable Register (GPIO32 to 63)
//
union GPBDAT_REG GPBPUD;
Uint16 rsvd2[8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
//
// GPIO C Pull Up Disable Register (GPIO64 to 95)
//
union GPCDAT_REG GPCPUD;
};
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
//
// GPIO Data Set Register (GPIO0 to 31)
//
union GPADAT_REG GPASET;
//
// GPIO Data Clear Register (GPIO0 to 31)
//
union GPADAT_REG GPACLEAR;
//
// GPIO Data Toggle Register (GPIO0 to 31)
//
union GPADAT_REG GPATOGGLE;
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
//
// GPIO Data Set Register (GPIO32 to 63)
//
union GPBDAT_REG GPBSET;
//
// GPIO Data Clear Register (GPIO32 to 63)
//
union GPBDAT_REG GPBCLEAR;
//
// GPIO Data Toggle Register (GPIO32 to 63)
//
union GPBDAT_REG GPBTOGGLE;
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
//
// GPIO Data Clear Register (GPIO64 to 95)
//
union GPCDAT_REG GPCCLEAR;
//
// GPIO Data Toggle Register (GPIO64 to 95)
//
union GPCDAT_REG GPCTOGGLE;
Uint16 rsvd1[8];
};
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection
union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection
union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection
union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection
union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection
union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection
union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection
union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection
union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_GPIO_H definition
//
// End of file
//

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// TI File $Revision: /main/11 $
// Checkin $Date: May 12, 2008 14:30:08 $
//###########################################################################
//
// FILE: DSP2833x_GlobalPrototypes.h
//
// TITLE: Global prototypes for DSP2833x Examples
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_GLOBALPROTOTYPES_H
#define DSP2833x_GLOBALPROTOTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// shared global function prototypes
//
extern void InitAdc(void);
extern void DMAInitialize(void);
//
// DMA Channel 1
//
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH1(void);
//
// DMA Channel 2
//
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH2(void);
//
// DMA Channel 3
//
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH3(void);
//
// DMA Channel 4
//
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH4(void);
//
// DMA Channel 5
//
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH5(void);
//
// DMA Channel 6
//
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH6(void);
extern void InitPeripherals(void);
#if DSP28_ECANA
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
#endif // endif DSP28_ECANA
#if DSP28_ECANB
extern void InitECanb(void);
extern void InitECanbGpio(void);
#endif // endif DSP28_ECANB
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
#if DSP28_ECAP3
extern void InitECap3Gpio(void);
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
extern void InitECap4Gpio(void);
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
extern void InitECap5Gpio(void);
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
extern void InitECap6Gpio(void);
#endif // endif DSP28_ECAP6
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
#if DSP28_EPWM4
extern void InitEPwm4Gpio(void);
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
extern void InitEPwm5Gpio(void);
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
extern void InitEPwm6Gpio(void);
#endif // endif DSP28_EPWM6
#if DSP28_EQEP1
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
extern void InitEQep2Gpio(void);
#endif // endif DSP28_EQEP2
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitMcbsp(void);
extern void InitMcbspa(void);
extern void delay_loop(void);
extern void InitMcbspaGpio(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
#if DSP28_MCBSPB
extern void InitMcbspb(void);
extern void InitMcbspbGpio(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
#endif // endif DSP28_MCBSPB
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
#if DSP28_SCIB
extern void InitScibGpio(void);
#endif // endif DSP28_SCIB
#if DSP28_SCIC
extern void InitScicGpio(void);
#endif
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void InitXintf(void);
extern void InitXintf16Gpio();
extern void InitXintf32Gpio();
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ADC_cal (void);
#define KickDog ServiceDog // For compatiblity with previous versions
extern void ServiceDog(void);
extern void DisableDog(void);
extern Uint16 CsmUnlock(void);
//
// DSP28_DBGIER.asm
//
extern void SetDBGIER(Uint16 dbgier);
//
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
//
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in either Flash or XINTF to a different RUN location in internal
// RAM
//
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 XintffuncsLoadStart;
extern Uint16 XintffuncsLoadEnd;
extern Uint16 XintffuncsRunStart;
extern Uint16 XintffuncsLoadSize;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
//
// End of file
//

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#ifndef SOURCE_COMM_H_
#define SOURCE_COMM_H_
typedef struct ClassCommCheck
{
Uint16 CarComputer;
Uint16 Gcu;
Uint16 Ecu;
} CCommCheck;
typedef struct ClassTx100
{
struct
{
Uint16 Heartbit : 16;
Uint16 : 8;
Uint16 : 8;
Uint16 : 8;
Uint16 VersionMajor : 8;
Uint16 VersionMinor : 8;
Uint16 VersionPatch : 8;
} ApuData;
} CTx100;
typedef struct ClassTx101
{
struct
{
/* byte 0 */
Uint16 PlayState : 3;
Uint16 : 5;
/* byte 1 */
Uint16 AlarmOccured : 1;
Uint16 Emergency : 1;
Uint16 PowerSwitch : 1;
Uint16 : 5;
/* byte 2 */
Uint16 GcuPlayState : 3;
Uint16 : 5;
/* byte 3 */
Uint16 GcuAlarmOccured : 1;
Uint16 GcuShutdown : 1;
Uint16 : 6;
/* byte 4 */
Uint16 EcuAlarmOccured : 1;
Uint16 EcuPlayState : 3;
Uint16 OverrideActive : 1;
Uint16 GlowPlugActive : 1;
Uint16 HeaterActive : 1;
Uint16 OilPressureMissing : 1;
} ApuData;
} CTx101;
typedef struct ClassTx102
{
struct
{
Uint16 PlayCommand : 4; // 0:3 bit
Uint16 rsvd_padding1 : 4; // 4:7 bit
Uint16 rsvd_padding2 : 8; // 1 byte
Uint16 rsvd_padding3 : 16; // 2:3 byte
Uint16 rsvd_padding4 : 16; // 4:5 byte
Uint16 rsvd_padding5 : 16; // 6:7 byte
} GcuCommand;
} CTx102;
typedef struct ClassTx103
{
struct
{
Uint16 EngineStart : 8; // 0 byte
Uint16 EngineStop : 8; // 1 byte
Uint16 rsvd_padding1 : 8; // 2 byte
Uint16 rsvd_padding2 : 8; // 3 byte
Uint16 RpmSetpoint : 16; // 4:5 byte
Uint16 Override : 8; // 6 byte
Uint16 Emergency : 8; // 7 byte
} EcuCommand;
} CTx103;
typedef struct ClassTx110
{
union
{
Uint16 uiTotal;
struct
{
Uint16 PcbOverHeat : 1; // 0 bit
Uint16 FetOverHeat : 1; // 1 bit
Uint16 GenOverHeat1 : 1; // 2 bit
Uint16 GenOverHeat2 : 1; // 3 bit
Uint16 rsvd_padding : 12; // 16bit 정렬을 위한 패딩
} bit;
} GcuWarning;
union
{
Uint16 uiTotal;
struct
{
Uint16 EngineOverHeat : 1; // 0 bit
Uint16 LowOilLevel : 1; // 1 bit
Uint16 IntakeOverHeat : 1; // 2 bit
Uint16 IntakeLoPressure : 1; // 3 bit
Uint16 EngineLoTemperature : 1; // 4 bit
Uint16 EngineSensor : 1; // 5 bit
Uint16 DefaltValueActive : 1; // 6 bit
Uint16 rsvd_padding : 1; // 16bit 정렬을 위한 패딩
} bit;
} EcuWarning;
struct
{
CFaultBitValue ApuFault;
};
union
{
Uint16 uiTotal;
struct
{
Uint16 HwTrip : 1; // 0 bit
Uint16 HwIgbt : 1; // 1 bit
Uint16 HwDc : 1; // 2 bit
Uint16 GenOverCurrentU : 1; // 3 bit
Uint16 GenOverCurrentV : 1; // 4 bit
Uint16 GenOverCurrentW : 1; // 5 bit
Uint16 DcOverVoltage : 1; // 6 bit
Uint16 DcOverCurrent : 1; // 7 bit
Uint16 CrankningOverCurrent : 1; // 0 bit
Uint16 PcbOverHeat : 1; // 1 bit
Uint16 FetOverHeat : 1; // 2 bit
Uint16 GenTempOverHeat1 : 1; // 3 bit
Uint16 GenTempOverHeat2 : 1; // 4 bit
Uint16 GenOverSpeed : 1; // 5 bit
Uint16 ResolverIC : 1; // 6 bit
Uint16 ResolverParity : 1; // 7 bit
} bit;
} GcuFault;
union
{
Uint16 uiTotal;
struct
{
Uint16 EngineOverHeat : 1; // 0 bit
Uint16 LowOilPressure : 1; // 1 bit
Uint16 Actuator : 1; // 2 bit
Uint16 RpmSignal : 1; // 3 bit
Uint16 EngineStartFail : 1; // 4 bit
Uint16 rsvd_padding : 11; // 16bit 정렬을 위한 패딩
} bit;
} EcuFault;
} CTx110;
typedef struct ClassTx120
{
struct
{
Uint16 DcVoltage : 16; // 0:1 byte
Uint16 DcCurrent : 16; // 2:3 byte
Uint16 Rpm : 16; // 4:5 byte
Uint16 rsvd_padding3 : 8; // 6 byte
Uint16 rsvd_padding4 : 8; // 7 byte
} GcuData;
} CTx120;
typedef struct ClassTx121
{
struct
{
Uint16 PcbTemperature : 8; // 0 byte
Uint16 FetTemperature : 8; // 1 byte
Uint16 GenTemperature1 : 8; // 2 byte
Uint16 GenTemperature2 : 8; // 3 byte
Uint16 rsvd_padding1 : 8; // 4 byte
Uint16 rsvd_padding2 : 8; // 5 byte
Uint16 rsvd_padding3 : 8; // 6 byte
Uint16 rsvd_padding4 : 8; // 7 byte
} GcuData;
} CTx121;
typedef struct ClassTx130
{
struct
{
Uint16 ActualRpm : 16; // 0:1 byte
Uint16 SetRpm : 16; // 2:3 byte
Uint16 ActualTorque : 8; // 4 byte
Uint16 SetTorque : 8; // 5 byte
Uint16 SystemVoltage : 16; // 6:7 byte
} EcuData;
} CTx130;
typedef struct ClassTx131
{
struct
{
Uint16 CoolantTemperature : 8; // 0 byte
Uint16 Fan1Speed : 8; // 1 byte
Uint16 Fan2Speed : 8; // 2 byte
Uint16 CoolantPumpSpeed : 8; // 3 byte
Uint16 BarometicPressure : 16; // 4:5 byte
Uint16 rsvd_padding1 : 8; // 6 byte
Uint16 rsvd_padding2 : 8; // 7 byte
} EcuData;
} CTx131;
typedef struct ClassTx132
{
struct
{
Uint16 TotalOperTimeL : 16; // 0:1 byte
Uint16 TotalOperTimeH : 16; // 2:3 byte
Uint16 rsvd_padding1 : 8; // 4 byte
Uint16 rsvd_padding2 : 8; // 5 byte
Uint16 rsvd_padding3 : 8; // 6 byte
Uint16 rsvd_padding4 : 8; // 7 byte
} EcuData;
} CTx132;
typedef struct ClassRx200
{
struct
{
Uint16 HeartBit : 16; // 0:1 byte
Uint16 rsvd_padding1 : 8; // 2 byte
Uint16 rsvd_padding2 : 8; // 3 byte
Uint16 rsvd_padding3 : 8; // 4 byte
Uint16 VersionMajor : 8; // 5 byte
Uint16 VersionMinor : 8; // 6 byte
Uint16 VersionPatch : 8; // 7 byte
} GcuData;
} CRx200;
typedef struct ClassRx201
{
struct
{
Uint16 PlayState : 3; // 0:3 bit
Uint16 rsvd_padding1 : 5; // 4:7 bit
Uint16 AlarmOccured : 1; // 0 bit
Uint16 Shutdown : 1; // 1 bit
Uint16 rsvd_padding2 : 6; // 2:7 bit
} GcuData;
} CRx201;
typedef struct ClassRx210
{
union
{
Uint16 uiTotal;
struct
{
Uint16 PcbOverHeat : 1; // 0 bit
Uint16 FetOverHeat : 1; // 1 bit
Uint16 GenOverHeat1 : 1; // 2 bit
Uint16 GenOverHeat2 : 1; // 3 bit
Uint16 rsvd_padding : 12; // 16bit 정렬을 위한 패딩
} bit;
} GcuWarning;
union
{
Uint16 uiTotal;
struct
{
Uint16 HwTrip : 1; // 0 bit
Uint16 HwIgbt : 1; // 1 bit
Uint16 HwDc : 1; // 2 bit
Uint16 GenOverCurrentU : 1; // 3 bit
Uint16 GenOverCurrentV : 1; // 4 bit
Uint16 GenOverCurrentW : 1; // 5 bit
Uint16 DcOverVoltage : 1; // 6 bit
Uint16 DcOverCurrent : 1; // 7 bit
Uint16 CrankningOverCurrent : 1; // 0 bit
Uint16 PcbOverHeat : 1; // 1 bit
Uint16 FetOverHeat : 1; // 2 bit
Uint16 GenTempOverHeat1 : 1; // 3 bit
Uint16 GenTempOverHeat2 : 1; // 4 bit
Uint16 GenOverSpeed : 1; // 5 bit
Uint16 ResolverIC : 1; // 6 bit
Uint16 ResolverParity : 1; // 7 bit
} bit;
}GcuFault;
} CRx210;
typedef struct ClassRx220
{
struct
{
Uint16 DcVoltage : 16; // 0:1 byte
Uint16 DcCurrent : 16; // 2:3 byte
Uint16 Rpm : 16; // 4:5 byte
Uint16 rsvd_padding : 16; // 6:7 byte
} GcuData;
} CRx220;
typedef struct ClassRx221
{
struct
{
Uint16 PcbTemperature : 8; // 0 byte
Uint16 FetTemperature : 8; // 1 byte
Uint16 GenTemperature1 : 8; // 2 byte
Uint16 GenTemperature2 : 8; // 3 byte
Uint16 rsvd_padding1 : 16; // 4:5 byte
Uint16 rsvd_padding2 : 16; // 6:7 byte
} GcuData;
} CRx221;
typedef struct ClassRx300
{
struct
{
Uint16 VersionMajor : 8; // 0 byte
Uint16 VersionMinor : 8; // 1 byte
Uint16 VersionPatch : 8; // 2 byte
Uint16 rsvd_padding1 : 8; // 3 byte
Uint16 rsvd_padding2 : 16; // 4:5 byte
Uint16 rsvd_padding3 : 16; // 6:7 byte
} EcuData;
} CRx300;
typedef struct ClassRx301
{
struct
{
Uint16 AlarmOccured : 1; // 0 bit
Uint16 PlayState : 3; // 1:3 bit
Uint16 OverrideActive : 1; // 4 bit
Uint16 GlowPlugActive : 1; // 5 bit
Uint16 HeaterActive : 1; // 6 bit
Uint16 OilPressureMissing : 1; // 7 bit
Uint16 rsvd_padding : 8; // 16bit 정렬을 위한 패딩
} OperationInfo;
} CRx301;
typedef struct ClassRx310
{
union
{
Uint16 uiTotal;
struct
{
Uint16 EngineOverHeat : 1; // 0 bit
Uint16 reserved : 1; // 1 bit
Uint16 LowOilLevel : 1; // 2 bit
Uint16 IntakeOverHeat : 1; // 3 bit
Uint16 IntakeLoPressure : 1; // 4 bit
Uint16 EngineLoTemperature : 1; // 5 bit
Uint16 EngineSensor : 1; // 6 bit
Uint16 DefaltValueActive : 1; // 7 bit
Uint16 rsvd_padding : 8; // 16bit 정렬을 위한 패딩
} bit;
} EcuWarning;
union
{
Uint16 uiTotal;
struct
{
Uint16 OilPressureMissing : 1; // 0 bit
Uint16 IntakeOverHeat : 1; // 1 bit
Uint16 EngineOverHeat : 1; // 2 bit
Uint16 Actuator : 1; // 3 bit
Uint16 RpmSignal : 1; // 4 bit
Uint16 EngineStartFail : 1; // 5 bit
Uint16 rsvd_padding : 10; // 16bit 정렬을 위한 패딩
} bit;
} EcuFault;
} CRx310;
typedef struct ClassRx320
{
struct
{
Uint16 ActualRpm : 16; // 0:1 byte
Uint16 SetRpm : 16; // 2:3 byte
Uint16 ActualTorque : 8; // 4 byte
Uint16 SetTorque : 8; // 5 byte
Uint16 SystemVoltage : 16; // 6:7 byte
} EcuData;
} CRx320;
typedef struct ClassRx321
{
struct
{
Uint16 CoolantTemperature : 8; // 0 byte
Uint16 Fan1Speed : 8; // 1 byte
Uint16 Fan2Speed : 8; // 2 byte
Uint16 CoolantPumpSpeed : 8; // 3 byte
Uint16 BarometicPressure : 16; // 4:5 byte
Uint16 rsvd_padding : 16; // 6:7 byte
} EcuData;
} CRx321;
typedef struct ClassRx322
{
struct
{
Uint16 TotalOperTimeL : 16; // 0:1 byte
Uint16 TotalOperTimeH : 16; // 2:3 byte
Uint16 rsvd_padding1 : 16; // 4:5 byte
Uint16 rsvd_padding2 : 16; // 6:7 byte
} EcuData;
} CRx322;
interrupt void CECanInterruptA(void);
interrupt void CECanInterruptB(void);
void CSendECanDataA(void);
void CSendECanDataB(void);
void CInitEcan(void);
extern CCommCheck CommCheck;
extern CTx102 Tx102;
extern CTx103 Tx103;
extern CRx210 Rx210;
extern CRx220 Rx220;
extern CRx221 Rx221;
extern CRx310 Rx310;
extern CRx320 Rx320;
extern CRx321 Rx321;
extern CRx322 Rx322;
#endif /* SOURCE_COMM_H_ */

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#include "main.h"
void CApuStartReady(void);
void CApuStopProcedure(Uint16 Level);
void CSetEngineActualRpm(Uint16 Rpm);
static void CSetGcuCommand(Uint16 Command);
void CSetEcuCommand(Uint16 Command);
Uint16 CStartSwitchCheck(void);
void CApuOperProcedure(void)
{
if (CApuSystemAlarmCheck() > 0U || KeyOperValue.KeyList.bit.Emergency == 1U)
{
// 알람으로 인한 정지 상태(비상정지에 준함, 즉시정지)
CSetApuOperIndex(APU_OPER_IDX_EMERGENCY);
CActiveChipSelect(0U);
}
else
{
CSetApuOperIndex(APU_OPER_IDX_STANDBY);
switch (CGetApuOperIndex())
{
case APU_OPER_IDX_STANDBY:
{
if (KeyOperValue.KeyList.bit.EngineStartStop == 1U)
{
CSetApuOperIndex(APU_OPER_IDX_START_CHECK);
CActiveChipSelect(1U); // 시동키가 입력되면 CS ON
if (CGetEngCoolantTemperature() < -10) // 냉각수 온도 체크
{
CSetApuOperIndex(APU_OPER_IDX_ENGINE_PREHEAT);
}
else
{
CSetApuOperIndex(APU_OPER_IDX_CRANKING);
}
}
break;
}
case APU_OPER_IDX_ENGINE_PREHEAT:
{
break;
}
case APU_OPER_IDX_CRANKING:
{
CSetGcuCommand(GCU_OPER_CMD_CRANKING);
if (CGetGeneratorRpm() > 800)
{
CSetGcuCommand(GCU_OPER_CMD_STOP_CRANKING);
CSetApuOperIndex(APU_OPER_IDX_CHECK_OPERATION);
}
break;
}
case APU_OPER_IDX_CHECK_OPERATION:
{
}
}
}
}
void CSetApuOperIndex(eApuOperIdx idx)
{
GeneralOperValue.uiApuState = (Uint16) idx;
}
eApuOperIdx CGetApuOperIndex(void)
{
return (eApuOperIdx)GeneralOperValue.uiApuState;
}
Uint16 CStartSwitchCheck(void)
{
return KeyOperValue.KeyList.bit.EngineStartStop;
}
Uint16 CApuSystemAlarmCheck(void)
{
return ((FaultBitValue.ulTotal | Rx210.GcuFault.uiTotal | Rx310.EcuFault.uiTotal) > 0) ? 1U : 0U;
}
void CSetEngineActualRpm(Uint16 Rpm)
{
float32 fTemp = (float32) Rpm / 0.125f; // 0.125 mean : J1939 Scaling Factor.
Tx103.EcuCommand.RpmSetpoint = (Uint16) fTemp;
}
Uint16 CGetEngineActualRpm(void)
{
float32 fTemp = (float32) Rx320.EcuData.ActualRpm * 0.125f;
return (Uint16) fTemp;
}
Uint16 CGetGeneratorRpm(void)
{
return Rx220.GcuData.Rpm;
}
static void CSetGcuCommand(Uint16 Command)
{
GeneralOperValue.GcuCommand.PlayCmd = Command;
}
void CSetEcuCommand(Uint16 Command)
{
if (Command == ECU_OPER_CMD_STOP)
{
GeneralOperValue.EcuCommand.EngineStart = 0U;
GeneralOperValue.EcuCommand.EngineStop = 1U;
CSetEngineActualRpm(2400U);
}
else if (Command == ECU_OPER_CMD_START)
{
GeneralOperValue.EcuCommand.EngineStart = 1U;
GeneralOperValue.EcuCommand.EngineStop = 0U;
CSetEngineActualRpm(2400U);
}
else
{
// Emergency
GeneralOperValue.EcuCommand.EngineStart = 0U;
GeneralOperValue.EcuCommand.EngineStop = 1U;
CSetEngineActualRpm(0U);
}
}
int16 CGetEngCoolantTemperature(void)
{
return (int16) Rx321.EcuData.CoolantTemperature - 40; // 온도 오프셋 -40도
}
void CDebugModeProcedure(void)
{
if (GeneralOperValue.Maintenence.ManualCranking == 1U)
{
if (CApuSystemAlarmCheck() == 0U)
{
; // 알람이 없을 경우만 동작 하도록 함.
}
}
else
{
;
}
if (GeneralOperValue.Maintenence.LampTest == 1U)
{
GPIO_CPU_LED_OPERATION(1U);
GPIO_CPU_LED_FAULT(1U);
GPIO_CPU_LED_STOP(1U);
}
else
{
GPIO_CPU_LED_OPERATION(0U);
GPIO_CPU_LED_FAULT(0U);
GPIO_CPU_LED_STOP(0U);
}
if (GeneralOperValue.Maintenence.KeyTest == 1U)
{
if ((GPIO_KEY_UP() == 1U) && (GPIO_KEY_DOWN() == 1U))
{
GeneralOperValue.Maintenence.KeyTest = 0U;
OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE;
}
}
}
void CLedControlProcedure(void)
{
switch (CGetApuOperIndex())
{
case APU_OPER_IDX_EMERGENCY:
{
GPIO_CPU_LED_FAULT(1U);
GPIO_CPU_LED_STOP(1U);
GPIO_CPU_LED_OPERATION(0U);
break;
}
case APU_OPER_IDX_STANDBY:
{
GPIO_CPU_LED_STOP(1U);
GPIO_CPU_LED_FAULT(0U);
GPIO_CPU_LED_OPERATION(0U);
break;
}
case APU_OPER_IDX_ENGINE_STABLED:
{
GPIO_CPU_LED_OPERATION(1U);
GPIO_CPU_LED_FAULT(0U);
GPIO_CPU_LED_STOP(0U);
break;
}
default:
{
break;
}
}
}

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// TI File $Revision: /main/3 $
// Checkin $Date: April 17, 2008 11:08:27 $
//###########################################################################
//
// FILE: DSP2833x_Spi.h
//
// TITLE: DSP2833x Device SPI Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_SPI_H
#define DSP2833x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
//
// SPI Individual Register Bit Definitions
//
//
// SPI FIFO Transmit register bit definitions
//
struct SPIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFO:1; // 13 FIFO reset
Uint16 SPIFFENA:1; // 14 Enhancement enable
Uint16 SPIRST:1; // 15 Reset SPI
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
//
// SPI FIFO recieve register bit definitions
//
struct SPIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
//
// SPI FIFO control register bit definitions
//
struct SPIFFCT_BITS { // bits description
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:8; // 15:8 reserved
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
//
// SPI configuration register bit definitions
//
struct SPICCR_BITS { // bits description
Uint16 SPICHAR:4; // 3:0 Character length control
Uint16 SPILBK:1; // 4 Loop-back enable/disable
Uint16 rsvd1:1; // 5 reserved
Uint16 CLKPOLARITY:1; // 6 Clock polarity
Uint16 SPISWRESET:1; // 7 SPI SW Reset
Uint16 rsvd2:8; // 15:8 reserved
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
//
// SPI operation control register bit definitions
//
struct SPICTL_BITS { // bits description
Uint16 SPIINTENA:1; // 0 Interrupt enable
Uint16 TALK:1; // 1 Master/Slave transmit enable
Uint16 MASTER_SLAVE:1; // 2 Network control mode
Uint16 CLK_PHASE:1; // 3 Clock phase select
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
Uint16 rsvd:11; // 15:5 reserved
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
//
// SPI status register bit definitions
//
struct SPISTS_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
Uint16 rsvd2:8; // 15:8 reserved
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
//
// SPI priority control register bit definitions
//
struct SPIPRI_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 FREE:1; // 4 Free emulation mode control
Uint16 SOFT:1; // 5 Soft emulation mode control
Uint16 rsvd2:1; // 6 reserved
Uint16 rsvd3:9; // 15:7 reserved
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
//
// SPI Register File
//
struct SPI_REGS {
union SPICCR_REG SPICCR; // Configuration register
union SPICTL_REG SPICTL; // Operation control register
union SPISTS_REG SPISTS; // Status register
Uint16 rsvd1; // reserved
Uint16 SPIBRR; // Baud Rate
Uint16 rsvd2; // reserved
Uint16 SPIRXEMU; // Emulation buffer
Uint16 SPIRXBUF; // Serial input buffer
Uint16 SPITXBUF; // Serial output buffer
Uint16 SPIDAT; // Serial data
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
union SPIFFCT_REG SPIFFCT; // FIFO control register
Uint16 rsvd3[2]; // reserved
union SPIPRI_REG SPIPRI; // FIFO Priority control
};
//
// SPI External References & Function Declarations
//
extern volatile struct SPI_REGS SpiaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SPI_H definition
//
// End of file
//

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// TI File $Revision: /main/9 $
// Checkin $Date: July 2, 2008 14:31:12 $
//###########################################################################
//
// FILE: DSP2833x_Examples.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_EXAMPLES_H
#define DSP2833x_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
//
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//
// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
//
// Take into account the input clock frequency and the PLL multiplier
// selected in step 1.
//
// Use one of the values provided, or define your own.
// The trailing L is required tells the compiler to treat
// the number as a 64-bit value.
//
// Only one statement should be uncommented.
//
// Example 1:150 MHz devices:
// CLKIN is a 30MHz crystal.
//
// In step 1 the user specified PLLCR = 0xA for a
// 150Mhz CPU clock (SYSCLKOUT = 150MHz).
//
// In this case, the CPU_RATE will be 6.667L
// Uncomment the line: #define CPU_RATE 6.667L
//
// Example 2: 100 MHz devices:
// CLKIN is a 20MHz crystal.
//
// In step 1 the user specified PLLCR = 0xA for a
// 100Mhz CPU clock (SYSCLKOUT = 100MHz).
//
// In this case, the CPU_RATE will be 10.000L
// Uncomment the line: #define CPU_RATE 10.000L
//
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//
// Target device (in DSP2833x_Device.h) determines CPU frequency
// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
// (for 28332 and 28333). User does not have to change anything here.
//
#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
#define CPU_FRQ_150MHZ 0
#else
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
#endif
//
// Include Example Header Files
//
//
// Prototypes for global functions within the .c files.
//
#include "DSP2833x_GlobalPrototypes.h"
#include "DSP2833x_EPwm_defines.h" // Macros used for PWM examples.
#include "DSP2833x_Dma_defines.h" // Macros used for DMA examples.
#include "DSP2833x_I2c_defines.h" // Macros used for I2C examples.
#define PARTNO_28335 0xEF
#define PARTNO_28334 0xEE
#define PARTNO_28333 0xEA
#define PARTNO_28332 0xED
//
// Include files not used with DSP/BIOS
//
#ifndef DSP28_BIOS
#include "DSP2833x_DefaultIsr.h"
#endif
//
// DO NOT MODIFY THIS LINE.
//
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \
(long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EXAMPLES_H definition
//
// End of file
//

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// TI File $Revision: /main/5 $
// Checkin $Date: January 22, 2008 16:55:35 $
//###########################################################################
//
// FILE: DSP2833x_Device.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DEVICE_H
#define DSP2833x_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Defines
//
#define TARGET 1
//
// User To Select Target Device
//
#define DSP28_28335 TARGET // Selects '28335/'28235
#define DSP28_28334 0 // Selects '28334/'28234
#define DSP28_28333 0 // Selects '28333/'
#define DSP28_28332 0 // Selects '28332/'28232
//
// Common CPU Definitions
//
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define EINT asm(" clrc INTM")
#define DINT asm(" setc INTM")
#define ERTM asm(" clrc DBGM")
#define DRTM asm(" setc DBGM")
#define EALLOW asm(" EALLOW")
#define EDIS asm(" EDIS")
#define ESTOP0 asm(" ESTOP0")
#define M_INT1 0x0001
#define M_INT2 0x0002
#define M_INT3 0x0004
#define M_INT4 0x0008
#define M_INT5 0x0010
#define M_INT6 0x0020
#define M_INT7 0x0040
#define M_INT8 0x0080
#define M_INT9 0x0100
#define M_INT10 0x0200
#define M_INT11 0x0400
#define M_INT12 0x0800
#define M_INT13 0x1000
#define M_INT14 0x2000
#define M_DLOG 0x4000
#define M_RTOS 0x8000
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
//
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//
#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef int int16;
typedef long int32;
typedef long long int64;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef unsigned long long Uint64;
typedef float float32;
typedef long double float64;
#endif
//
// Included Peripheral Header Files
//
#include "DSP2833x_Adc.h" // ADC Registers
#include "DSP2833x_DevEmu.h" // Device Emulation Registers
#include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers
#include "DSP2833x_ECan.h" // Enhanced eCAN Registers
#include "DSP2833x_ECap.h" // Enhanced Capture
#include "DSP2833x_DMA.h" // DMA Registers
#include "DSP2833x_EPwm.h" // Enhanced PWM
#include "DSP2833x_EQep.h" // Enhanced QEP
#include "DSP2833x_Gpio.h" // General Purpose I/O Registers
#include "DSP2833x_I2c.h" // I2C Registers
#include "DSP2833x_Mcbsp.h" // McBSP
#include "DSP2833x_PieCtrl.h" // PIE Control Registers
#include "DSP2833x_PieVect.h" // PIE Vector Table
#include "DSP2833x_Spi.h" // SPI Registers
#include "DSP2833x_Sci.h" // SCI Registers
#include "DSP2833x_SysCtrl.h" // System Control/Power Modes
#include "DSP2833x_XIntrupt.h" // External Interrupts
#include "DSP2833x_Xintf.h" // XINTF External Interface
#if DSP28_28335 || DSP28_28333
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 1
#define DSP28_ECAP6 1
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28335 || DSP28_28333
#if DSP28_28334
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28334
#if DSP28_28332
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 0
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 0
#define DSP28_I2CA 1
#endif // end DSP28_28332
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEVICE_H definition
//
// End of file
//

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#ifndef SOURCE_DISPLAY_H_
#define SOURCE_DISPLAY_H_
#define ZONE6_DAT *(volatile Uint16*)0x00100001
#define ZONE6_COM *(volatile Uint16*)0x00100000
#define OLED_WIDTH (128U) // ER-OLEDM024 Vertical Pixel 0~127
#define OLED_HEIGHT (64U)
#define OLED_PAGE (8U) // ER-OLEDM024 Page 0~7
#define TXT_ENG_WIDTH (6U)
#define TXT_ENG_HEIGHT (12U)
#define TXT_TYPE_ENG (0U)
#define TXT_TYPE_ETC (1U)
#define TXT_MAX_LEN (22U)
#define TXT_LINE_LEN (5U)
#define OLED_LOAD_PROGRESS_X (14U)
#define OLED_LOAD_PROGRESS_Y (52U)
#define OLED_LOAD_PROGRESS_W (114U)
#define OLED_LOAD_PROGRESS_H (10U)
#define MODE_COMMAND (0U)
#define MODE_DATA (1U)
#define DIR_UP (1U)
#define DIR_DOWN (0U)
enum
{
OLED_LINE_TITLE = 0U,
OLED_LINE_1 = 14U,
OLED_LINE_2 = 27U,
OLED_LINE_3 = 40U,
OLED_LINE_4 = 53U
};
enum
{
OLED_ROW_0 = 0U,
OLED_ROW_1,
OLED_ROW_2,
OLED_ROW_3,
OLED_ROW_4
};
enum
{
OLED_PASS_DIGIT_1 = 0U,
OLED_PASS_DIGIT_2,
OLED_PASS_DIGIT_3,
OLED_PASS_DIGIT_4
};
typedef enum
{
OLED_PAGE_APU1 = 0U, // 0
OLED_PAGE_APU2, // 1
OLED_PAGE_MENU1, // 2
OLED_PAGE_MENU2, // 3
OLED_PAGE_TEMP, // 4
OLED_PAGE_SENSOR1, // 5
OLED_PAGE_SENSOR2, // 6
OLED_PAGE_SENSOR3, // 7
OLED_PAGE_SENSOR4, // 8
OLED_PAGE_WARNING1, // 9
OLED_PAGE_WARNING2, // 10
OLED_PAGE_FAULT1, // 11
OLED_PAGE_FAULT2, // 12
OLED_PAGE_FAULT3, // 13
OLED_PAGE_FAULT4, // 14
OLED_PAGE_FAULT5, // 15
OLED_PAGE_FAULT6, // 16
OLED_PAGE_RESET_ALARM, // 17
OLED_PAGE_PASSWORD, // 18
OLED_PAGE_MAINTENENCE, // 19
OLED_PAGE_KEY_TEST, // 20
OLED_PAGE_SHUTDOWN, // 21
OLED_PAGE_MAX
} EOledPage;
enum
{
OLED_MENU_APU = 0U, // 0
OLED_MENU_TEMP, // 1
OLED_MENU_SENSOR, // 2
OLED_MENU_WARNING, // 3
OLED_MENU_FAULT = 0U, // 0
OLED_MENU_RESET, // 1
OLED_MENU_DEBUG // 2
};
enum
{
OLED_LINE_FOCUS_1 = 0U,
OLED_LINE_FOCUS_2,
OLED_LINE_FOCUS_3,
OLED_LINE_FOCUS_4
};
typedef struct ClassPageHandler
{
Uint16 uiPage;
void (*pAction) (void); // PageTable ÂüÁ¶
} CPageHandler;
typedef struct ClassOledOperValue
{
Uint16 uiBuff[OLED_WIDTH][OLED_PAGE];
Uint16 uiPageNum;
Uint16 uiOldPageNum;
Uint16 uiFocusLine;
Uint16 uiPrevFocusLine;
Uint16 uiFocusDigit;
Uint16 uiProgressValue;
Uint16 uiProgressDone;
Uint16 uiAlarmPopCheck;
Uint16 uiAlreadyAlarm;
Uint16 uiPrevAlarmPage;
Uint16 uiResetAnswer;
int8 cStrBuff[TXT_LINE_LEN][TXT_MAX_LEN];
int8 cAlignBuffer[TXT_MAX_LEN];
struct
{
Uint16 TxtColor;
Uint16 BgColor;
} Color;
struct
{
Uint16 X1;
Uint16 Y1;
Uint16 X2;
Uint16 Y2;
} Point;
} COledOperValue;
void CInitXintf(void);
void CInitOled(void);
void COledReflash(Uint16 x, Uint16 y, Uint16 width, Uint16 height);
void CDisplayPostFail(void);
void CSetPage(Uint16 PageNum);
void CInitKeyOperValue(void);
void CInitializePage(void);
void COledBufferReset(void);
extern COledOperValue OledOperValue;
#endif /* SOURCE_DISPLAY_H_ */

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#ifndef SOURCE_OPER_H_
#define SOURCE_OPER_H_
typedef enum
{
APU_OPER_IDX_BOOT = 0U, // 0
APU_OPER_IDX_INITIAL, // 1
APU_OPER_IDX_POST, // 2
APU_OPER_IDX_EMERGENCY, // 3
APU_OPER_IDX_STANDBY, // 4
APU_OPER_IDX_START_CHECK, // 5
APU_OPER_IDX_ENGINE_PREHEAT, // 6
APU_OPER_IDX_CRANKING, // 7
APU_OPER_IDX_ENGINE_WARM_UP, // 8
APU_OPER_IDX_CHECK_OPERATION, // 9
APU_OPER_IDX_GENERATING, // 10
APU_OPER_IDX_ENGINE_STABLED, // 11
APU_OPER_IDX_ENGINE_STOP, // 12
APU_OPER_IDX_ENGINE_COOLDOWN // 13
} eApuOperIdx;
typedef enum
{
GCU_OPER_CMD_STOP = 0U, // 0
GCU_OPER_CMD_CRANKING, // 1
GCU_OPER_CMD_STOP_CRANKING, // 2
GCU_OPER_CMD_GENERATING // 3
} eGcuCmdIdx;
typedef enum
{
ECU_OPER_CMD_STOP = 0U, // 0
ECU_OPER_CMD_START, // 1
ECU_OPER_CMD_EMERGENCY // 2
} eEcuCmdIdx;
void CApuOperProcedure(void);
void CDebugModeProcedure(void);
Uint16 CApuSystemAlarmCheck(void);
void CSetApuOperIndex(eApuOperIdx idx);
eApuOperIdx CGetApuOperIndex(void);
void CLedControlProcedure(void);
int16 CGetEngCoolantTemperature(void);
Uint16 CGetGeneratorRpm(void);
Uint16 CGetEngineActualRpm(void);
#endif /* SOURCE_OPER_H_ */

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// TI File $Revision: /main/2 $
// Checkin $Date: August 14, 2007 16:32:29 $
//###########################################################################
//
// FILE: DSP2833x_Dma_defines.h
//
// TITLE: #defines used in DMA examples
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DMA_DEFINES_H
#define DSP2833x_DMA_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// MODE
//
// PERINTSEL bits
//
#define DMA_SEQ1INT 1
#define DMA_SEQ2INT 2
#define DMA_XINT1 3
#define DMA_XINT2 4
#define DMA_XINT3 5
#define DMA_XINT4 6
#define DMA_XINT5 7
#define DMA_XINT6 8
#define DMA_XINT7 9
#define DMA_XINT13 10
#define DMA_TINT0 11
#define DMA_TINT1 12
#define DMA_TINT2 13
#define DMA_MXEVTA 14
#define DMA_MREVTA 15
#define DMA_MXREVTB 16
#define DMA_MREVTB 17
//
// OVERINTE bit
//
#define OVRFLOW_DISABLE 0x0
#define OVEFLOW_ENABLE 0x1
//
// PERINTE bit
//
#define PERINT_DISABLE 0x0
#define PERINT_ENABLE 0x1
//
// CHINTMODE bits
//
#define CHINT_BEGIN 0x0
#define CHINT_END 0x1
//
// ONESHOT bits
//
#define ONESHOT_DISABLE 0x0
#define ONESHOT_ENABLE 0x1
//
// CONTINOUS bit
//
#define CONT_DISABLE 0x0
#define CONT_ENABLE 0x1
//
// SYNCE bit
//
#define SYNC_DISABLE 0x0
#define SYNC_ENABLE 0x1
//
// SYNCSEL bit
//
#define SYNC_SRC 0x0
#define SYNC_DST 0x1
//
// DATASIZE bit
//
#define SIXTEEN_BIT 0x0
#define THIRTYTWO_BIT 0x1
//
// CHINTE bit
//
#define CHINT_DISABLE 0x0
#define CHINT_ENABLE 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//
// End of file
//

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/*****************************************************************************/
/* string.h */
/* */
/* Copyright (c) 1993 Texas Instruments Incorporated */
/* http://www.ti.com/ */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in */
/* the documentation and/or other materials provided with the */
/* distribution. */
/* */
/* Neither the name of Texas Instruments Incorporated nor the names */
/* of its contributors may be used to endorse or promote products */
/* derived from this software without specific prior written */
/* permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* */
/*****************************************************************************/
#ifndef _STRING_H_
#define _STRING_H_
#include <_ti_config.h>
#if defined(__TMS320C2000__)
#if defined(__TMS320C28XX_CLA__)
#error "Header file <string.h> not supported by CLA compiler"
#endif
#endif
_TI_PROPRIETARY_PRAGMA("diag_push")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")") /* #includes required for implementation */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifndef NULL
#define NULL 0
#endif
#ifndef _SIZE_T_DECLARED
#define _SIZE_T_DECLARED
#ifdef __clang__
typedef __SIZE_TYPE__ size_t;
#else
typedef __SIZE_T_TYPE__ size_t;
#endif
#endif
_TI_PROPRIETARY_PRAGMA("diag_push")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
#if defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
defined(__TMS320C2000__) || \
defined(__MSP430__))
#define _OPT_IDECL
#else
#define _OPT_IDECL _IDECL
#endif
_TI_PROPRIETARY_PRAGMA("diag_pop")
_OPT_IDECL size_t strlen(const char *string);
_OPT_IDECL char *strcpy(char * __restrict dest,
const char * __restrict src);
_OPT_IDECL char *strncpy(char * __restrict dest,
const char * __restrict src, size_t n);
_OPT_IDECL char *strcat(char * __restrict string1,
const char * __restrict string2);
_OPT_IDECL char *strncat(char * __restrict dest,
const char * __restrict src, size_t n);
_OPT_IDECL char *strchr(const char *string, int c);
_OPT_IDECL char *strrchr(const char *string, int c);
_OPT_IDECL int strcmp(const char *string1, const char *string2);
_OPT_IDECL int strncmp(const char *string1, const char *string2, size_t n);
_CODE_ACCESS int strcoll(const char *string1, const char *_string2);
_CODE_ACCESS size_t strxfrm(char * __restrict to,
const char * __restrict from, size_t n);
_CODE_ACCESS char *strpbrk(const char *string, const char *chs);
_CODE_ACCESS size_t strspn(const char *string, const char *chs);
_CODE_ACCESS size_t strcspn(const char *string, const char *chs);
_CODE_ACCESS char *strstr(const char *string1, const char *string2);
_CODE_ACCESS char *strtok(char * __restrict str1,
const char * __restrict str2);
_CODE_ACCESS char *strerror(int _errno);
_CODE_ACCESS char *strdup(const char *string);
_CODE_ACCESS void *memmove(void *s1, const void *s2, size_t n);
_CODE_ACCESS void *memccpy(void *dest, const void *src, int ch, size_t count);
_TI_PROPRIETARY_PRAGMA("diag_push")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-16.4\")") /* false positives due to builtin declarations */
_CODE_ACCESS void *memcpy(void * __restrict s1,
const void * __restrict s2, size_t n);
_TI_PROPRIETARY_PRAGMA("diag_pop")
_OPT_IDECL int memcmp(const void *cs, const void *ct, size_t n);
_OPT_IDECL void *memchr(const void *cs, int c, size_t n);
#if (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \
defined(__ARM_ARCH) || defined(__ARP32__) || defined(__C7000__)
_CODE_ACCESS void *memset(void *mem, int ch, size_t length);
#else
_OPT_IDECL void *memset(void *mem, int ch, size_t length);
#endif
#if defined(__TMS320C2000__) && !defined(__TI_EABI__)
#ifndef __cplusplus
_TI_PROPRIETARY_PRAGMA("diag_push")
/* keep macros as direct #defines and not function-like macros or function
names surrounded by parentheses to support all original supported use cases
including taking their address through the macros and prefixing with
namespace macros */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
#define far_memcpy __memcpy_ff
#define far_strcpy strcpy_ff
_TI_PROPRIETARY_PRAGMA("diag_pop")
size_t far_strlen(const char *s);
char *strcpy_nf(char *s1, const char *s2);
char *strcpy_fn(char *s1, const char *s2);
char *strcpy_ff(char *s1, const char *s2);
char *far_strncpy(char *s1, const char *s2, size_t n);
char *far_strcat(char *s1, const char *s2);
char *far_strncat(char *s1, const char *s2, size_t n);
char *far_strchr(const char *s, int c);
char *far_strrchr(const char *s, int c);
int far_strcmp(const char *s1, const char *s2);
int far_strncmp(const char *s1, const char *s2, size_t n);
int far_strcoll(const char *s1, const char *s2);
size_t far_strxfrm(char *s1, const char *s2, size_t n);
char *far_strpbrk(const char *s1, const char *s2);
size_t far_strspn(const char *s1, const char *s2);
size_t far_strcspn(const char *s1, const char *s2);
char *far_strstr(const char *s1, const char *s2);
char *far_strtok(char *s1, const char *s2);
char *far_strerror(int _errno);
void *far_memmove(void *s1, const void *s2, size_t n);
void *__memcpy_nf (void *_s1, const void *_s2, size_t _n);
void *__memcpy_fn (void *_s1, const void *_s2, size_t _n);
void *__memcpy_ff (void *_s1, const void *_s2, size_t _n);
int far_memcmp(const void *s1, const void *s2, size_t n);
void *far_memchr(const void *s, int c, size_t n);
void *far_memset(void *s, int c, size_t n);
void *far_memlcpy(void *to, const void *from,
unsigned long n);
void *far_memlmove(void *to, const void *from,
unsigned long n);
#else /* __cplusplus */
long far_memlcpy(long to, long from, unsigned long n);
long far_memlmove(long to, long from, unsigned long n);
#endif /* __cplusplus */
#endif /* __TMS320C2000__ && !defined(__TI_EABI__) */
#ifdef __cplusplus
} /* extern "C" */
#endif /* __cplusplus */
#if defined(_INLINE) || defined(_STRING_IMPLEMENTATION)
#if (defined(_STRING_IMPLEMENTATION) || \
!(defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
defined(__TMS320C2000__) || \
defined(__MSP430__))))
_TI_PROPRIETARY_PRAGMA("diag_push")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */
#if (defined(_OPTIMIZE_FOR_SPACE) && (defined(__ARM_ARCH) || \
defined(__TMS320C2000__) || \
defined(__MSP430__)))
#define _OPT_IDEFN
#else
#define _OPT_IDEFN _IDEFN
#endif
_TI_PROPRIETARY_PRAGMA("diag_pop")
_TI_PROPRIETARY_PRAGMA("diag_push") /* functions */
/* MISRA exceptions to avoid changing inline versions of the functions that
would be linked in instead of included inline at different mf levels */
/* these functions are very well-tested, stable, and efficient; it would
introduce a high risk to implement new, separate MISRA versions just for the
inline headers */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-5.7\")") /* keep names intact */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-6.1\")") /* false positive on use of char type */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-8.5\")") /* need to define inline functions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.1\")") /* use implicit casts */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-10.3\")") /* need casts */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-11.5\")") /* casting away const required for standard impl */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.1\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.2\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.4\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.5\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.6\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-12.13\")") /* ++/-- needed for reasonable implementation */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-13.1\")") /* avoid changing expressions */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.7\")") /* use multiple return points */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.8\")") /* use non-compound statements */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-14.9\")") /* use non-compound statements */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.4\")") /* pointer arithmetic needed for reasonable impl */
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-17.6\")") /* false positive returning pointer-typed param */
#if defined(_INLINE) || defined(_STRLEN)
_OPT_IDEFN size_t strlen(const char *string)
{
size_t n = (size_t)-1;
const char *s = string;
do n++; while (*s++);
return n;
}
#endif /* _INLINE || _STRLEN */
#if defined(_INLINE) || defined(_STRCPY)
_OPT_IDEFN char *strcpy(char * __restrict dest, const char * __restrict src)
{
char *d = dest;
const char *s = src;
while ((*d++ = *s++));
return dest;
}
#endif /* _INLINE || _STRCPY */
#if defined(_INLINE) || defined(_STRNCPY)
_OPT_IDEFN char *strncpy(char * __restrict dest,
const char * __restrict src,
size_t n)
{
if (n)
{
char *d = dest;
const char *s = src;
while ((*d++ = *s++) && --n); /* COPY STRING */
if (n-- > 1) do *d++ = '\0'; while (--n); /* TERMINATION PADDING */
}
return dest;
}
#endif /* _INLINE || _STRNCPY */
#if defined(_INLINE) || defined(_STRCAT)
_OPT_IDEFN char *strcat(char * __restrict string1,
const char * __restrict string2)
{
char *s1 = string1;
const char *s2 = string2;
while (*s1) s1++; /* FIND END OF STRING */
while ((*s1++ = *s2++)); /* APPEND SECOND STRING */
return string1;
}
#endif /* _INLINE || _STRCAT */
#if defined(_INLINE) || defined(_STRNCAT)
_OPT_IDEFN char *strncat(char * __restrict dest,
const char * __restrict src, size_t n)
{
if (n)
{
char *d = dest;
const char *s = src;
while (*d) d++; /* FIND END OF STRING */
while (n--)
if (!(*d++ = *s++)) return dest; /* APPEND SECOND STRING */
*d = 0;
}
return dest;
}
#endif /* _INLINE || _STRNCAT */
#if defined(_INLINE) || defined(_STRCHR)
_OPT_IDEFN char *strchr(const char *string, int c)
{
char tch, ch = c;
const char *s = string;
for (;;)
{
if ((tch = *s) == ch) return (char *) s;
if (!tch) return (char *) 0;
s++;
}
}
#endif /* _INLINE || _STRCHR */
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_OPT_IDEFN char *strrchr(const char *string, int c)
{
char tch, ch = c;
char *result = 0;
const char *s = string;
for (;;)
{
if ((tch = *s) == ch) result = (char *) s;
if (!tch) break;
s++;
}
return result;
}
#endif /* _INLINE || _STRRCHR */
#if defined(_INLINE) || defined(_STRCMP)
_OPT_IDEFN int strcmp(const char *string1, const char *string2)
{
int c1, res;
for (;;)
{
c1 = (unsigned char)*string1++;
res = c1 - (unsigned char)*string2++;
if (c1 == 0 || res != 0) break;
}
return res;
}
#endif /* _INLINE || _STRCMP */
#if defined(_INLINE) || defined(_STRNCMP)
_OPT_IDEFN int strncmp(const char *string1, const char *string2, size_t n)
{
if (n)
{
const char *s1 = string1;
const char *s2 = string2;
unsigned char cp;
int result;
do
if ((result = (unsigned char)*s1++ - (cp = (unsigned char)*s2++)))
return result;
while (cp && --n);
}
return 0;
}
#endif /* _INLINE || _STRNCMP */
#if defined(_INLINE) || defined(_MEMCMP)
_OPT_IDEFN int memcmp(const void *cs, const void *ct, size_t n)
{
if (n)
{
const unsigned char *mem1 = (unsigned char *)cs;
const unsigned char *mem2 = (unsigned char *)ct;
int cp1, cp2;
while ((cp1 = *mem1++) == (cp2 = *mem2++) && --n);
return cp1 - cp2;
}
return 0;
}
#endif /* _INLINE || _MEMCMP */
#if defined(_INLINE) || defined(_MEMCHR)
_OPT_IDEFN void *memchr(const void *cs, int c, size_t n)
{
if (n)
{
const unsigned char *mem = (unsigned char *)cs;
unsigned char ch = c;
do
if ( *mem == ch ) return (void *)mem;
else mem++;
while (--n);
}
return NULL;
}
#endif /* _INLINE || _MEMCHR */
#if (((defined(_INLINE) || defined(_MEMSET)) && \
!(defined(_TMS320C6X) && !defined(__C6X_MIGRATION__))) && \
!defined(__ARM_ARCH) && !defined(__ARP32__) && !defined(__C7000__))
_OPT_IDEFN void *memset(void *mem, int ch, size_t length)
{
char *m = (char *)mem;
while (length--) *m++ = ch;
return mem;
}
#endif /* _INLINE || _MEMSET */
_TI_PROPRIETARY_PRAGMA("diag_pop")
#endif /* (_STRING_IMPLEMENTATION || !(_OPTIMIZE_FOR_SPACE && __ARM_ARCH)) */
#endif /* (_INLINE || _STRING_IMPLEMENTATION) */
/*----------------------------------------------------------------------------*/
/* If sys/cdefs.h is available, go ahead and include it. xlocale.h assumes */
/* this file will have already included sys/cdefs.h. */
/*----------------------------------------------------------------------------*/
#if __has_include(<sys/cdefs.h>)
#include <sys/cdefs.h>
#endif
/*----------------------------------------------------------------------------*/
/* Include xlocale/_string.h if POSIX is enabled. This will expose the */
/* xlocale string interface. */
/*----------------------------------------------------------------------------*/
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
__BEGIN_DECLS
#include <xlocale/_string.h>
__END_DECLS
#endif
#if defined(__POSIX_VISIBLE) && __POSIX_VISIBLE >= 200809
_CODE_ACCESS char *stpcpy(char * __restrict, const char * __restrict);
_CODE_ACCESS char *stpncpy(char * __restrict, const char * __restrict, size_t);
#endif
_TI_PROPRIETARY_PRAGMA("diag_pop")
#endif /* ! _STRING_H_ */

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/*****************************************************************************/
/* linkage.h */
/* */
/* Copyright (c) 1998 Texas Instruments Incorporated */
/* http://www.ti.com/ */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
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/* Redistributions in binary form must reproduce the above copyright */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* */
/*****************************************************************************/
#ifndef _LINKAGE
#define _LINKAGE
#pragma diag_push
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */
/* No modifiers needed to access code */
#define _CODE_ACCESS
/*--------------------------------------------------------------------------*/
/* Define _DATA_ACCESS ==> how to access RTS global or static data */
/*--------------------------------------------------------------------------*/
#define _DATA_ACCESS
#define _DATA_ACCESS_NEAR
/*--------------------------------------------------------------------------*/
/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */
/*--------------------------------------------------------------------------*/
#ifndef _OPTIMIZE_FOR_SPACE
#define _OPTIMIZE_FOR_SPACE 1
#endif
/*--------------------------------------------------------------------------*/
/* Define _IDECL ==> how inline functions are declared */
/*--------------------------------------------------------------------------*/
#ifdef _INLINE
#define _IDECL static __inline
#define _IDEFN static __inline
#else
#define _IDECL extern _CODE_ACCESS
#define _IDEFN _CODE_ACCESS
#endif
#pragma diag_pop
#endif /* _LINKAGE */

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/*****************************************************************************/
/* _ti_config.h */
/* */
/* Copyright (c) 2017 Texas Instruments Incorporated */
/* http://www.ti.com/ */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* Redistributions of source code must retain the above copyright */
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/* */
/* Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in */
/* the documentation and/or other materials provided with the */
/* distribution. */
/* */
/* Neither the name of Texas Instruments Incorporated nor the names */
/* of its contributors may be used to endorse or promote products */
/* derived from this software without specific prior written */
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/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* */
/*****************************************************************************/
#ifndef __TI_CONFIG_H
#define __TI_CONFIG_H
/*Unsupported pragmas are omitted */
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# pragma diag_push
# pragma CHECK_MISRA("-19.7")
# pragma CHECK_MISRA("-19.4")
# pragma CHECK_MISRA("-19.1")
# pragma CHECK_MISRA("-19.15")
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# pragma diag_pop
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#endif
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_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.4\")")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.1\")")
_TI_PROPRIETARY_PRAGMA("CHECK_MISRA(\"-19.6\")")
/* Hide uses of the TI proprietary macros behind other macros.
Implementations that don't implement these features should leave
these macros undefined. */
#ifdef __TI_COMPILER_VERSION__
# ifdef __TI_STRICT_ANSI_MODE__
# define __TI_PROPRIETARY_STRICT_ANSI_MACRO __TI_STRICT_ANSI_MODE__
# else
# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
# endif
# ifdef __TI_STRICT_FP_MODE__
# define __TI_PROPRIETARY_STRICT_FP_MACRO __TI_STRICT_FP_MODE__
# else
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
# endif
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# else
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# endif
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# undef __TI_PROPRIETARY_STRICT_ANSI_MACRO
# undef __TI_PROPRIETARY_STRICT_FP_MACRO
#endif
/* Common definitions */
#if defined(__cplusplus)
/* C++ */
# if (__cplusplus >= 201103L)
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# define _TI_NORETURN [[noreturn]]
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# else
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# define _TI_NORETURN __attribute__((noreturn))
# define _TI_NOEXCEPT throw()
# endif
#else
/* C */
# if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L)
/* C11 */
# define _TI_NORETURN _Noreturn
# else
/* C89/C99 */
# define _TI_NORETURN __attribute__((noreturn))
# endif
# define _TI_NOEXCEPT
#endif
#if defined(__cplusplus) && (__cplusplus >= 201103L)
# define _TI_CPP11LIB 1
#endif
#if defined(__cplusplus) && (__cplusplus >= 201402L)
# define _TI_CPP14LIB 1
#endif
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || \
defined(_TI_CPP11LIB)
# define _TI_C99LIB 1
#endif
#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) || \
defined(_TI_CPP14LIB)
# define _TI_C11LIB 1
#endif
/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It
is intended to be used for functions like abort and atexit that are supposed
to be declared noexcept only in C++14 mode. */
#ifdef _TI_CPP14LIB
# define _TI_NOEXCEPT_CPP14 noexcept
#else
# define _TI_NOEXCEPT_CPP14
#endif
/* Target-specific definitions */
#include <linkage.h>
_TI_PROPRIETARY_PRAGMA("diag_pop")
#endif /* ifndef __TI_CONFIG_H */

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// TI File $Revision: /main/11 $
// Checkin $Date: June 23, 2008 11:34:15 $
//###########################################################################
//
// FILE: DSP2833x_DMA.h
//
// TITLE: DSP2833x DMA Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DMA_H
#define DSP2833x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Channel MODE register bit definitions
//
struct MODE_BITS { // bits description
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
// 0 no interrupt
// 1 SEQ1INT & ADCSYNC
// 2 SEQ2INT
// 3 XINT1
// 4 XINT2
// 5 XINT3
// 6 XINT4
// 7 XINT5
// 8 XINT6
// 9 XINT7
// 10 XINT13
// 11 TINT0
// 12 TINT1
// 13 TINT2
// 14 MXEVTA & MXSYNCA
// 15 MREVTA & MRSYNCA
// 16 MXEVTB & MXSYNCB
// 17 MREVTB & MRSYNCB
// 18 ePWM1SOCA
// 19 ePWM1SOCB
// 20 ePWM2SOCA
// 21 ePWM2SOCB
// 22 ePWM3SOCA
// 23 ePWM3SOCB
// 24 ePWM4SOCA
// 25 ePWM4SOCB
// 26 ePWM5SOCA
// 27 ePWM5SOCB
// 28 ePWM6SOCA
// 29 ePWM6SOCB
// 30:31 no interrupt
Uint16 rsvd1:2; // 6:5 (R=0:0)
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
// 0 overflow interrupt disabled
// 1 overflow interrupt enabled
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
// 0 peripheral interrupt disabled
// 1 peripheral interrupt enabled
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
// 0 generate interrupt at beginning of new
// transfer
// 1 generate interrupt at end of transfer
Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
// 0 only interrupt event triggers single
// burst transfer
// 1 first interrupt triggers burst,
// continue until transfer count is zero
Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
// 0 stop when transfer count is zero
// 1 re-initialize when transfer count is
// zero
Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
// 0 ignore selected interrupt sync signal
// 1 enable selected interrupt sync signal
Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
// 0 sync signal controls source wrap
// counter
// 1 sync signal controls destination wrap
// counter
Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
// 0 16-bit data transfer size
// 1 32-bit data transfer size
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
// 0 channel interrupt disabled
// 1 channel interrupt enabled
};
union MODE_REG {
Uint16 all;
struct MODE_BITS bit;
};
//
// Channel CONTROL register bit definitions
//
struct CONTROL_BITS { // bits description
Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
// 0 no interrupt pending
// 1 interrupt pending
Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
// 0 no sync pending
// 1 sync pending
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
// 0 no sync error
// 1 sync error detected
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
// 0 no transfer in progress or pending
// 1 transfer in progress or pending
Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
// 0 no burst in progress or pending
// 1 burst in progress or pending
Uint16 RUNSTS:1; // 13 Run Status Bit (R):
// 0 channel not running or halted
// 1 channel running
Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
// 0 no overflow event
// 1 overflow event
Uint16 rsvd1:1; // 15 (R=0)
};
union CONTROL_REG {
Uint16 all;
struct CONTROL_BITS bit;
};
//
// DMACTRL register bit definitions
//
struct DMACTRL_BITS { // bits description
Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
Uint16 rsvd1:14; // 15:2 (R=0:0)
};
union DMACTRL_REG {
Uint16 all;
struct DMACTRL_BITS bit;
};
//
// DEBUGCTRL register bit definitions
//
struct DEBUGCTRL_BITS { // bits description
Uint16 rsvd1:15; // 14:0 (R=0:0)
Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
// 0 halt after current read-write operation
// 1 continue running
};
union DEBUGCTRL_REG {
Uint16 all;
struct DEBUGCTRL_BITS bit;
};
//
// PRIORITYCTRL1 register bit definitions
//
struct PRIORITYCTRL1_BITS { // bits description
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
// 0 same priority as all other channels
// 1 highest priority channel
Uint16 rsvd1:15; // 15:1 (R=0:0)
};
union PRIORITYCTRL1_REG {
Uint16 all;
struct PRIORITYCTRL1_BITS bit;
};
//
// PRIORITYSTAT register bit definitions:
//
struct PRIORITYSTAT_BITS { // bits description
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
// 0,0,0 no channel active
// 0,0,1 Ch1 channel active
// 0,1,0 Ch2 channel active
// 0,1,1 Ch3 channel active
// 1,0,0 Ch4 channel active
// 1,0,1 Ch5 channel active
// 1,1,0 Ch6 channel active
Uint16 rsvd1:1; // 3 (R=0)
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
// 0,0,0 no channel active & interrupted by Ch1
// 0,0,1 cannot occur
// 0,1,0 Ch2 was active and interrupted by Ch1
// 0,1,1 Ch3 was active and interrupted by Ch1
// 1,0,0 Ch4 was active and interrupted by Ch1
// 1,0,1 Ch5 was active and interrupted by Ch1
// 1,1,0 Ch6 was active and interrupted by Ch1
Uint16 rsvd2:9; // 15:7 (R=0:0)
};
union PRIORITYSTAT_REG {
Uint16 all;
struct PRIORITYSTAT_BITS bit;
};
//
// Burst Size
//
struct BURST_SIZE_BITS { // bits description
Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_SIZE_REG {
Uint16 all;
struct BURST_SIZE_BITS bit;
};
//
// Burst Count
//
struct BURST_COUNT_BITS { // bits description
Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_COUNT_REG {
Uint16 all;
struct BURST_COUNT_BITS bit;
};
//
// DMA Channel Registers:
//
struct CH_REGS {
union MODE_REG MODE; // Mode Register
union CONTROL_REG CONTROL; // Control Register
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
//
// Source Burst Step Register
//
int16 SRC_BURST_STEP;
//
// Destination Burst Step Register
//
int16 DST_BURST_STEP;
Uint16 TRANSFER_SIZE; // Transfer Size Register
Uint16 TRANSFER_COUNT; // Transfer Count Register
//
// Source Transfer Step Register
//
int16 SRC_TRANSFER_STEP;
//
// Destination Transfer Step Register
//
int16 DST_TRANSFER_STEP;
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
int16 SRC_WRAP_STEP; // Source Wrap Step Register
//
// Destination Wrap Size Register
//
Uint16 DST_WRAP_SIZE;
//
// Destination Wrap Count Register
//
Uint16 DST_WRAP_COUNT;
//
// Destination Wrap Step Register
//
int16 DST_WRAP_STEP;
//
// Source Begin Address Shadow Register
//
Uint32 SRC_BEG_ADDR_SHADOW;
//
// Source Address Shadow Register
//
Uint32 SRC_ADDR_SHADOW;
//
// Source Begin Address Active Register
//
Uint32 SRC_BEG_ADDR_ACTIVE;
//
// Source Address Active Register
//
Uint32 SRC_ADDR_ACTIVE;
//
// Destination Begin Address Shadow Register
//
Uint32 DST_BEG_ADDR_SHADOW;
//
// Destination Address Shadow Register
//
Uint32 DST_ADDR_SHADOW;
//
// Destination Begin Address Active Register
//
Uint32 DST_BEG_ADDR_ACTIVE;
//
// Destination Address Active Register
//
Uint32 DST_ADDR_ACTIVE;
};
//
// DMA Registers
//
struct DMA_REGS {
union DMACTRL_REG DMACTRL; // DMA Control Register
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
Uint16 rsvd0; // reserved
Uint16 rsvd1; //
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
Uint16 rsvd2; //
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
Uint16 rsvd3[25]; //
struct CH_REGS CH1; // DMA Channel 1 Registers
struct CH_REGS CH2; // DMA Channel 2 Registers
struct CH_REGS CH3; // DMA Channel 3 Registers
struct CH_REGS CH4; // DMA Channel 4 Registers
struct CH_REGS CH5; // DMA Channel 5 Registers
struct CH_REGS CH6; // DMA Channel 6 Registers
};
//
// External References & Function Declarations
//
extern volatile struct DMA_REGS DmaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DMA_H definition
//
// End of file
//

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// TI File $Revision: /main/2 $
// Checkin $Date: March 16, 2007 09:00:21 $
//###########################################################################
//
// FILE: DSP2833x_PieVect.h
//
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_PIE_VECT_H
#define DSP2833x_PIE_VECT_H
#ifdef __cplusplus
extern "C" {
#endif
//
// PIE Interrupt Vector Table Definition
//
//
// Typedef used to create a user type called PINT (pointer to interrupt)
//
typedef interrupt void(*PINT)(void);
//
// Vector Table Define
//
struct PIE_VECT_TABLE {
//
// Reset is never fetched from this table. It will always be fetched from
// 0x3FFFC0 in boot ROM
//
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
//
// Non-Peripheral Interrupts
//
PINT XINT13; // XINT13 / CPU-Timer1
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
//
// Group 1 PIE Peripheral Vectors
//
PINT SEQ1INT;
PINT SEQ2INT;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
//
// Group 2 PIE Peripheral Vectors
//
PINT EPWM1_TZINT; // EPWM-1
PINT EPWM2_TZINT; // EPWM-2
PINT EPWM3_TZINT; // EPWM-3
PINT EPWM4_TZINT; // EPWM-4
PINT EPWM5_TZINT; // EPWM-5
PINT EPWM6_TZINT; // EPWM-6
PINT rsvd2_7;
PINT rsvd2_8;
//
// Group 3 PIE Peripheral Vectors
//
PINT EPWM1_INT; // EPWM-1
PINT EPWM2_INT; // EPWM-2
PINT EPWM3_INT; // EPWM-3
PINT EPWM4_INT; // EPWM-4
PINT EPWM5_INT; // EPWM-5
PINT EPWM6_INT; // EPWM-6
PINT rsvd3_7;
PINT rsvd3_8;
//
// Group 4 PIE Peripheral Vectors
//
PINT ECAP1_INT; // ECAP-1
PINT ECAP2_INT; // ECAP-2
PINT ECAP3_INT; // ECAP-3
PINT ECAP4_INT; // ECAP-4
PINT ECAP5_INT; // ECAP-5
PINT ECAP6_INT; // ECAP-6
PINT rsvd4_7;
PINT rsvd4_8;
//
// Group 5 PIE Peripheral Vectors
//
PINT EQEP1_INT; // EQEP-1
PINT EQEP2_INT; // EQEP-2
PINT rsvd5_3;
PINT rsvd5_4;
PINT rsvd5_5;
PINT rsvd5_6;
PINT rsvd5_7;
PINT rsvd5_8;
//
// Group 6 PIE Peripheral Vectors
//
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT MRINTB; // McBSP-B
PINT MXINTB; // McBSP-B
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
//
// Group 7 PIE Peripheral Vectors
//
PINT DINTCH1; // DMA
PINT DINTCH2; // DMA
PINT DINTCH3; // DMA
PINT DINTCH4; // DMA
PINT DINTCH5; // DMA
PINT DINTCH6; // DMA
PINT rsvd7_7;
PINT rsvd7_8;
//
// Group 8 PIE Peripheral Vectors
//
PINT I2CINT1A; // I2C-A
PINT I2CINT2A; // I2C-A
PINT rsvd8_3;
PINT rsvd8_4;
PINT SCIRXINTC; // SCI-C
PINT SCITXINTC; // SCI-C
PINT rsvd8_7;
PINT rsvd8_8;
//
// Group 9 PIE Peripheral Vectors
//
PINT SCIRXINTA; // SCI-A
PINT SCITXINTA; // SCI-A
PINT SCIRXINTB; // SCI-B
PINT SCITXINTB; // SCI-B
PINT ECAN0INTA; // eCAN-A
PINT ECAN1INTA; // eCAN-A
PINT ECAN0INTB; // eCAN-B
PINT ECAN1INTB; // eCAN-B
//
// Group 10 PIE Peripheral Vectors
//
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
//
// Group 11 PIE Peripheral Vectors
//
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
//
// Group 12 PIE Peripheral Vectors
//
PINT XINT3; // External interrupt
PINT XINT4;
PINT XINT5;
PINT XINT6;
PINT XINT7;
PINT rsvd12_6;
PINT LVF; // Latched overflow
PINT LUF; // Latched underflow
};
//
// PIE Interrupt Vector Table External References & Function Declarations
//
extern volatile struct PIE_VECT_TABLE PieVectTable;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_VECT_H definition
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:39 $
//###########################################################################
//
// FILE: DSP2833x_XIntrupt.h
//
// TITLE: DSP2833x Device External Interrupt Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_XINTRUPT_H
#define DSP2833x_XINTRUPT_H
#ifdef __cplusplus
extern "C" {
#endif
struct XINTCR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 rsvd1:1; // 1 reserved
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
Uint16 rsvd2:12; //15:4 reserved
};
union XINTCR_REG {
Uint16 all;
struct XINTCR_BITS bit;
};
struct XNMICR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
Uint16 rsvd2:12; // 15:4 reserved
};
union XNMICR_REG {
Uint16 all;
struct XNMICR_BITS bit;
};
//
// External Interrupt Register File
//
struct XINTRUPT_REGS {
union XINTCR_REG XINT1CR;
union XINTCR_REG XINT2CR;
union XINTCR_REG XINT3CR;
union XINTCR_REG XINT4CR;
union XINTCR_REG XINT5CR;
union XINTCR_REG XINT6CR;
union XINTCR_REG XINT7CR;
union XNMICR_REG XNMICR;
Uint16 XINT1CTR;
Uint16 XINT2CTR;
Uint16 rsvd[5];
Uint16 XNMICTR;
};
//
// External Interrupt References & Function Declarations
//
extern volatile struct XINTRUPT_REGS XIntruptRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//
// End of file
//

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// TI File $Revision: /main/2 $
// Checkin $Date: April 16, 2008 17:16:47 $
//###########################################################################
//
// FILE: DSP2833x_I2cExample.h
//
// TITLE: 2833x I2C Example Code Definitions.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_I2C_DEFINES_H
#define DSP2833x_I2C_DEFINES_H
//
// Defines
//
//
// Error Messages
//
#define I2C_ERROR 0xFFFF
#define I2C_ARB_LOST_ERROR 0x0001
#define I2C_NACK_ERROR 0x0002
#define I2C_BUS_BUSY_ERROR 0x1000
#define I2C_STP_NOT_READY_ERROR 0x5555
#define I2C_NO_FLAGS 0xAAAA
#define I2C_SUCCESS 0x0000
//
// Clear Status Flags
//
#define I2C_CLR_AL_BIT 0x0001
#define I2C_CLR_NACK_BIT 0x0002
#define I2C_CLR_ARDY_BIT 0x0004
#define I2C_CLR_RRDY_BIT 0x0008
#define I2C_CLR_SCD_BIT 0x0020
//
// Interrupt Source Messages
//
#define I2C_NO_ISRC 0x0000
#define I2C_ARB_ISRC 0x0001
#define I2C_NACK_ISRC 0x0002
#define I2C_ARDY_ISRC 0x0003
#define I2C_RX_ISRC 0x0004
#define I2C_TX_ISRC 0x0005
#define I2C_SCD_ISRC 0x0006
#define I2C_AAS_ISRC 0x0007
//
// I2CMSG structure defines
//
#define I2C_NO_STOP 0
#define I2C_YES_STOP 1
#define I2C_RECEIVE 0
#define I2C_TRANSMIT 1
#define I2C_MAX_BUFFER_SIZE 16
//
// I2C Slave State defines
//
#define I2C_NOTSLAVE 0
#define I2C_ADDR_AS_SLAVE 1
#define I2C_ST_MSG_READY 2
//
// I2C Slave Receiver messages defines
//
#define I2C_SND_MSG1 1
#define I2C_SND_MSG2 2
//
// I2C State defines
//
#define I2C_IDLE 0
#define I2C_SLAVE_RECEIVER 1
#define I2C_SLAVE_TRANSMITTER 2
#define I2C_MASTER_RECEIVER 3
#define I2C_MASTER_TRANSMITTER 4
//
// I2C Message Commands for I2CMSG struct
//
#define I2C_MSGSTAT_INACTIVE 0x0000
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
#define I2C_MSGSTAT_RESTART 0x0022
#define I2C_MSGSTAT_READ_BUSY 0x0023
//
// Generic defines
//
#define I2C_TRUE 1
#define I2C_FALSE 0
#define I2C_YES 1
#define I2C_NO 0
#define I2C_DUMMY_BYTE 0
//
// Structures
//
//
// I2C Message Structure
//
struct I2CMSG
{
Uint16 MsgStatus; // Word stating what state msg is in:
// I2C_MSGCMD_INACTIVE = do not send msg
// I2C_MSGCMD_BUSY = msg start has been sent,
// awaiting stop
// I2C_MSGCMD_SEND_WITHSTOP = command to send
// master trans msg complete with a stop bit
// I2C_MSGCMD_SEND_NOSTOP = command to send
// master trans msg without the stop bit
// I2C_MSGCMD_RESTART = command to send a restart
// as a master receiver with a stop bit
Uint16 SlaveAddress; // I2C address of slave msg is intended for
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
//
// EEPROM address of data associated with msg (high byte)
//
Uint16 MemoryHighAddr;
//
// EEPROM address of data associated with msg (low byte)
//
Uint16 MemoryLowAddr;
//
// Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to
// the FIFO's
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];
};
#endif // end of DSP2833x_I2C_DEFINES_H definition
//
// End of file
//

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// TI File $Revision: /main/4 $
// Checkin $Date: April 15, 2009 10:05:17 $
//###########################################################################
//
// FILE: DSP2833x_DevEmu.h
//
// TITLE: DSP2833x Device Emulation Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DEV_EMU_H
#define DSP2833x_DEV_EMU_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Device Emulation Register Bit Definitions:
//
//
// Device Configuration Register Bit Definitions
//
struct DEVICECNF_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 VMAPS:1; // 3 VMAP Status
Uint16 rsvd2:1; // 4 reserved
Uint16 XRSn:1; // 5 XRSn Signal Status
Uint16 rsvd3:10; // 15:6
Uint16 rsvd4:3; // 18:16
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
Uint16 rsvd5:7; // 26:20 reserved
Uint16 TRSTN:1; // 27 Status of TRSTn signal
Uint16 rsvd6:4; // 31:28 reserved
};
union DEVICECNF_REG {
Uint32 all;
struct DEVICECNF_BITS bit;
};
//
// CLASSID
//
struct CLASSID_BITS { // bits description
Uint16 CLASSNO:8; // 7:0 Class Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union CLASSID_REG {
Uint16 all;
struct CLASSID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF; // device configuration
union CLASSID_REG CLASSID; // Class ID
Uint16 REVID; // Device ID
Uint16 PROTSTART; // Write-Read protection start
Uint16 PROTRANGE; // Write-Read protection range
Uint16 rsvd2[202];
};
//
// PARTID
//
struct PARTID_BITS { // bits description
Uint16 PARTNO:8; // 7:0 Part Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union PARTID_REG {
Uint16 all;
struct PARTID_BITS bit;
};
struct PARTID_REGS {
union PARTID_REG PARTID; // Part ID
};
//
// Device Emulation Register References & Function Declarations
//
extern volatile struct DEV_EMU_REGS DevEmuRegs;
extern volatile struct PARTID_REGS PartIdRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEV_EMU_H definition
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:07 $
//###########################################################################
//
// FILE: DSP2833x_ECap.h
//
// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_ECAP_H
#define DSP2833x_ECAP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Capture control register 1 bit definitions
//
struct ECCTL1_BITS { // bits description
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap
// Event
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union ECCTL1_REG {
Uint16 all;
struct ECCTL1_BITS bit;
};
//
// In V1.1 the STOPVALUE bit field was changed to
// STOP_WRAP. This correlated to a silicon change from
// F2833x Rev 0 to Rev A.
//
//
// Capture control register 2 bit definitions
//
struct ECCTL2_BITS { // bits description
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
Uint16 REARM:1; // 3 One-shot re-arm
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
Uint16 SWSYNC:1; // 8 SW forced counter sync
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
Uint16 APWMPOL:1; // 10 APWM output polarity select
Uint16 rsvd1:5; // 15:11
};
union ECCTL2_REG {
Uint16 all;
struct ECCTL2_BITS bit;
};
//
// ECAP interrupt enable register bit definitions
//
struct ECEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
Uint16 rsvd2:8; // 15:8 reserved
};
union ECEINT_REG {
Uint16 all;
struct ECEINT_BITS bit;
};
//
// ECAP interrupt flag register bit definitions
//
struct ECFLG_BITS { // bits description
Uint16 INT:1; // 0 Global Flag
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
Uint16 rsvd2:8; // 15:8 reserved
};
union ECFLG_REG {
Uint16 all;
struct ECFLG_BITS bit;
};
struct ECAP_REGS {
Uint32 TSCTR; // Time stamp counter
Uint32 CTRPHS; // Counter phase
Uint32 CAP1; // Capture 1
Uint32 CAP2; // Capture 2
Uint32 CAP3; // Capture 3
Uint32 CAP4; // Capture 4
Uint16 rsvd1[8]; // reserved
union ECCTL1_REG ECCTL1; // Capture Control Reg 1
union ECCTL2_REG ECCTL2; // Capture Control Reg 2
union ECEINT_REG ECEINT; // ECAP interrupt enable
union ECFLG_REG ECFLG; // ECAP interrupt flags
union ECFLG_REG ECCLR; // ECAP interrupt clear
union ECEINT_REG ECFRC; // ECAP interrupt force
Uint16 rsvd2[6]; // reserved
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct ECAP_REGS ECap1Regs;
extern volatile struct ECAP_REGS ECap2Regs;
extern volatile struct ECAP_REGS ECap3Regs;
extern volatile struct ECAP_REGS ECap4Regs;
extern volatile struct ECAP_REGS ECap5Regs;
extern volatile struct ECAP_REGS ECap6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ECAP_H definition
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:24 $
//###########################################################################
//
// FILE: DSP2833x_PieCtrl.h
//
// TITLE: DSP2833x Device PIE Control Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_PIE_CTRL_H
#define DSP2833x_PIE_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//
// PIE Control Register Bit Definitions
//
//
// PIECTRL: Register bit definitions
//
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
//
// PIEIER: Register bit definitions
//
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
//
// PIEIFR: Register bit definitions
//
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
//
// PIEACK: Register bit definitions
//
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//
// PIE Control Register File
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECTRL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE int1 IER register
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE int10 IER register
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
union PIEIER_REG PIEIER11; // PIE int11 IER register
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
union PIEIER_REG PIEIER12; // PIE int12 IER register
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
};
//
// Defines
//
#define PIEACK_GROUP1 0x0001
#define PIEACK_GROUP2 0x0002
#define PIEACK_GROUP3 0x0004
#define PIEACK_GROUP4 0x0008
#define PIEACK_GROUP5 0x0010
#define PIEACK_GROUP6 0x0020
#define PIEACK_GROUP7 0x0040
#define PIEACK_GROUP8 0x0080
#define PIEACK_GROUP9 0x0100
#define PIEACK_GROUP10 0x0200
#define PIEACK_GROUP11 0x0400
#define PIEACK_GROUP12 0x0800
//
// PIE Control Registers External References & Function Declarations
//
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_CTRL_H definition
//
// End of file
//

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#ifndef CFONT_H
#define CFONT_H
const Uint16 EngFontTable[96][9] =
{
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // 공백
{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x00, 0x10, 0x40, 0x00 }, // !
{ 0x28, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // "
{ 0x14, 0x57, 0xCA, 0x28, 0xAF, 0xD4, 0x51, 0x40, 0x00 }, // #
{ 0x10, 0xE5, 0x54, 0x30, 0x61, 0x45, 0x54, 0xE1, 0x00 }, // $
{ 0x25, 0x55, 0x8A, 0x10, 0x42, 0x8D, 0x55, 0x20, 0x00 }, // %
{ 0x31, 0x24, 0x92, 0x31, 0x54, 0x92, 0x48, 0xD0, 0x00 }, // &
{ 0x10, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // '
{ 0x08, 0x41, 0x08, 0x20, 0x82, 0x08, 0x20, 0x41, 0x02 }, // (
{ 0x20, 0x41, 0x02, 0x08, 0x20, 0x82, 0x08, 0x41, 0x08 }, // )
{ 0x00, 0x00, 0x04, 0x11, 0xF1, 0x0A, 0x00, 0x00, 0x00 }, // *
{ 0x00, 0x00, 0x04, 0x11, 0xF1, 0x04, 0x00, 0x00, 0x00 }, // +
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x42, 0x00 }, // ,
{ 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00 }, // -
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x40, 0x00 }, // .
{ 0x04, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0x00, 0x00 }, // /
{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 0
{ 0x10, 0xC1, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // 1
{ 0x39, 0x14, 0x41, 0x08, 0x42, 0x10, 0x41, 0xF0, 0x00 }, // 2
{ 0x39, 0x14, 0x41, 0x18, 0x10, 0x51, 0x44, 0xE0, 0x00 }, // 3
{ 0x08, 0x61, 0x8A, 0x29, 0x24, 0x9F, 0x08, 0x20, 0x00 }, // 4
{ 0x7D, 0x04, 0x10, 0x79, 0x10, 0x41, 0x44, 0xE0, 0x00 }, // 5
{ 0x39, 0x14, 0x10, 0x79, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 6
{ 0x7D, 0x14, 0x41, 0x08, 0x21, 0x04, 0x10, 0x40, 0x00 }, // 7
{ 0x39, 0x14, 0x51, 0x39, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // 8
{ 0x39, 0x14, 0x51, 0x44, 0xF0, 0x41, 0x44, 0xE0, 0x00 }, // 9
{ 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x00, 0x00 }, // :
{ 0x00, 0x01, 0x04, 0x00, 0x00, 0x04, 0x10, 0x80, 0x00 }, // ;
{ 0x00, 0x00, 0x42, 0x31, 0x03, 0x02, 0x04, 0x00, 0x00 }, // <
{ 0x00, 0x00, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x00, 0x00 }, // =
{ 0x00, 0x04, 0x08, 0x18, 0x11, 0x88, 0x40, 0x00, 0x00 }, // >
{ 0x39, 0x14, 0x41, 0x08, 0x41, 0x00, 0x10, 0x40, 0x00 }, // ?
{ 0x18, 0x94, 0xD5, 0x55, 0x55, 0x57, 0x40, 0xE0, 0x00 }, // @
{ 0x10, 0x41, 0x0A, 0x28, 0xA7, 0xD1, 0x45, 0x10, 0x00 }, // A
{ 0x79, 0x14, 0x51, 0x79, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // B
{ 0x39, 0x14, 0x50, 0x41, 0x04, 0x11, 0x44, 0xE0, 0x00 }, // C
{ 0x79, 0x14, 0x51, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // D
{ 0x7D, 0x04, 0x10, 0x7D, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // E
{ 0x7D, 0x04, 0x10, 0x79, 0x04, 0x10, 0x41, 0x00, 0x00 }, // F
{ 0x39, 0x14, 0x50, 0x5D, 0x14, 0x51, 0x4C, 0xD0, 0x00 }, // G
{ 0x45, 0x14, 0x51, 0x7D, 0x14, 0x51, 0x45, 0x10, 0x00 }, // H
{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // I
{ 0x08, 0x20, 0x82, 0x08, 0x20, 0x92, 0x48, 0xC0, 0x00 }, // J
{ 0x45, 0x24, 0x94, 0x61, 0x45, 0x12, 0x49, 0x10, 0x00 }, // K
{ 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0xF0, 0x00 }, // L
{ 0x45, 0x16, 0xDB, 0x6D, 0x55, 0x55, 0x45, 0x10, 0x00 }, // M
{ 0x45, 0x16, 0x59, 0x55, 0x54, 0xD3, 0x45, 0x10, 0x00 }, // N
{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // O
{ 0x79, 0x14, 0x51, 0x45, 0xE4, 0x10, 0x41, 0x00, 0x00 }, // P
{ 0x39, 0x14, 0x51, 0x45, 0x14, 0x51, 0x54, 0xE0, 0x40 }, // Q
{ 0x79, 0x14, 0x51, 0x45, 0xE4, 0x91, 0x45, 0x10, 0x00 }, // R
{ 0x39, 0x14, 0x48, 0x10, 0x20, 0x51, 0x44, 0xE0, 0x00 }, // S
{ 0x7C, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // T
{ 0x45, 0x14, 0x51, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // U
{ 0x45, 0x14, 0x51, 0x28, 0xA2, 0x84, 0x10, 0x40, 0x00 }, // V
{ 0x55, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W
{ 0x45, 0x12, 0x8A, 0x10, 0x42, 0x8A, 0x45, 0x10, 0x00 }, // X
{ 0x45, 0x14, 0x4A, 0x28, 0x41, 0x04, 0x10, 0x40, 0x00 }, // Y
{ 0x7C, 0x10, 0x82, 0x10, 0x42, 0x08, 0x41, 0xF0, 0x00 }, // Z
{ 0x30, 0x82, 0x08, 0x20, 0x82, 0x08, 0x20, 0x82, 0x0C }, // [
{ 0x55, 0x55, 0x7F, 0x55, 0x55, 0x4A, 0x28, 0xA0, 0x00 }, // W(WON)
{ 0x30, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x0C }, // ]
{ 0x31, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ^
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0 }, // _
{ 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // `
{ 0x00, 0x00, 0x0C, 0x48, 0xE4, 0x92, 0x48, 0xD0, 0x00 }, // a
{ 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0xE0, 0x00 }, // b
{ 0x00, 0x00, 0x0E, 0x45, 0x04, 0x10, 0x44, 0xE0, 0x00 }, // c
{ 0x04, 0x10, 0x4F, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // d
{ 0x00, 0x00, 0x0E, 0x45, 0x17, 0xD0, 0x44, 0xE0, 0x00 }, // e
{ 0x10, 0x82, 0x1C, 0x20, 0x82, 0x08, 0x20, 0x80, 0x00 }, // f
{ 0x00, 0x00, 0x0F, 0x45, 0x14, 0x4F, 0x05, 0x13, 0x80 }, // g
{ 0x41, 0x04, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // h
{ 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // i
{ 0x10, 0x40, 0x04, 0x10, 0x41, 0x04, 0x10, 0x46, 0x00 }, // j
{ 0x41, 0x04, 0x11, 0x49, 0x46, 0x14, 0x49, 0x10, 0x00 }, // k
{ 0x00, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x40, 0x00 }, // l
{ 0x00, 0x00, 0x1A, 0x55, 0x55, 0x55, 0x55, 0x50, 0x00 }, // m
{ 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x45, 0x10, 0x00 }, // n
{ 0x00, 0x00, 0x0E, 0x45, 0x14, 0x51, 0x44, 0xE0, 0x00 }, // o
{ 0x00, 0x00, 0x1E, 0x45, 0x14, 0x51, 0x79, 0x04, 0x00 }, // p
{ 0x00, 0x00, 0x0F, 0x45, 0x14, 0x51, 0x3C, 0x10, 0x40 }, // q
{ 0x00, 0x00, 0x0B, 0x30, 0x82, 0x08, 0x20, 0x80, 0x00 }, // r
{ 0x00, 0x00, 0x0E, 0x45, 0x03, 0x81, 0x44, 0xE0, 0x00 }, // s
{ 0x00, 0x82, 0x1E, 0x20, 0x82, 0x08, 0x20, 0x60, 0x00 }, // t
{ 0x00, 0x00, 0x11, 0x45, 0x14, 0x51, 0x44, 0xF0, 0x00 }, // u
{ 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x40, 0x00 }, // v
{ 0x00, 0x00, 0x15, 0x55, 0x55, 0x4E, 0x28, 0xA0, 0x00 }, // w
{ 0x00, 0x00, 0x11, 0x44, 0xA1, 0x0A, 0x45, 0x10, 0x00 }, // x
{ 0x00, 0x00, 0x11, 0x45, 0x12, 0x8A, 0x10, 0x46, 0x00 }, // y
{ 0x00, 0x00, 0x1F, 0x04, 0x21, 0x08, 0x41, 0xF0, 0x00 }, // z
{ 0x08, 0x41, 0x04, 0x11, 0x81, 0x04, 0x10, 0x41, 0x02 }, // {
{ 0x10, 0x41, 0x04, 0x10, 0x41, 0x04, 0x10, 0x41, 0x04 }, // |
{ 0x40, 0x82, 0x08, 0x20, 0x62, 0x08, 0x20, 0x82, 0x10 }, // }
{ 0x00, 0x00, 0x00, 0x00, 0xD4, 0x80, 0x00, 0x00, 0x00 }, // ~
{ 0x01, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49, 0xE0, 0x00 }, // 
};
const Uint16 EtcFontTable[81][18] =
{
{ 0x00, 0x02, 0x00, 0x53, 0x82, 0x44, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x40, 0x38, 0x00, 0x00, 0x00 }, // ℃, A1C9
{ 0x00, 0x06, 0x00, 0x78, 0x07, 0xE0, 0x7F, 0x87, 0xFC, 0x7F, 0x87, 0xE0, 0x78, 0x06, 0x00, 0x00, 0x00, 0x00 }, // ▶, A2BA
{ 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x12, 0xA1, 0x2A, 0x24, 0xC2, 0x48, 0x3C, 0xA4, 0x34, 0x40, 0x00, 0x00 }, // ㎕, A7A1
{ 0x00, 0x00, 0x04, 0x00, 0xA0, 0x0A, 0x68, 0xA5, 0x4A, 0x54, 0xC5, 0x48, 0x54, 0xA5, 0x54, 0x00, 0x00, 0x00 }, // ㎖, A7A2
{ 0x00, 0x00, 0x44, 0x04, 0xA0, 0x4A, 0x1C, 0xA2, 0x4A, 0x24, 0xC2, 0x48, 0x25, 0xA1, 0xE4, 0x00, 0x00, 0x00 }, // ㎗, A7A3
{ 0x00, 0x00, 0x00, 0x02, 0x00, 0x50, 0x05, 0x00, 0x50, 0x06, 0x00, 0x40, 0x0D, 0x00, 0x20, 0x00, 0x00, 0x00 }, // ℓ , A7A4
{ 0x00, 0x02, 0x04, 0x20, 0xA2, 0x0A, 0x24, 0xA2, 0x8A, 0x30, 0xC3, 0x08, 0x29, 0x52, 0x62, 0x00, 0x00, 0x00 }, // ㎘, A7A5
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xC2, 0x52, 0x21, 0x02, 0x10, 0x25, 0x21, 0x8C, 0x00, 0x00, 0x00 }, // ㏄, A7A6
{ 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x6A, 0x95, 0x56, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // ㎣, A7A7
{ 0x00, 0x00, 0x02, 0x00, 0x10, 0x02, 0x36, 0x94, 0xD6, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // ㎤, A7A8
{ 0x00, 0x00, 0x04, 0x00, 0x20, 0x04, 0x76, 0x24, 0x94, 0x49, 0x04, 0x90, 0x49, 0x04, 0x90, 0x00, 0x00, 0x00 }, // ㎥, A7A9
{ 0x00, 0x04, 0x02, 0x40, 0x14, 0x02, 0x4E, 0x95, 0x56, 0x65, 0x45, 0x54, 0x4D, 0x44, 0x54, 0x00, 0x00, 0x00 }, // ㎦, A7AA
{ 0x00, 0x00, 0x80, 0x10, 0x01, 0x00, 0x3B, 0x41, 0x2A, 0x12, 0xA1, 0x2A, 0x12, 0xA1, 0x2A, 0x00, 0x00, 0x00 }, // ㎙, A7AB
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x44, 0xAA, 0x4A, 0xA4, 0xAA, 0x4A, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // ㎚, A7AC
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0xA1, 0x55, 0x29, 0x52, 0x95, 0x35, 0x54, 0x15, 0x40, 0x00, 0x00 }, // ㎛, A7AD
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xA5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00 }, // ㎜, A7AE
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x44, 0xAA, 0x42, 0xA4, 0x2A, 0x4A, 0xA3, 0x2A, 0x00, 0x00, 0x00 }, // ㎝, A7AF
{ 0x00, 0x04, 0x00, 0x40, 0x04, 0x00, 0x4B, 0x45, 0x2A, 0x62, 0xA6, 0x2A, 0x52, 0xA4, 0xAA, 0x00, 0x00, 0x00 }, // ㎞, A7B0
{ 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x6A, 0xA5, 0x57, 0x55, 0x45, 0x54, 0x55, 0x45, 0x54, 0x00, 0x00, 0x00 }, // ㎟, A7B1
{ 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x36, 0xA4, 0xD7, 0x45, 0x44, 0x54, 0x4D, 0x43, 0x54, 0x00, 0x00, 0x00 }, // ㎠, A7B2
{ 0x00, 0x00, 0x02, 0x00, 0x10, 0x01, 0x3B, 0x22, 0x4B, 0x24, 0x82, 0x48, 0x24, 0x82, 0x48, 0x00, 0x00, 0x00 }, // ㎡, A7B3
{ 0x00, 0x04, 0x02, 0x40, 0x14, 0x01, 0x4E, 0xA5, 0x57, 0x65, 0x46, 0x54, 0x55, 0x44, 0xD4, 0x00, 0x00, 0x00 }, // ㎢, A7B4
{ 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x38, 0xC2, 0x52, 0x24, 0xE2, 0x52, 0x25, 0x22, 0x4D, 0x00, 0x00, 0x00 }, // ㏊, A7B5
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0xE1, 0x52, 0x29, 0x22, 0x92, 0x34, 0xE4, 0x12, 0x40, 0xC0, 0x00 }, // ㎍, A7B6
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xE5, 0x52, 0x55, 0x25, 0x52, 0x54, 0xE5, 0x52, 0x00, 0xC0, 0x00 }, // ㎎, A7B7
{ 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x24, 0xE2, 0x92, 0x31, 0x23, 0x12, 0x28, 0xE2, 0x52, 0x00, 0xC0, 0x00 }, // ㎏, A7B8
{ 0x00, 0x02, 0x08, 0x20, 0x82, 0x08, 0x25, 0xC2, 0x88, 0x30, 0x83, 0x08, 0x28, 0xA2, 0x44, 0x00, 0x00, 0x00 }, // ㏏, A7B9
{ 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x33, 0x14, 0xC9, 0x43, 0x94, 0x49, 0x4C, 0x93, 0x35, 0x00, 0x00, 0x00 }, // ㎈, A7BA
{ 0x00, 0x04, 0x01, 0x40, 0x14, 0x01, 0x56, 0x96, 0x95, 0x68, 0xD6, 0x95, 0x59, 0x55, 0x6B, 0x00, 0x00, 0x00 }, // ㎉, A7BB
{ 0x00, 0x00, 0x5C, 0x05, 0x20, 0x52, 0x1D, 0x22, 0x5C, 0x25, 0x22, 0x52, 0x25, 0x21, 0xDC, 0x00, 0x00, 0x00 }, // ㏈, A7BC
{ 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x68, 0xE5, 0x59, 0x55, 0x45, 0x52, 0x55, 0x95, 0x56, 0x00, 0x00, 0x00 }, // ㎧, A7BD
{ 0x00, 0x00, 0x12, 0x01, 0x10, 0x21, 0x6A, 0xE5, 0x73, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // ㎨, A7BE
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x39, 0x22, 0x0C, 0x20, 0x00, 0x00 }, // ㎰, A7BF
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0xC2, 0x52, 0x24, 0x82, 0x44, 0x25, 0x22, 0x4C, 0x00, 0x00, 0x00 }, // ㎱, A7C0
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x61, 0x29, 0x24, 0x42, 0x42, 0x3A, 0x94, 0x06, 0x40, 0x00, 0x00 }, // ㎲, A7C1
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0xC5, 0x52, 0x54, 0x85, 0x44, 0x55, 0x25, 0x4C, 0x00, 0x00, 0x00 }, // ㎳, A7C2
{ 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x39, 0x42, 0x54, 0x25, 0x42, 0x48, 0x38, 0x82, 0x08, 0x20, 0x00, 0x00 }, // ㎴, A7C3
{ 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x71, 0x44, 0x94, 0x49, 0x44, 0x88, 0x48, 0x84, 0x88, 0x00, 0x00, 0x00 }, // ㎵, A7C4
{ 0x00, 0x00, 0x11, 0x01, 0x10, 0x11, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x44, 0x3A, 0x44, 0x04, 0x40, 0x00, 0x00 }, // ㎶, A7C5
{ 0x00, 0x00, 0x22, 0x02, 0x20, 0x22, 0x69, 0x45, 0x54, 0x55, 0x45, 0x48, 0x54, 0x85, 0x48, 0x00, 0x00, 0x00 }, // ㎷, A7C6
{ 0x00, 0x04, 0x22, 0x42, 0x24, 0x22, 0x49, 0x45, 0x14, 0x61, 0x46, 0x08, 0x50, 0x84, 0x88, 0x00, 0x00, 0x00 }, // ㎸, A7C7
{ 0x00, 0x04, 0x51, 0x45, 0x16, 0xD1, 0x6C, 0xA5, 0x4A, 0x54, 0xA5, 0x44, 0x44, 0x44, 0x44, 0x00, 0x00, 0x00 }, // ㎹, A7C8
{ 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0x44, 0xBE, 0x72, 0x24, 0x22, 0x40, 0x00, 0x00 }, // ㎀, A7C9
{ 0x00, 0x00, 0x08, 0x00, 0x80, 0x08, 0x71, 0x44, 0x94, 0x49, 0xC4, 0xA2, 0x4A, 0x24, 0xA2, 0x00, 0x00, 0x00 }, // ㎁, A7CA
{ 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x12, 0xA1, 0x2A, 0x24, 0xA2, 0x5F, 0x3B, 0x14, 0x11, 0x40, 0x00, 0x00 }, // ㎂, A7CB
{ 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x68, 0xA5, 0x4A, 0x54, 0xA5, 0x5F, 0x55, 0x15, 0x51, 0x00, 0x00, 0x00 }, // ㎃, A7CC
{ 0x00, 0x02, 0x04, 0x20, 0x42, 0x04, 0x24, 0xA2, 0x8A, 0x30, 0xA3, 0x1F, 0x29, 0x12, 0x51, 0x00, 0x00, 0x00 }, // ㎄, A7CD
{ 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x71, 0x44, 0x14, 0x40, 0x00, 0x00 }, // ㎺, A7CE
{ 0x00, 0x00, 0x2A, 0x02, 0xA0, 0x2A, 0x72, 0xA4, 0xAA, 0x4A, 0xA4, 0x94, 0x49, 0x44, 0x94, 0x00, 0x00, 0x00 }, // ㎻, A7CF
{ 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x15, 0x51, 0x55, 0x29, 0x52, 0x8A, 0x34, 0xA4, 0x0A, 0x40, 0x00, 0x00 }, // ㎼, A7D0
{ 0x00, 0x00, 0x15, 0x01, 0x50, 0x15, 0x69, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x54, 0xA5, 0x4A, 0x00, 0x00, 0x00 }, // ㎽, A7D1
{ 0x00, 0x04, 0x2A, 0x42, 0xA4, 0x2A, 0x4A, 0xA5, 0x2A, 0x62, 0xA6, 0x14, 0x51, 0x44, 0x94, 0x00, 0x00, 0x00 }, // ㎾, A7D2
{ 0x00, 0x04, 0x55, 0x45, 0x56, 0xD5, 0x6D, 0x55, 0x55, 0x55, 0x55, 0x4A, 0x44, 0xA4, 0x4A, 0x00, 0x00, 0x00 }, // ㎿, A7D3
{ 0x00, 0x02, 0x40, 0x24, 0x02, 0x40, 0x25, 0xE3, 0xC2, 0x24, 0x42, 0x48, 0x25, 0x02, 0x5E, 0x00, 0x00, 0x00 }, // ㎐, A7D4
{ 0x00, 0x04, 0x50, 0x45, 0x04, 0x50, 0x55, 0x75, 0x71, 0x65, 0x26, 0x52, 0x55, 0x45, 0x57, 0x00, 0x00, 0x00 }, // ㎑, A7D5
{ 0x00, 0x04, 0x48, 0x44, 0x86, 0xC8, 0x6C, 0xF5, 0x79, 0x54, 0xA5, 0x4A, 0x54, 0xC4, 0x4F, 0x00, 0x00, 0x00 }, // ㎒, A7D6
{ 0x00, 0x03, 0x28, 0x4A, 0x84, 0xA8, 0x42, 0xF5, 0xB9, 0x4A, 0xA4, 0xAA, 0x4A, 0xC3, 0xAF, 0x00, 0x00, 0x00 }, // ㎓, A7D7
{ 0x00, 0x07, 0xE8, 0x12, 0x81, 0x28, 0x12, 0xF1, 0x39, 0x12, 0xA1, 0x2A, 0x12, 0xC1, 0x2F, 0x00, 0x00, 0x00 }, // ㎔, A7D8
{ 0x00, 0x00, 0x00, 0x07, 0x00, 0x88, 0x10, 0x41, 0x04, 0x10, 0x40, 0x88, 0x15, 0x41, 0xDC, 0x00, 0x00, 0x00 }, // Ω, A7D9
{ 0x00, 0x04, 0x1C, 0x42, 0x24, 0x22, 0x4A, 0x25, 0x22, 0x61, 0x46, 0x14, 0x51, 0x44, 0xB6, 0x00, 0x00, 0x00 }, // ㏀, A7DA
{ 0x00, 0x04, 0x4E, 0x45, 0x16, 0xD1, 0x6D, 0x15, 0x51, 0x54, 0xA5, 0x4A, 0x44, 0xA4, 0x5B, 0x00, 0x00, 0x00 }, // ㏁, A7DB
{ 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x72, 0x04, 0x20, 0x40, 0x00, 0x00 }, // ㎊, A7DC
{ 0x00, 0x00, 0x3E, 0x02, 0x00, 0x20, 0x72, 0x04, 0xBC, 0x4A, 0x04, 0xA0, 0x4A, 0x04, 0xA0, 0x00, 0x00, 0x00 }, // ㎋, A7DD
{ 0x00, 0x00, 0x0F, 0x00, 0x80, 0x08, 0x12, 0x81, 0x2E, 0x24, 0x82, 0x48, 0x3A, 0x84, 0x08, 0x40, 0x00, 0x00 }, // ㎌, A7DE
{ 0x00, 0x00, 0x02, 0x00, 0x20, 0x02, 0x6B, 0x25, 0x4A, 0x54, 0xA5, 0x4A, 0x54, 0xA5, 0x72, 0x00, 0x00, 0x00 }, // ㏖, A7DF
{ 0x00, 0x00, 0x04, 0x00, 0x40, 0x04, 0x31, 0xC4, 0xA4, 0x42, 0x44, 0x24, 0x4A, 0x43, 0x1C, 0x00, 0x00, 0x00 }, // ㏅, A7E0
{ 0x00, 0x00, 0x01, 0x00, 0x10, 0x01, 0x56, 0x36, 0x95, 0x47, 0x54, 0x95, 0x49, 0x54, 0x6B, 0x00, 0x00, 0x00 }, // ㎭, A7E1
{ 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x54, 0x4E, 0xC0, 0x07, 0x07, 0x87, 0x86, 0x00, 0xC0, 0x02, 0x00, 0xC0, 0x00 }, // ㎮, A7E2
{ 0x58, 0x46, 0x4C, 0x4D, 0x45, 0x57, 0x4E, 0xC0, 0x32, 0x1C, 0x16, 0x1A, 0x03, 0x30, 0x08, 0x03, 0x00, 0x00 }, // ㎯, A7E3
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0xA2, 0x2C, 0x18, 0x80, 0x48, 0x22, 0x81, 0xC8, 0x00, 0x00, 0x00 }, // ㏛, A7E4
{ 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xC2, 0x52, 0x38, 0xE2, 0x12, 0x21, 0x22, 0x0D, 0x00, 0x00, 0x00 }, // ㎩, A7E5
{ 0x00, 0x04, 0x60, 0x45, 0x04, 0x50, 0x55, 0xC5, 0x52, 0x66, 0x66, 0x4A, 0x54, 0xA5, 0x47, 0x00, 0x00, 0x00 }, // ㎪, A7E6
{ 0x00, 0x04, 0x58, 0x45, 0x46, 0xD4, 0x6D, 0x65, 0x55, 0x55, 0xB5, 0x55, 0x45, 0x54, 0x53, 0x00, 0x00, 0x00 }, // ㎫, A7E7
{ 0x00, 0x03, 0x30, 0x4A, 0x84, 0xA8, 0x42, 0xE5, 0xA9, 0x4B, 0x34, 0xA5, 0x4A, 0x53, 0xA3, 0x00, 0x00, 0x00 }, // ㎬, A7E8
{ 0x00, 0x05, 0x50, 0x55, 0x05, 0x50, 0x55, 0xC5, 0x52, 0x55, 0x22, 0x92, 0x29, 0x22, 0x9C, 0x00, 0x00, 0x00 }, // ㏝, A7E9
{ 0x00, 0x02, 0x00, 0x20, 0x02, 0x00, 0x26, 0x82, 0x54, 0x25, 0x42, 0x54, 0x25, 0x42, 0x54, 0x00, 0x00, 0x00 }, // ㏐, A7EA
{ 0x00, 0x01, 0x00, 0x10, 0x01, 0x00, 0x14, 0x41, 0x28, 0x11, 0x01, 0x10, 0x12, 0x81, 0x44, 0x00, 0x00, 0x00 }, // ㏓, A7EB
{ 0x00, 0x03, 0x80, 0x24, 0x02, 0x40, 0x24, 0xE3, 0x92, 0x25, 0x22, 0x52, 0x24, 0xE3, 0x82, 0x00, 0x20, 0x00 }, // ㏃, A7EC
{ 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x42, 0x25, 0xA2, 0x49, 0x44, 0x94, 0x48, 0x83, 0x08, 0x03, 0x00, 0x00 }, // ㏉, A7ED
{ 0x00, 0x03, 0x00, 0x48, 0x04, 0x80, 0x22, 0x21, 0x22, 0x09, 0x44, 0x94, 0x48, 0x83, 0x08, 0x00, 0x00, 0x00 }, // ㏜, A7EE
{ 0x24, 0x05, 0x60, 0x56, 0x04, 0xA0, 0x4A, 0xB5, 0xAD, 0x2B, 0x51, 0x35, 0x12, 0xB1, 0x2D, 0x00, 0x20, 0x00 } // ㏆, A7EF
};
extern const Uint16 EngFontTable[96][9];
extern const Uint16 EtcFontTable[81][18];
#endif

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// TI File $Revision: /main/5 $
// Checkin $Date: May 14, 2008 16:30:31 $
//###########################################################################
//
// FILE: DSP2833x_Mcbsp.h
//
// TITLE: DSP2833x Device McBSP Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_MCBSP_H
#define DSP2833x_MCBSP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// McBSP Individual Register Bit Definitions
//
//
// McBSP DRR2 register bit definitions
//
struct DRR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DRR2_REG {
Uint16 all;
struct DRR2_BITS bit;
};
//
// McBSP DRR1 register bit definitions
//
struct DRR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DRR1_REG {
Uint16 all;
struct DRR1_BITS bit;
};
//
// McBSP DXR2 register bit definitions
//
struct DXR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DXR2_REG {
Uint16 all;
struct DXR2_BITS bit;
};
//
// McBSP DXR1 register bit definitions
//
struct DXR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DXR1_REG {
Uint16 all;
struct DXR1_BITS bit;
};
//
// SPCR2 control register bit definitions
//
struct SPCR2_BITS { // bit description
Uint16 XRST:1; // 0 transmit reset
Uint16 XRDY:1; // 1 transmit ready
Uint16 XEMPTY:1; // 2 Transmit empty
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
Uint16 XINTM:2; // 5:4 Transmit interrupt types
Uint16 GRST:1; // 6 CLKG reset
Uint16 FRST:1; // 7 Frame sync reset
Uint16 SOFT:1; // 8 SOFT bit
Uint16 FREE:1; // 9 FREE bit
Uint16 rsvd:6; // 15:10 reserved
};
union SPCR2_REG {
Uint16 all;
struct SPCR2_BITS bit;
};
//
// SPCR1 control register bit definitions
//
struct SPCR1_BITS { // bit description
Uint16 RRST:1; // 0 Receive reset
Uint16 RRDY:1; // 1 Receive ready
Uint16 RFULL:1; // 2 Receive full
Uint16 RSYNCERR:1; // 7 Receive syn error
Uint16 RINTM:2; // 5:4 Receive interrupt types
Uint16 rsvd1:1; // 6 reserved
Uint16 DXENA:1; // 7 DX hi-z enable
Uint16 rsvd2:3; // 10:8 reserved
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
Uint16 RJUST:2; // 13:14 Right justified
Uint16 DLB:1; // 15 Digital loop back
};
union SPCR1_REG {
Uint16 all;
struct SPCR1_BITS bit;
};
//
// RCR2 control register bit definitions
//
struct RCR2_BITS { // bit description
Uint16 RDATDLY:2; // 1:0 Receive data delay
Uint16 RFIG:1; // 2 Receive frame sync ignore
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
Uint16 RWDLEN2:3; // 7:5 Receive word length
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
Uint16 RPHASE:1; // 15 Receive Phase
};
union RCR2_REG {
Uint16 all;
struct RCR2_BITS bit;
};
//
// RCR1 control register bit definitions
//
struct RCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 RWDLEN1:3; // 7:5 Receive word length
Uint16 RFRLEN1:7; // 14:8 Receive frame length
Uint16 rsvd2:1; // 15 reserved
};
union RCR1_REG {
Uint16 all;
struct RCR1_BITS bit;
};
//
// XCR2 control register bit definitions
//
struct XCR2_BITS { // bit description
Uint16 XDATDLY:2; // 1:0 Transmit data delay
Uint16 XFIG:1; // 2 Transmit frame sync ignore
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
Uint16 XWDLEN2:3; // 7:5 Transmit word length
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
Uint16 XPHASE:1; // 15 Transmit Phase
};
union XCR2_REG {
Uint16 all;
struct XCR2_BITS bit;
};
//
// XCR1 control register bit definitions
//
struct XCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 XWDLEN1:3; // 7:5 Transmit word length
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
Uint16 rsvd2:1; // 15 reserved
};
union XCR1_REG {
Uint16 all;
struct XCR1_BITS bit;
};
//
// SRGR2 Sample rate generator control register bit definitions
//
struct SRGR2_BITS { // bit description
Uint16 FPER:12; // 11:0 Frame period
Uint16 FSGM:1; // 12 Frame sync generator mode
Uint16 CLKSM:1; // 13 Sample rate generator mode
Uint16 rsvd:1; // 14 reserved
Uint16 GSYNC:1; // 15 CLKG sync
};
union SRGR2_REG {
Uint16 all;
struct SRGR2_BITS bit;
};
//
// SRGR1 control register bit definitions
//
struct SRGR1_BITS { // bit description
Uint16 CLKGDV:8; // 7:0 CLKG divider
Uint16 FWID:8; // 15:8 Frame width
};
union SRGR1_REG {
Uint16 all;
struct SRGR1_BITS bit;
};
//
// MCR2 Multichannel control register bit definitions
//
struct MCR2_BITS { // bit description
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
Uint16 XCBLK:3; // 2:4 Transmit current block
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
Uint16 rsvd:6; // 15:10 reserved
};
union MCR2_REG {
Uint16 all;
struct MCR2_BITS bit;
};
//
// MCR1 Multichannel control register bit definitions
//
struct MCR1_BITS { // bit description
Uint16 RMCM:1; // 0 Receive multichannel mode
Uint16 rsvd:1; // 1 reserved
Uint16 RCBLK:3; // 4:2 Receive current block
Uint16 RPABLK:2; // 6:5 Receive partition A Block
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
Uint16 rsvd1:6; // 15:10 reserved
};
union MCR1_REG {
Uint16 all;
struct MCR1_BITS bit;
};
//
// RCERA control register bit definitions
//
struct RCERA_BITS { // bit description
Uint16 RCEA0:1; // 0 Receive Channel enable bit
Uint16 RCEA1:1; // 1 Receive Channel enable bit
Uint16 RCEA2:1; // 2 Receive Channel enable bit
Uint16 RCEA3:1; // 3 Receive Channel enable bit
Uint16 RCEA4:1; // 4 Receive Channel enable bit
Uint16 RCEA5:1; // 5 Receive Channel enable bit
Uint16 RCEA6:1; // 6 Receive Channel enable bit
Uint16 RCEA7:1; // 7 Receive Channel enable bit
Uint16 RCEA8:1; // 8 Receive Channel enable bit
Uint16 RCEA9:1; // 9 Receive Channel enable bit
Uint16 RCEA10:1; // 10 Receive Channel enable bit
Uint16 RCEA11:1; // 11 Receive Channel enable bit
Uint16 RCEA12:1; // 12 Receive Channel enable bit
Uint16 RCEA13:1; // 13 Receive Channel enable bit
Uint16 RCEA14:1; // 14 Receive Channel enable bit
Uint16 RCEA15:1; // 15 Receive Channel enable bit
};
union RCERA_REG {
Uint16 all;
struct RCERA_BITS bit;
};
//
// RCERB control register bit definitions
//
struct RCERB_BITS { // bit description
Uint16 RCEB0:1; // 0 Receive Channel enable bit
Uint16 RCEB1:1; // 1 Receive Channel enable bit
Uint16 RCEB2:1; // 2 Receive Channel enable bit
Uint16 RCEB3:1; // 3 Receive Channel enable bit
Uint16 RCEB4:1; // 4 Receive Channel enable bit
Uint16 RCEB5:1; // 5 Receive Channel enable bit
Uint16 RCEB6:1; // 6 Receive Channel enable bit
Uint16 RCEB7:1; // 7 Receive Channel enable bit
Uint16 RCEB8:1; // 8 Receive Channel enable bit
Uint16 RCEB9:1; // 9 Receive Channel enable bit
Uint16 RCEB10:1; // 10 Receive Channel enable bit
Uint16 RCEB11:1; // 11 Receive Channel enable bit
Uint16 RCEB12:1; // 12 Receive Channel enable bit
Uint16 RCEB13:1; // 13 Receive Channel enable bit
Uint16 RCEB14:1; // 14 Receive Channel enable bit
Uint16 RCEB15:1; // 15 Receive Channel enable bit
};
union RCERB_REG {
Uint16 all;
struct RCERB_BITS bit;
};
//
// XCERA control register bit definitions
//
struct XCERA_BITS { // bit description
Uint16 XCERA0:1; // 0 Receive Channel enable bit
Uint16 XCERA1:1; // 1 Receive Channel enable bit
Uint16 XCERA2:1; // 2 Receive Channel enable bit
Uint16 XCERA3:1; // 3 Receive Channel enable bit
Uint16 XCERA4:1; // 4 Receive Channel enable bit
Uint16 XCERA5:1; // 5 Receive Channel enable bit
Uint16 XCERA6:1; // 6 Receive Channel enable bit
Uint16 XCERA7:1; // 7 Receive Channel enable bit
Uint16 XCERA8:1; // 8 Receive Channel enable bit
Uint16 XCERA9:1; // 9 Receive Channel enable bit
Uint16 XCERA10:1; // 10 Receive Channel enable bit
Uint16 XCERA11:1; // 11 Receive Channel enable bit
Uint16 XCERA12:1; // 12 Receive Channel enable bit
Uint16 XCERA13:1; // 13 Receive Channel enable bit
Uint16 XCERA14:1; // 14 Receive Channel enable bit
Uint16 XCERA15:1; // 15 Receive Channel enable bit
};
union XCERA_REG {
Uint16 all;
struct XCERA_BITS bit;
};
//
// XCERB control register bit definitions
//
struct XCERB_BITS { // bit description
Uint16 XCERB0:1; // 0 Receive Channel enable bit
Uint16 XCERB1:1; // 1 Receive Channel enable bit
Uint16 XCERB2:1; // 2 Receive Channel enable bit
Uint16 XCERB3:1; // 3 Receive Channel enable bit
Uint16 XCERB4:1; // 4 Receive Channel enable bit
Uint16 XCERB5:1; // 5 Receive Channel enable bit
Uint16 XCERB6:1; // 6 Receive Channel enable bit
Uint16 XCERB7:1; // 7 Receive Channel enable bit
Uint16 XCERB8:1; // 8 Receive Channel enable bit
Uint16 XCERB9:1; // 9 Receive Channel enable bit
Uint16 XCERB10:1; // 10 Receive Channel enable bit
Uint16 XCERB11:1; // 11 Receive Channel enable bit
Uint16 XCERB12:1; // 12 Receive Channel enable bit
Uint16 XCERB13:1; // 13 Receive Channel enable bit
Uint16 XCERB14:1; // 14 Receive Channel enable bit
Uint16 XCERB15:1; // 15 Receive Channel enable bit
};
union XCERB_REG {
Uint16 all;
struct XCERB_BITS bit;
};
//
// PCR control register bit definitions
//
struct PCR_BITS { // bit description
Uint16 CLKRP:1; // 0 Receive Clock polarity
Uint16 CLKXP:1; // 1 Transmit clock polarity
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
Uint16 CLKRM:1; // 8 Receiver Clock Mode
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in
// this 28x-McBSP
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in
// this 28x-McBSP
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
Uint16 rsvd:1 ; // 15 reserved
};
union PCR_REG {
Uint16 all;
struct PCR_BITS bit;
};
//
// RCERC control register bit definitions
//
struct RCERC_BITS { // bit description
Uint16 RCEC0:1; // 0 Receive Channel enable bit
Uint16 RCEC1:1; // 1 Receive Channel enable bit
Uint16 RCEC2:1; // 2 Receive Channel enable bit
Uint16 RCEC3:1; // 3 Receive Channel enable bit
Uint16 RCEC4:1; // 4 Receive Channel enable bit
Uint16 RCEC5:1; // 5 Receive Channel enable bit
Uint16 RCEC6:1; // 6 Receive Channel enable bit
Uint16 RCEC7:1; // 7 Receive Channel enable bit
Uint16 RCEC8:1; // 8 Receive Channel enable bit
Uint16 RCEC9:1; // 9 Receive Channel enable bit
Uint16 RCEC10:1; // 10 Receive Channel enable bit
Uint16 RCEC11:1; // 11 Receive Channel enable bit
Uint16 RCEC12:1; // 12 Receive Channel enable bit
Uint16 RCEC13:1; // 13 Receive Channel enable bit
Uint16 RCEC14:1; // 14 Receive Channel enable bit
Uint16 RCEC15:1; // 15 Receive Channel enable bit
};
union RCERC_REG {
Uint16 all;
struct RCERC_BITS bit;
};
//
// RCERD control register bit definitions
//
struct RCERD_BITS { // bit description
Uint16 RCED0:1; // 0 Receive Channel enable bit
Uint16 RCED1:1; // 1 Receive Channel enable bit
Uint16 RCED2:1; // 2 Receive Channel enable bit
Uint16 RCED3:1; // 3 Receive Channel enable bit
Uint16 RCED4:1; // 4 Receive Channel enable bit
Uint16 RCED5:1; // 5 Receive Channel enable bit
Uint16 RCED6:1; // 6 Receive Channel enable bit
Uint16 RCED7:1; // 7 Receive Channel enable bit
Uint16 RCED8:1; // 8 Receive Channel enable bit
Uint16 RCED9:1; // 9 Receive Channel enable bit
Uint16 RCED10:1; // 10 Receive Channel enable bit
Uint16 RCED11:1; // 11 Receive Channel enable bit
Uint16 RCED12:1; // 12 Receive Channel enable bit
Uint16 RCED13:1; // 13 Receive Channel enable bit
Uint16 RCED14:1; // 14 Receive Channel enable bit
Uint16 RCED15:1; // 15 Receive Channel enable bit
};
union RCERD_REG {
Uint16 all;
struct RCERD_BITS bit;
};
//
// XCERC control register bit definitions
//
struct XCERC_BITS { // bit description
Uint16 XCERC0:1; // 0 Receive Channel enable bit
Uint16 XCERC1:1; // 1 Receive Channel enable bit
Uint16 XCERC2:1; // 2 Receive Channel enable bit
Uint16 XCERC3:1; // 3 Receive Channel enable bit
Uint16 XCERC4:1; // 4 Receive Channel enable bit
Uint16 XCERC5:1; // 5 Receive Channel enable bit
Uint16 XCERC6:1; // 6 Receive Channel enable bit
Uint16 XCERC7:1; // 7 Receive Channel enable bit
Uint16 XCERC8:1; // 8 Receive Channel enable bit
Uint16 XCERC9:1; // 9 Receive Channel enable bit
Uint16 XCERC10:1; // 10 Receive Channel enable bit
Uint16 XCERC11:1; // 11 Receive Channel enable bit
Uint16 XCERC12:1; // 12 Receive Channel enable bit
Uint16 XCERC13:1; // 13 Receive Channel enable bit
Uint16 XCERC14:1; // 14 Receive Channel enable bit
Uint16 XCERC15:1; // 15 Receive Channel enable bit
};
union XCERC_REG {
Uint16 all;
struct XCERC_BITS bit;
};
//
// XCERD control register bit definitions
//
struct XCERD_BITS { // bit description
Uint16 XCERD0:1; // 0 Receive Channel enable bit
Uint16 XCERD1:1; // 1 Receive Channel enable bit
Uint16 XCERD2:1; // 2 Receive Channel enable bit
Uint16 XCERD3:1; // 3 Receive Channel enable bit
Uint16 XCERD4:1; // 4 Receive Channel enable bit
Uint16 XCERD5:1; // 5 Receive Channel enable bit
Uint16 XCERD6:1; // 6 Receive Channel enable bit
Uint16 XCERD7:1; // 7 Receive Channel enable bit
Uint16 XCERD8:1; // 8 Receive Channel enable bit
Uint16 XCERD9:1; // 9 Receive Channel enable bit
Uint16 XCERD10:1; // 10 Receive Channel enable bit
Uint16 XCERD11:1; // 11 Receive Channel enable bit
Uint16 XCERD12:1; // 12 Receive Channel enable bit
Uint16 XCERD13:1; // 13 Receive Channel enable bit
Uint16 XCERD14:1; // 14 Receive Channel enable bit
Uint16 XCERD15:1; // 15 Receive Channel enable bit
};
union XCERD_REG {
Uint16 all;
struct XCERD_BITS bit;
};
//
// RCERE control register bit definitions
//
struct RCERE_BITS { // bit description
Uint16 RCEE0:1; // 0 Receive Channel enable bit
Uint16 RCEE1:1; // 1 Receive Channel enable bit
Uint16 RCEE2:1; // 2 Receive Channel enable bit
Uint16 RCEE3:1; // 3 Receive Channel enable bit
Uint16 RCEE4:1; // 4 Receive Channel enable bit
Uint16 RCEE5:1; // 5 Receive Channel enable bit
Uint16 RCEE6:1; // 6 Receive Channel enable bit
Uint16 RCEE7:1; // 7 Receive Channel enable bit
Uint16 RCEE8:1; // 8 Receive Channel enable bit
Uint16 RCEE9:1; // 9 Receive Channel enable bit
Uint16 RCEE10:1; // 10 Receive Channel enable bit
Uint16 RCEE11:1; // 11 Receive Channel enable bit
Uint16 RCEE12:1; // 12 Receive Channel enable bit
Uint16 RCEE13:1; // 13 Receive Channel enable bit
Uint16 RCEE14:1; // 14 Receive Channel enable bit
Uint16 RCEE15:1; // 15 Receive Channel enable bit
};
union RCERE_REG {
Uint16 all;
struct RCERE_BITS bit;
};
//
// RCERF control register bit definitions
//
struct RCERF_BITS { // bit description
Uint16 RCEF0:1; // 0 Receive Channel enable bit
Uint16 RCEF1:1; // 1 Receive Channel enable bit
Uint16 RCEF2:1; // 2 Receive Channel enable bit
Uint16 RCEF3:1; // 3 Receive Channel enable bit
Uint16 RCEF4:1; // 4 Receive Channel enable bit
Uint16 RCEF5:1; // 5 Receive Channel enable bit
Uint16 RCEF6:1; // 6 Receive Channel enable bit
Uint16 RCEF7:1; // 7 Receive Channel enable bit
Uint16 RCEF8:1; // 8 Receive Channel enable bit
Uint16 RCEF9:1; // 9 Receive Channel enable bit
Uint16 RCEF10:1; // 10 Receive Channel enable bit
Uint16 RCEF11:1; // 11 Receive Channel enable bit
Uint16 RCEF12:1; // 12 Receive Channel enable bit
Uint16 RCEF13:1; // 13 Receive Channel enable bit
Uint16 RCEF14:1; // 14 Receive Channel enable bit
Uint16 RCEF15:1; // 15 Receive Channel enable bit
};
union RCERF_REG {
Uint16 all;
struct RCERF_BITS bit;
};
// XCERE control register bit definitions:
struct XCERE_BITS { // bit description
Uint16 XCERE0:1; // 0 Receive Channel enable bit
Uint16 XCERE1:1; // 1 Receive Channel enable bit
Uint16 XCERE2:1; // 2 Receive Channel enable bit
Uint16 XCERE3:1; // 3 Receive Channel enable bit
Uint16 XCERE4:1; // 4 Receive Channel enable bit
Uint16 XCERE5:1; // 5 Receive Channel enable bit
Uint16 XCERE6:1; // 6 Receive Channel enable bit
Uint16 XCERE7:1; // 7 Receive Channel enable bit
Uint16 XCERE8:1; // 8 Receive Channel enable bit
Uint16 XCERE9:1; // 9 Receive Channel enable bit
Uint16 XCERE10:1; // 10 Receive Channel enable bit
Uint16 XCERE11:1; // 11 Receive Channel enable bit
Uint16 XCERE12:1; // 12 Receive Channel enable bit
Uint16 XCERE13:1; // 13 Receive Channel enable bit
Uint16 XCERE14:1; // 14 Receive Channel enable bit
Uint16 XCERE15:1; // 15 Receive Channel enable bit
};
union XCERE_REG {
Uint16 all;
struct XCERE_BITS bit;
};
//
// XCERF control register bit definitions
//
struct XCERF_BITS { // bit description
Uint16 XCERF0:1; // 0 Receive Channel enable bit
Uint16 XCERF1:1; // 1 Receive Channel enable bit
Uint16 XCERF2:1; // 2 Receive Channel enable bit
Uint16 XCERF3:1; // 3 Receive Channel enable bit
Uint16 XCERF4:1; // 4 Receive Channel enable bit
Uint16 XCERF5:1; // 5 Receive Channel enable bit
Uint16 XCERF6:1; // 6 Receive Channel enable bit
Uint16 XCERF7:1; // 7 Receive Channel enable bit
Uint16 XCERF8:1; // 8 Receive Channel enable bit
Uint16 XCERF9:1; // 9 Receive Channel enable bit
Uint16 XCERF10:1; // 10 Receive Channel enable bit
Uint16 XCERF11:1; // 11 Receive Channel enable bit
Uint16 XCERF12:1; // 12 Receive Channel enable bit
Uint16 XCERF13:1; // 13 Receive Channel enable bit
Uint16 XCERF14:1; // 14 Receive Channel enable bit
Uint16 XCERF15:1; // 15 Receive Channel enable bit
};
union XCERF_REG {
Uint16 all;
struct XCERF_BITS bit;
};
//
// RCERG control register bit definitions
//
struct RCERG_BITS { // bit description
Uint16 RCEG0:1; // 0 Receive Channel enable bit
Uint16 RCEG1:1; // 1 Receive Channel enable bit
Uint16 RCEG2:1; // 2 Receive Channel enable bit
Uint16 RCEG3:1; // 3 Receive Channel enable bit
Uint16 RCEG4:1; // 4 Receive Channel enable bit
Uint16 RCEG5:1; // 5 Receive Channel enable bit
Uint16 RCEG6:1; // 6 Receive Channel enable bit
Uint16 RCEG7:1; // 7 Receive Channel enable bit
Uint16 RCEG8:1; // 8 Receive Channel enable bit
Uint16 RCEG9:1; // 9 Receive Channel enable bit
Uint16 RCEG10:1; // 10 Receive Channel enable bit
Uint16 RCEG11:1; // 11 Receive Channel enable bit
Uint16 RCEG12:1; // 12 Receive Channel enable bit
Uint16 RCEG13:1; // 13 Receive Channel enable bit
Uint16 RCEG14:1; // 14 Receive Channel enable bit
Uint16 RCEG15:1; // 15 Receive Channel enable bit
};
union RCERG_REG {
Uint16 all;
struct RCERG_BITS bit;
};
// RCERH control register bit definitions:
struct RCERH_BITS { // bit description
Uint16 RCEH0:1; // 0 Receive Channel enable bit
Uint16 RCEH1:1; // 1 Receive Channel enable bit
Uint16 RCEH2:1; // 2 Receive Channel enable bit
Uint16 RCEH3:1; // 3 Receive Channel enable bit
Uint16 RCEH4:1; // 4 Receive Channel enable bit
Uint16 RCEH5:1; // 5 Receive Channel enable bit
Uint16 RCEH6:1; // 6 Receive Channel enable bit
Uint16 RCEH7:1; // 7 Receive Channel enable bit
Uint16 RCEH8:1; // 8 Receive Channel enable bit
Uint16 RCEH9:1; // 9 Receive Channel enable bit
Uint16 RCEH10:1; // 10 Receive Channel enable bit
Uint16 RCEH11:1; // 11 Receive Channel enable bit
Uint16 RCEH12:1; // 12 Receive Channel enable bit
Uint16 RCEH13:1; // 13 Receive Channel enable bit
Uint16 RCEH14:1; // 14 Receive Channel enable bit
Uint16 RCEH15:1; // 15 Receive Channel enable bit
};
union RCERH_REG {
Uint16 all;
struct RCERH_BITS bit;
};
//
// XCERG control register bit definitions
//
struct XCERG_BITS { // bit description
Uint16 XCERG0:1; // 0 Receive Channel enable bit
Uint16 XCERG1:1; // 1 Receive Channel enable bit
Uint16 XCERG2:1; // 2 Receive Channel enable bit
Uint16 XCERG3:1; // 3 Receive Channel enable bit
Uint16 XCERG4:1; // 4 Receive Channel enable bit
Uint16 XCERG5:1; // 5 Receive Channel enable bit
Uint16 XCERG6:1; // 6 Receive Channel enable bit
Uint16 XCERG7:1; // 7 Receive Channel enable bit
Uint16 XCERG8:1; // 8 Receive Channel enable bit
Uint16 XCERG9:1; // 9 Receive Channel enable bit
Uint16 XCERG10:1; // 10 Receive Channel enable bit
Uint16 XCERG11:1; // 11 Receive Channel enable bit
Uint16 XCERG12:1; // 12 Receive Channel enable bit
Uint16 XCERG13:1; // 13 Receive Channel enable bit
Uint16 XCERG14:1; // 14 Receive Channel enable bit
Uint16 XCERG15:1; // 15 Receive Channel enable bit
};
union XCERG_REG {
Uint16 all;
struct XCERG_BITS bit;
};
//
// XCERH control register bit definitions
//
struct XCERH_BITS { // bit description
Uint16 XCEH0:1; // 0 Receive Channel enable bit
Uint16 XCEH1:1; // 1 Receive Channel enable bit
Uint16 XCEH2:1; // 2 Receive Channel enable bit
Uint16 XCEH3:1; // 3 Receive Channel enable bit
Uint16 XCEH4:1; // 4 Receive Channel enable bit
Uint16 XCEH5:1; // 5 Receive Channel enable bit
Uint16 XCEH6:1; // 6 Receive Channel enable bit
Uint16 XCEH7:1; // 7 Receive Channel enable bit
Uint16 XCEH8:1; // 8 Receive Channel enable bit
Uint16 XCEH9:1; // 9 Receive Channel enable bit
Uint16 XCEH10:1; // 10 Receive Channel enable bit
Uint16 XCEH11:1; // 11 Receive Channel enable bit
Uint16 XCEH12:1; // 12 Receive Channel enable bit
Uint16 XCEH13:1; // 13 Receive Channel enable bit
Uint16 XCEH14:1; // 14 Receive Channel enable bit
Uint16 XCEH15:1; // 15 Receive Channel enable bit
};
union XCERH_REG {
Uint16 all;
struct XCERH_BITS bit;
};
//
// McBSP Interrupt enable register for RINT/XINT
//
struct MFFINT_BITS { // bits description
Uint16 XINT:1; // 0 XINT interrupt enable
Uint16 rsvd1:1; // 1 reserved
Uint16 RINT:1; // 2 RINT interrupt enable
Uint16 rsvd2:13; // 15:3 reserved
};
union MFFINT_REG {
Uint16 all;
struct MFFINT_BITS bit;
};
//
// McBSP Register File
//
struct MCBSP_REGS {
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
Uint16 rsvd1[4]; // reserved
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for
// RINT/XINT
Uint16 rsvd2; // reserved
};
//
// McBSP External References & Function Declarations
//
extern volatile struct MCBSP_REGS McbspaRegs;
extern volatile struct MCBSP_REGS McbspbRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_MCBSP_H definition
//
// No more
//

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#include "main.h"
void CInitAlarmOperValue(void);
void CKeyMainPowerProcess(void);
void CKeyArrowUpProcess(void);
void CKeyArrowDownProcess(void);
void CKeyEnterProcess(void);
void CKeyMenuProcess(void);
void CKeyEngineStartStopProcess(void);
void CKeyEmergencyProcess(void);
void CInitAdcStructure(void);
Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType);
static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh);
Uint32 CGetKey(void);
void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead);
static void MoveFocusLine(Uint16 maxLines, Uint16 direction);
static void CChangePasswordDigit(Uint16 direction);
static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff);
CAdcCalcValue Adc_EngineHeater_I;
CAdcCalcValue Adc_GlowPlug_I;
CAdcCalcValue Adc_Solenoid_I;
CAdcCalcValue Adc_FuelPump_I;
CAdcCalcValue Adc_CoolantPump_I;
CAdcCalcValue Adc_Fan1_I;
CAdcCalcValue Adc_Fan2_I;
CAdcOperValue AdcOperValue;
CAlarmOperValue AlarmOperValue[IDX_FAULT_MAX];
CFaultBitValue FaultBitValue;
CKeyOperValue KeyOperValue;
static const CKeyHandler KeyTable[IDX_KEY_MAX] =
{
{ IDX_KEY_MAIN_POWER, CKeyMainPowerProcess },
{ IDX_KEY_ARR_UP, CKeyArrowUpProcess },
{ IDX_KEY_ARR_DOWN, CKeyArrowDownProcess },
{ IDX_KEY_ENTER, CKeyEnterProcess },
{ IDX_KEY_MENU, CKeyMenuProcess },
{ IDX_KEY_ENG_START_STOP, CKeyEngineStartStopProcess },
{ IDX_KEY_EMERGENCY, CKeyEmergencyProcess }
};
interrupt void CAdcInterrupt(void)
{
Uint16 uiTemp[IDX_ADC_MAX];
Uint16 i;
const volatile Uint16 *pAdcAddress = &AdcRegs.ADCRESULT0;
for (i = 0U; i < IDX_ADC_MAX; i++)
{
uiTemp[i] = (*(pAdcAddress++) >> 4);
}
Adc_EngineHeater_I.iAdcValue = (int16) uiTemp[IDX_ADC_ENGINE_HEATER_I];
Adc_GlowPlug_I.iAdcValue = (int16) uiTemp[IDX_ADC_GLOW_PLUG_I];
Adc_Solenoid_I.iAdcValue = (int16) uiTemp[IDX_ADC_SOLENOID_I];
Adc_FuelPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_FUEL_PUMP_I];
Adc_CoolantPump_I.iAdcValue = (int16) uiTemp[IDX_ADC_COOLANT_PUMP_I];
Adc_Fan1_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN1_I];
Adc_Fan2_I.iAdcValue = (int16) uiTemp[IDX_ADC_FAN2_I];
CCalcAdcSum(&Adc_EngineHeater_I);
CCalcAdcSum(&Adc_GlowPlug_I);
CCalcAdcSum(&Adc_Solenoid_I);
CCalcAdcSum(&Adc_FuelPump_I);
CCalcAdcSum(&Adc_CoolantPump_I);
CCalcAdcSum(&Adc_Fan1_I);
CCalcAdcSum(&Adc_Fan2_I);
if (AdcOperValue.uiOffsetAdjustStart == 1U) // ADC Calibration
{
Adc_EngineHeater_I.fTempAdcOffset += Adc_EngineHeater_I.fSampledValue;
Adc_GlowPlug_I.fTempAdcOffset += Adc_GlowPlug_I.fSampledValue;
Adc_Solenoid_I.fTempAdcOffset += Adc_Solenoid_I.fSampledValue;
Adc_FuelPump_I.fTempAdcOffset += Adc_FuelPump_I.fSampledValue;
Adc_CoolantPump_I.fTempAdcOffset += Adc_CoolantPump_I.fSampledValue;
Adc_Fan1_I.fTempAdcOffset += Adc_Fan1_I.fSampledValue;
Adc_Fan2_I.fTempAdcOffset += Adc_Fan2_I.fSampledValue;
AdcOperValue.uiAdcOffsetIndex--;
if (AdcOperValue.uiAdcOffsetIndex == 0U)
{
Adc_EngineHeater_I.fOffset -= (Adc_EngineHeater_I.fTempAdcOffset / 10000.0f);
Adc_GlowPlug_I.fOffset -= (Adc_GlowPlug_I.fTempAdcOffset / 10000.0f);
Adc_Solenoid_I.fOffset -= (Adc_Solenoid_I.fTempAdcOffset / 10000.0f);
Adc_FuelPump_I.fOffset -= (Adc_FuelPump_I.fTempAdcOffset / 10000.0f);
Adc_CoolantPump_I.fOffset -= (Adc_CoolantPump_I.fTempAdcOffset / 10000.0f);
Adc_Fan1_I.fOffset -= (Adc_Fan1_I.fTempAdcOffset / 10000.0f);
Adc_Fan2_I.fOffset -= (Adc_Fan2_I.fTempAdcOffset / 10000.0f);
AdcOperValue.uiOffsetAdjustStart = 0U;
}
}
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1U; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1U; // Clear INT SEQ1 bit
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; // Acknowledge interrupt to PIE
}
void CDisplayAlarmPopup(void)
{
Uint64 ullFaultValue = ((Uint64)FaultBitValue.ulTotal & 0x3FFFFUL) | (((Uint64)Rx210.GcuFault.uiTotal & 0xFFFFU) << 19UL) | (((Uint64)Rx310.EcuFault.uiTotal & 0x3FU) << 35UL);
Uint32 ulWarningValue = ((Uint32)Rx210.GcuWarning.uiTotal & 0x7U) | (((Uint32)Rx310.EcuWarning.uiTotal & 0xFU) << 4U);
Uint16 i;
if (OledOperValue.uiAlarmPopCheck == 0U)
{
if (ulWarningValue > 0U)
{
for (i = 0U; i < 16U; i++)
{
if ((ulWarningValue >> i) == 1U)
{
OledOperValue.uiAlarmPopCheck = 1U;
OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum;
OledOperValue.uiPageNum = ((i / 9U) + OLED_PAGE_WARNING1);
break;
}
}
}
if (ullFaultValue > 0U)
{
for (i = 0U; i < 64U; i++)
{
if ((ullFaultValue >> i) == 1U)
{
OledOperValue.uiAlarmPopCheck = 1U;
OledOperValue.uiPrevAlarmPage = OledOperValue.uiPageNum;
OledOperValue.uiPageNum = (((i % 64U) / 8U) + OLED_PAGE_FAULT1);
break;
}
}
}
}
}
void CAlarmProcedure(void)
{
int16 iDiffRpm = 0U;
if (CGetApuOperIndex() == APU_OPER_IDX_EMERGENCY)
{
// 타임 아웃 발생 시 연결수립 비트는 클리어 한다.
GeneralOperValue.Conection.CarComputer = (FaultBitValue.bit.CarCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.CarComputer;
GeneralOperValue.Conection.Gcu = (FaultBitValue.bit.GcuCommTimeout == 1U) ? 0U : GeneralOperValue.Conection.Gcu;
GeneralOperValue.Conection.Ecu = (FaultBitValue.bit.EcuCommTimeOut == 1U) ? 0U : GeneralOperValue.Conection.Ecu;
if (GeneralOperValue.uiAlarmReset == 1U)
{
GeneralOperValue.uiAlarmReset = 0U;
CInitAlarmOperValue();
}
}
else
{
if (GeneralOperValue.uiApuState > APU_OPER_IDX_EMERGENCY)
{
// Comm Timeout Checks
FaultBitValue.bit.CarCommTimeout = CAlarmCheck(IDX_FAULT_CAR_COMM, (float32)CommCheck.CarComputer, AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.GcuCommTimeout = CAlarmCheck(IDX_FAULT_GCU_COMM, (float32)CommCheck.Gcu, AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.EcuCommTimeOut = CAlarmCheck(IDX_FAULT_ECU_COMM, (float32)CommCheck.Ecu, AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime, ALARM_OVER_CHECK);
if ((GeneralOperValue.Conection.Gcu == 1U) && (GeneralOperValue.Conection.Ecu == 1U))
{
// RPM오류는 보조발전기제어기와 보조엔진제어기의 통신이 연결되었을 때 검출한다.
iDiffRpm = (int16)CGetGeneratorRpm() - (int16)CGetEngineActualRpm();
iDiffRpm = ABS(iDiffRpm);
FaultBitValue.bit.RpmError = CAlarmCheck(IDX_FAULT_RPM_ERR, (float32)iDiffRpm, AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime, ALARM_OVER_CHECK);
}
FaultBitValue.bit.EngineHeatOverCurrent = CAlarmCheck(IDX_FAULT_ENGINE_HEAT_OC, Adc_EngineHeater_I.fLpfValue, AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.GlowPlugOverCurrent = CAlarmCheck(IDX_FAULT_GLOW_PLUG_OC, Adc_GlowPlug_I.fLpfValue, AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.SolenoidOverCurrent = CAlarmCheck(IDX_FAULT_SOLENOID_OC, Adc_Solenoid_I.fLpfValue, AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.FuelPumpOverCurrent = CAlarmCheck(IDX_FAULT_FUEL_PUMP_OC, Adc_FuelPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.CoolantPumpOverCurrent = CAlarmCheck(IDX_FAULT_COOLANT_PUMP_OC, Adc_CoolantPump_I.fLpfValue, AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.Fan1OverCurrent = CAlarmCheck(IDX_FAULT_FAN1_OC, Adc_Fan1_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime, ALARM_OVER_CHECK);
FaultBitValue.bit.Fan2OverCurrent = CAlarmCheck(IDX_FAULT_FAN2_OC, Adc_Fan2_I.fLpfValue, AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime, ALARM_OVER_CHECK);
// Fuse 신호는 각 장치에 대응하는 CS가 ON 상태에서 작동하므로 CS가 HI일 때, Fuse 신호가 HI면 단선
if (CGetApuOperIndex() > APU_OPER_IDX_STANDBY)
{
FaultBitValue.bit.EngineHeatOpen = CheckOpenFault(GPIO_ENGINE_HEATER_CS_READ(), GPIO_ENGINE_HEATER_FUSE());
FaultBitValue.bit.GlowPlugOpen = CheckOpenFault(GPIO_GLOW_PLUG_CS_READ(), GPIO_GLOW_PLUG_FUSE());
FaultBitValue.bit.SolenoidOpen = CheckOpenFault(GPIO_SOLENOID_CS_READ(), GPIO_SOLENOID_FUSE());
FaultBitValue.bit.FuelPumpOpen = CheckOpenFault(GPIO_FUEL_PUMP_CS_READ(), GPIO_FUEL_PUMP_FUSE());
FaultBitValue.bit.CoolantPumpOpen = CheckOpenFault(GPIO_COOLANT_PUMP_CS_READ(), GPIO_COOLANT_PUMP_FUSE());
FaultBitValue.bit.Fan1Open = CheckOpenFault(GPIO_FAN1_CS_READ(), GPIO_FAN1_FUSE());
FaultBitValue.bit.Fan2Open = CheckOpenFault(GPIO_FAN2_CS_READ(), GPIO_FAN2_FUSE());
}
}
}
}
Uint16 CAlarmCheck(ALARM_TYPE Idx, float32 fValue, Uint16 uiCheckDetectTime, Uint16 uiCheckType)
{
Uint16 uiCheckStatus = 0;
if (AlarmOperValue[Idx].uiCheck == 0U)
{
if (uiCheckType == ALARM_OVER_CHECK)
{
// Over Check !
if (fValue >= AlarmOperValue[Idx].fCheckLimit)
{
uiCheckStatus = 1U;
}
}
else
{
// Under Check !
if (fValue <= AlarmOperValue[Idx].fCheckLimit)
{
uiCheckStatus = 1U;
}
}
if (uiCheckStatus == 1U)
{
if (AlarmOperValue[Idx].uiCheckCount < uiCheckDetectTime)
{
AlarmOperValue[Idx].uiCheckCount++;
}
else
{
AlarmOperValue[Idx].uiCheck = 1U;
AlarmOperValue[Idx].uiCheckCount = 0U;
AlarmOperValue[Idx].fFaultValue = fValue;
}
}
else
{
AlarmOperValue[Idx].uiCheckCount = 0U;
}
}
return AlarmOperValue[Idx].uiCheck;
}
static inline Uint16 CheckOpenFault(Uint16 isCsHigh, Uint16 isFuseHigh)
{
// 두 신호가 모두 1(High)일 때만 1(Fault) 반환
return ((isCsHigh == 1U) && (isFuseHigh == 1U)) ? 1U : 0U;
}
void CInitAlarmOperValue(void)
{
int16 i;
for (i = 0; i < IDX_FAULT_MAX; i++)
{
(void) memset(&AlarmOperValue[i], 0, sizeof(CAlarmOperValue));
}
(void) memset(&FaultBitValue, 0, sizeof(CFaultBitValue));
(void) memset(&CommCheck, 0, sizeof(CCommCheck));
// 체계/GCU/ECU 통신 및 신호 단선은 다른 함수에서 처리
/*
* Alarm Check Standard Value
* Alarm Count per 1mS
*/
AlarmOperValue[IDX_FAULT_CAR_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds
AlarmOperValue[IDX_FAULT_CAR_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출
AlarmOperValue[IDX_FAULT_GCU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds
AlarmOperValue[IDX_FAULT_GCU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출
AlarmOperValue[IDX_FAULT_ECU_COMM].fCheckLimit = (float32)(COMM_TIME_OUT_COUNT); // 3 Seconds
AlarmOperValue[IDX_FAULT_ECU_COMM].uiCheckTime = 1U; // 시간을 감지 하므로 즉시 검출
AlarmOperValue[IDX_FAULT_RPM_ERR].fCheckLimit = 300.0f; // Value
AlarmOperValue[IDX_FAULT_RPM_ERR].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_ENGINE_HEAT_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_GLOW_PLUG_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_SOLENOID_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_SOLENOID_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_FUEL_PUMP_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_COOLANT_PUMP_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_FAN1_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_FAN1_OC].uiCheckTime = 10U; // Value
AlarmOperValue[IDX_FAULT_FAN2_OC].fCheckLimit = 10.0f; // Value
AlarmOperValue[IDX_FAULT_FAN2_OC].uiCheckTime = 10U; // Value
}
void CInitAdc(void)
{
InitAdc(); // ADC Initialize in DSP2833x_Adc.c
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; // No prescaler
AdcRegs.ADCTRL1.bit.CPS = 0x1; // scaler 12.5Mhz
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0; // sequentail mode
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // EOS
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascade Sequence Mode
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Engine_Heater_I
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Glow_Plug_I
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Solenoid_I
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Fuel_Pump_I
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Cooling_Pump_I
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Fan1_I
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Fan2_I
AdcRegs.ADCMAXCONV.all = IDX_ADC_MAX; // Setup 16 channel conversion for cascade sequence mode
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1; // external Reference 2.048[V], 'b01 - 2.048, b10 - 1.500[V], 'b11 - 1.024[v]
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // Enable SEQ1 interrupt (every EOS)
AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // Sample and hold duration(width) = (ACQ_PS + 1)
CInitAdcStructure();
CInitAlarmOperValue();
}
void CInitAdcStructure(void)
{
(void) memset(&AdcOperValue, 0, sizeof(CAdcOperValue));
(void) memset(&Adc_EngineHeater_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_GlowPlug_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_Solenoid_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_FuelPump_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_CoolantPump_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_Fan1_I, 0, sizeof(CAdcCalcValue));
(void) memset(&Adc_Fan2_I, 0, sizeof(CAdcCalcValue));
AdcOperValue.uiAdcOffsetIndex = 10000U;
Adc_EngineHeater_I.fGain = 0.005637f;
Adc_GlowPlug_I.fGain = 0.005637f;
Adc_Solenoid_I.fGain = 0.005637f;
Adc_FuelPump_I.fGain = 0.005637f;
Adc_CoolantPump_I.fGain = 0.005637f;
Adc_Fan1_I.fGain = 0.005637f;
Adc_Fan2_I.fGain = 0.005637f;
Adc_EngineHeater_I.fOffset = -2.333f;
Adc_GlowPlug_I.fOffset = -2.333f;
Adc_Solenoid_I.fOffset = -2.333f;
Adc_FuelPump_I.fOffset = -2.333f;
Adc_CoolantPump_I.fOffset = -2.333f;
Adc_Fan1_I.fOffset = -2.333f;
Adc_Fan2_I.fOffset = -2.333f;
}
static inline void CCalcAdcSum(CAdcCalcValue *AdcBuff)
{
#if 1
AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset;
AdcBuff->fSampledSum += AdcBuff->fSampledValue;
AdcBuff->uiSamplingCount++;
if (AdcBuff->uiSamplingCount >= 100)
{
AdcBuff->uiSamplingCount = 0;
AdcBuff->fSampledSum /= 100;
AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledSum) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue);
AdcBuff->fSampledSum = 0.0f;
}
#else
AdcBuff->fSampledValue = ((float32) AdcBuff->iAdcValue * AdcBuff->fGain) + AdcBuff->fOffset;
AdcBuff->fLpfValue = (ADC_LPF_GAIN * AdcBuff->fSampledValue) + ((1.0f - ADC_LPF_GAIN) * AdcBuff->fLpfValue);
#endif
}
Uint32 CGetKey(void)
{
Uint16 i, ucDiv, ucMod;
Uint32 ulGpioData = 0UL, ulKeyRead = 0UL;
Uint16 ucKeyGpioList[7] = { 67, 39, 31, 30, 29, 66, 64};
for (i = 0; i < IDX_KEY_MAX; i++)
{
ucDiv = ucKeyGpioList[i] / 32;
ucMod = ucKeyGpioList[i] % 32;
if (ucDiv == 0U) // GPIO-A
{
ulGpioData = GpioDataRegs.GPADAT.all;
}
else if (ucDiv == 1U)
{
ulGpioData = GpioDataRegs.GPBDAT.all;
}
else
{
ulGpioData = GpioDataRegs.GPCDAT.all;
}
if (((ulGpioData >> ucMod) & 0x01UL) == 0U) // Push Check
{
ulKeyRead |= (0x01UL << i);
}
}
return ulKeyRead;
}
void CKeyCheckProcedure(void)
{
static Uint32 ulLongKeyCnt = 0UL; // 롱키 카운트용 변수
static Uint16 uiLongKeyProcessed = 0U; // 롱키 처리 완료 플래그 (중복 실행 방지)
static Uint32 ulPrevKey = 0UL;
Uint32 ulChangeKey;
Uint32 ulReadKey = CGetKey();
ulChangeKey = (ulPrevKey ^ ulReadKey) & ~KEY_POWER_MASK; // 현재 키와 이전 키를 비교하되, 롱키(Bit 0)는 변화 감지에서 제외함 (& ~KEY_POWER_MASK)
if (ulChangeKey > 0UL)
{
if (KeyOperValue.uiKeyWait == 0U) // 채터링 무시 시작
{
KeyOperValue.uiKeyWait = 1U;
KeyOperValue.uiKeyWaitCount = 20; // 20ms
}
else
{
// 전원키를 제외한 나머지 키들은 POST 단계가 넘어가야지 동작한다.
if ((KeyOperValue.uiKeyWaitCount == 0U) && (CGetApuOperIndex() > APU_OPER_IDX_POST))
{
ulPrevKey = (ulPrevKey & KEY_POWER_MASK) | (ulReadKey & ~KEY_POWER_MASK); // ulPrevKey의 나머지 비트는 유지하고 변경된 비트만 갱신
CKeyCheck(ulChangeKey, ulReadKey); // 일반 키 동작
}
}
}
else
{
// 변화가 없으면 채터링 대기 초기화 (일반 키용)
// 단, 눌려있는 상태 유지를 위해 ulPrevKey 갱신은 필요 없음
if ((KeyOperValue.uiKeyWait) != 0U && (KeyOperValue.uiKeyWaitCount == 0U))
{
KeyOperValue.uiKeyWait = 0U;
}
}
// Bit 0이 눌려 있는지 확인 (1 = 눌림)
if ((ulReadKey & KEY_POWER_MASK) == KEY_POWER_MASK)
{
// 이미 처리가 끝난 상태가 아니라면 카운트 증가
if (uiLongKeyProcessed == 0U)
{
ulLongKeyCnt++;
// 1초(1000ms) 도달 시 동작 수행
if (ulLongKeyCnt >= LONG_KEY_TIME)
{
CKeyCheck(KEY_POWER_MASK, ulReadKey); // 롱키 동작 수행 (CKeyCheck에 롱키 비트만 전달)
uiLongKeyProcessed = 1U; // 떼기 전까지 다시 동작하지 않도록 플래그 설정
ulLongKeyCnt = LONG_KEY_TIME; // 카운트 오버플로우 방지
}
}
}
else
{
// 키를 뗐을 때 변수들 초기화
ulLongKeyCnt = 0UL;
uiLongKeyProcessed = 0U;
// ulPrevKey의 Bit 0 상태도 0으로 동기화 (다음 비교를 위해)
ulPrevKey &= ~KEY_POWER_MASK;
}
}
void CKeyWaitCount(void)
{
if (KeyOperValue.uiKeyWait == 1U)
{
if (KeyOperValue.uiKeyWaitCount > 0U)
{
KeyOperValue.uiKeyWaitCount--;
}
else
{
KeyOperValue.uiKeyWait = 0U;
}
}
}
void CKeyCheck(Uint32 ulChangeKey, Uint32 ulKeyRead)
{
Uint16 i;
for (i = 0U; i < IDX_KEY_MAX; i++)
{
if ((ulChangeKey & (0x1UL << i)) > 0U)
{
if ((ulKeyRead & (0x1UL << i)) > 0U)
{
KeyTable[i].pAction();
}
}
}
}
void CKeyArrowUpProcess(void)
{
if (OledOperValue.uiPageNum == OLED_PAGE_APU2)
{
OledOperValue.uiPageNum = OLED_PAGE_APU1;
}
else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1)
{
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1;
}
else
{
MoveFocusLine(4U, DIR_UP);
}
}
else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1)
{
// Go back to Menu 1
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_4;
OledOperValue.uiPageNum = OLED_PAGE_MENU1;
}
else
{
MoveFocusLine(3U, DIR_UP);
}
}
else if ((OledOperValue.uiPageNum > OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum <= OLED_PAGE_SENSOR4))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U;
}
else if ((OledOperValue.uiPageNum > OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_WARNING2))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U;
}
else if ((OledOperValue.uiPageNum > OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum - 1U;
}
else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD)
{
CChangePasswordDigit(DIR_UP);
}
else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM)
{
OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle
}
else
{
if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1)
{
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1;
}
else
{
MoveFocusLine(3U, DIR_UP);
}
}
}
}
void CKeyArrowDownProcess(void)
{
if (OledOperValue.uiPageNum == OLED_PAGE_APU1)
{
OledOperValue.uiPageNum = OLED_PAGE_APU2;
}
else if (OledOperValue.uiPageNum == OLED_PAGE_MENU1)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_4)
{
// Bottom of Menu 1 -> Go to Menu 2
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1;
OledOperValue.uiPageNum = OLED_PAGE_MENU2;
}
else
{
MoveFocusLine(4U, DIR_DOWN);
}
}
else if (OledOperValue.uiPageNum == OLED_PAGE_MENU2)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3)
{
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3;
}
else
{
MoveFocusLine(3U, DIR_DOWN);
}
}
else if ((OledOperValue.uiPageNum >= OLED_PAGE_SENSOR1) && (OledOperValue.uiPageNum < OLED_PAGE_SENSOR4))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U;
}
else if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum < OLED_PAGE_WARNING2))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U;
}
else if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum < OLED_PAGE_FAULT6))
{
OledOperValue.uiPageNum = OledOperValue.uiPageNum + 1U;
}
else if (OledOperValue.uiPageNum == OLED_PAGE_PASSWORD)
{
CChangePasswordDigit(DIR_DOWN);
}
else if (OledOperValue.uiPageNum == OLED_PAGE_RESET_ALARM)
{
OledOperValue.uiResetAnswer = OledOperValue.uiResetAnswer ^ 1U; // toggle
}
else
{
if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE)
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3)
{
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_3;
}
else
{
MoveFocusLine(3U, DIR_DOWN);
}
}
}
}
static void CChangePasswordDigit(Uint16 direction)
{
// Ensure the focus digit is within valid range to avoid out-of-bounds access
if (OledOperValue.uiFocusDigit <= OLED_PASS_DIGIT_4)
{
Uint16 *pDigit = &GeneralOperValue.uiPassword[OledOperValue.uiFocusDigit];
if (direction == DIR_UP)
{
*pDigit = (*pDigit + 1U) % 10U;
}
else // DIR_DOWN
{
if (*pDigit == 0U)
{
*pDigit = 9U;
}
else
{
*pDigit = (*pDigit - 1U) % 10U;
}
}
}
}
static void MoveFocusLine(Uint16 maxLines, Uint16 direction)
{
if (direction == DIR_UP)
{
OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + maxLines - 1U) % maxLines;
}
else // DIR_DOWN
{
OledOperValue.uiFocusLine = (OledOperValue.uiFocusLine + 1U) % maxLines;
}
}
void CKeyEnterProcess(void)
{
switch (OledOperValue.uiPageNum)
{
case OLED_PAGE_MENU1:
{
switch (OledOperValue.uiFocusLine)
{
case OLED_MENU_APU:
{
OledOperValue.uiPageNum = OLED_PAGE_APU1;
break;
}
case OLED_MENU_TEMP:
{
OledOperValue.uiPageNum = OLED_PAGE_TEMP;
break;
}
case OLED_MENU_SENSOR:
{
OledOperValue.uiPageNum = OLED_PAGE_SENSOR1;
break;
}
default:
{
if (OledOperValue.uiFocusLine == OLED_MENU_WARNING)
{
OledOperValue.uiPageNum = OLED_PAGE_WARNING1;
}
break;
}
}
break;
}
case OLED_PAGE_MENU2:
{
switch (OledOperValue.uiFocusLine)
{
case OLED_LINE_FOCUS_1: // Fault
{
OledOperValue.uiPageNum = OLED_PAGE_FAULT1;
break;
}
case OLED_LINE_FOCUS_2: // Reset
{
OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine;
OledOperValue.uiPageNum = OLED_PAGE_RESET_ALARM;
break;
}
case OLED_LINE_FOCUS_3: // Maintenence
{
OledOperValue.uiPrevFocusLine = OledOperValue.uiFocusLine;
OledOperValue.uiPageNum = OLED_PAGE_PASSWORD;
OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1;
break;
}
default:
break;
}
break;
}
case OLED_PAGE_PASSWORD:
{
if (OledOperValue.uiFocusDigit < OLED_PASS_DIGIT_4)
{
OledOperValue.uiFocusDigit = (OledOperValue.uiFocusDigit + 1U) % 4U;
}
else
{
// Check password
const Uint16 uiPassword[4] = DEBUG_MENU_PASSWORD;
if (memcmp(GeneralOperValue.uiPassword, uiPassword, sizeof(uiPassword)) == 0U)
{
GeneralOperValue.uiMaintenence = 1U;
OledOperValue.uiPageNum = OLED_PAGE_MAINTENENCE;
OledOperValue.uiFocusLine = OLED_LINE_FOCUS_1;
}
else
{
OledOperValue.uiFocusDigit = OLED_PASS_DIGIT_1;
}
}
break;
}
case OLED_PAGE_RESET_ALARM:
{
// Selected "YES"
if (OledOperValue.uiResetAnswer == 1U)
{
if (CApuSystemAlarmCheck() > 0)
{
GeneralOperValue.uiAlarmReset = 1U;
OledOperValue.uiAlarmPopCheck = 0U;
OledOperValue.uiAlreadyAlarm = 0U;
}
}
OledOperValue.uiPageNum = OLED_PAGE_MENU2;
break;
}
case OLED_PAGE_MAINTENENCE:
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_1)
{
GeneralOperValue.Maintenence.ManualCranking = GeneralOperValue.Maintenence.ManualCranking ^ 1U; // Toggle
}
else if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_2)
{
GeneralOperValue.Maintenence.LampTest = GeneralOperValue.Maintenence.LampTest ^ 1U; // Toggle
}
else
{
if (OledOperValue.uiFocusLine == OLED_LINE_FOCUS_3)
{
GeneralOperValue.Maintenence.KeyTest = GeneralOperValue.Maintenence.KeyTest ^ 1U; // Toggle
OledOperValue.uiPageNum = OLED_PAGE_KEY_TEST;
}
}
break;
}
default:
{
// Handle Fault/Warning page return logic
if ((OledOperValue.uiPageNum >= OLED_PAGE_WARNING1) && (OledOperValue.uiPageNum <= OLED_PAGE_FAULT6))
{
if (OledOperValue.uiAlarmPopCheck == 1U)
{
OledOperValue.uiAlreadyAlarm = 1U;
OledOperValue.uiPageNum = OledOperValue.uiPrevAlarmPage;
}
}
break;
}
}
}
void CKeyMenuProcess(void)
{
// Return to main menus from sub-pages
if ((OledOperValue.uiPageNum == OLED_PAGE_MENU1) || (OledOperValue.uiPageNum == OLED_PAGE_MENU2))
{
OledOperValue.uiPageNum = OLED_PAGE_APU1;
OledOperValue.uiFocusLine = 0U;
}
else
{
if ((OledOperValue.uiPageNum >= OLED_PAGE_FAULT1) && (OledOperValue.uiPageNum <= OLED_PAGE_MAINTENENCE))
{
// Return to Menu 2 from Faults or Debug
if (OledOperValue.uiPageNum == OLED_PAGE_MAINTENENCE)
{
GeneralOperValue.uiMaintenence = 0U;
OledOperValue.uiFocusLine = OledOperValue.uiPrevFocusLine;
}
OledOperValue.uiPageNum = OLED_PAGE_MENU2;
}
else
{
// Return to Menu 1 from others (APU, Temp, Sensor, Warning)
OledOperValue.uiPageNum = OLED_PAGE_MENU1;
}
}
}
void CKeyMainPowerProcess(void)
{
if (CGetApuOperIndex() <= APU_OPER_IDX_STANDBY)
{
// APU가 정지 상태에서만 전원 스위치 입력 가능
OledOperValue.uiPageNum = OLED_PAGE_SHUTDOWN;
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_SHUTDOWN, TIME_1SEC) == TIME_OVER)
{
GPIO_POWER_HOLD(0);
}
}
}
void CKeyEngineStartStopProcess(void)
{
KeyOperValue.KeyList.bit.EngineStartStop = KeyOperValue.KeyList.bit.EngineStartStop ^ 1U; // Toggle
}
void CKeyEmergencyProcess(void)
{
// 비상정지 스위치를 클리어 하기 위해서는 APU 시스템에 알람이 없어야 한다.
KeyOperValue.KeyList.bit.Emergency = KeyOperValue.KeyList.bit.Emergency ^ 1U; // Toggle
}

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:51:50 $
//###########################################################################
//
// FILE: DSP2833x_Adc.h
//
// TITLE: DSP2833x Device ADC Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_ADC_H
#define DSP2833x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
//
// ADC Individual Register Bit Definitions:
//
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
Uint16 SEQ_OVRD:1; // 5 Sequencer override
Uint16 CONT_RUN:1; // 6 Continuous run
Uint16 CPS:1; // 7 ADC core clock pre-scalar
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
Uint16 RESET:1; // 14 ADC reset
Uint16 rsvd2:1; // 15 reserved
};
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};
struct ADCTRL2_BITS { // bits description
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
Uint16 rsvd1:1; // 1 reserved
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
Uint16 rsvd2:1; // 4 reserved
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
Uint16 rsvd3:1; // 9 reserved
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
Uint16 rsvd4:1; // 12 reserved
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
};
union ADCTRL2_REG {
Uint16 all;
struct ADCTRL2_BITS bit;
};
struct ADCASEQSR_BITS { // bits description
Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
Uint16 rsvd1:1; // 7 reserved
Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
Uint16 rsvd2:4; // 15:12 reserved
};
union ADCASEQSR_REG {
Uint16 all;
struct ADCASEQSR_BITS bit;
};
struct ADCMAXCONV_BITS { // bits description
Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
Uint16 rsvd1:9; // 15:7 reserved
};
union ADCMAXCONV_REG {
Uint16 all;
struct ADCMAXCONV_BITS bit;
};
struct ADCCHSELSEQ1_BITS { // bits description
Uint16 CONV00:4; // 3:0 Conversion selection 00
Uint16 CONV01:4; // 7:4 Conversion selection 01
Uint16 CONV02:4; // 11:8 Conversion selection 02
Uint16 CONV03:4; // 15:12 Conversion selection 03
};
union ADCCHSELSEQ1_REG{
Uint16 all;
struct ADCCHSELSEQ1_BITS bit;
};
struct ADCCHSELSEQ2_BITS { // bits description
Uint16 CONV04:4; // 3:0 Conversion selection 04
Uint16 CONV05:4; // 7:4 Conversion selection 05
Uint16 CONV06:4; // 11:8 Conversion selection 06
Uint16 CONV07:4; // 15:12 Conversion selection 07
};
union ADCCHSELSEQ2_REG{
Uint16 all;
struct ADCCHSELSEQ2_BITS bit;
};
struct ADCCHSELSEQ3_BITS { // bits description
Uint16 CONV08:4; // 3:0 Conversion selection 08
Uint16 CONV09:4; // 7:4 Conversion selection 09
Uint16 CONV10:4; // 11:8 Conversion selection 10
Uint16 CONV11:4; // 15:12 Conversion selection 11
};
union ADCCHSELSEQ3_REG{
Uint16 all;
struct ADCCHSELSEQ3_BITS bit;
};
struct ADCCHSELSEQ4_BITS { // bits description
Uint16 CONV12:4; // 3:0 Conversion selection 12
Uint16 CONV13:4; // 7:4 Conversion selection 13
Uint16 CONV14:4; // 11:8 Conversion selection 14
Uint16 CONV15:4; // 15:12 Conversion selection 15
};
union ADCCHSELSEQ4_REG {
Uint16 all;
struct ADCCHSELSEQ4_BITS bit;
};
struct ADCTRL3_BITS { // bits description
Uint16 SMODE_SEL:1; // 0 Sampling mode select
Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
Uint16 ADCPWDN:1; // 5 ADC powerdown
Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCTRL3_REG {
Uint16 all;
struct ADCTRL3_BITS bit;
};
struct ADCST_BITS { // bits description
Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCST_REG {
Uint16 all;
struct ADCST_BITS bit;
};
struct ADCREFSEL_BITS { // bits description
Uint16 rsvd1:14; // 13:0 reserved
Uint16 REF_SEL:2; // 15:14 Reference select
};
union ADCREFSEL_REG {
Uint16 all;
struct ADCREFSEL_BITS bit;
};
struct ADCOFFTRIM_BITS{ // bits description
int16 OFFSET_TRIM:9; // 8:0 Offset Trim
Uint16 rsvd1:7; // 15:9 reserved
};
union ADCOFFTRIM_REG{
Uint16 all;
struct ADCOFFTRIM_BITS bit;
};
struct ADC_REGS {
union ADCTRL1_REG ADCTRL1; //ADC Control 1
union ADCTRL2_REG ADCTRL2; //ADC Control 2
union ADCMAXCONV_REG ADCMAXCONV; //Max conversions
union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1
union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2
union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3
union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4
union ADCASEQSR_REG ADCASEQSR; //Autosequence status register
Uint16 ADCRESULT0; //Conversion Result Buffer 0
Uint16 ADCRESULT1; //Conversion Result Buffer 1
Uint16 ADCRESULT2; //Conversion Result Buffer 2
Uint16 ADCRESULT3; //Conversion Result Buffer 3
Uint16 ADCRESULT4; //Conversion Result Buffer 4
Uint16 ADCRESULT5; //Conversion Result Buffer 5
Uint16 ADCRESULT6; //Conversion Result Buffer 6
Uint16 ADCRESULT7; //Conversion Result Buffer 7
Uint16 ADCRESULT8; //Conversion Result Buffer 8
Uint16 ADCRESULT9; //Conversion Result Buffer 9
Uint16 ADCRESULT10; //Conversion Result Buffer 10
Uint16 ADCRESULT11; //Conversion Result Buffer 11
Uint16 ADCRESULT12; //Conversion Result Buffer 12
Uint16 ADCRESULT13; //Conversion Result Buffer 13
Uint16 ADCRESULT14; //Conversion Result Buffer 14
Uint16 ADCRESULT15; //Conversion Result Buffer 15
union ADCTRL3_REG ADCTRL3; //ADC Control 3
union ADCST_REG ADCST; //ADC Status Register
Uint16 rsvd1;
Uint16 rsvd2;
union ADCREFSEL_REG ADCREFSEL; //Reference Select Register
union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register
};
struct ADC_RESULT_MIRROR_REGS
{
Uint16 ADCRESULT0; // Conversion Result Buffer 0
Uint16 ADCRESULT1; // Conversion Result Buffer 1
Uint16 ADCRESULT2; // Conversion Result Buffer 2
Uint16 ADCRESULT3; // Conversion Result Buffer 3
Uint16 ADCRESULT4; // Conversion Result Buffer 4
Uint16 ADCRESULT5; // Conversion Result Buffer 5
Uint16 ADCRESULT6; // Conversion Result Buffer 6
Uint16 ADCRESULT7; // Conversion Result Buffer 7
Uint16 ADCRESULT8; // Conversion Result Buffer 8
Uint16 ADCRESULT9; // Conversion Result Buffer 9
Uint16 ADCRESULT10; // Conversion Result Buffer 10
Uint16 ADCRESULT11; // Conversion Result Buffer 11
Uint16 ADCRESULT12; // Conversion Result Buffer 12
Uint16 ADCRESULT13; // Conversion Result Buffer 13
Uint16 ADCRESULT14; // Conversion Result Buffer 14
Uint16 ADCRESULT15; // Conversion Result Buffer 15
};
//
// ADC External References & Function Declarations:
//
extern volatile struct ADC_REGS AdcRegs;
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ADC_H definition
//
// End of file
//

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// TI File $Revision: /main/5 $
// Checkin $Date: May 12, 2008 09:34:58 $
//###########################################################################
//
// FILE: DSP2833x_SysCtrl.h
//
// TITLE: DSP2833x Device System Control Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_SYS_CTRL_H
#define DSP2833x_SYS_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//
// System Control Individual Register Bit Definitions
//
//
// PLL Status Register
//
struct PLLSTS_BITS { // bits description
Uint16 PLLLOCKS:1; // 0 PLL lock status
Uint16 rsvd1:1; // 1 reserved
Uint16 PLLOFF:1; // 2 PLL off bit
Uint16 MCLKSTS:1; // 3 Missing clock status bit
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
Uint16 OSCOFF:1; // 5 Oscillator clock off
Uint16 MCLKOFF:1; // 6 Missing clock detect
Uint16 DIVSEL:2; // 7 Divide Select
Uint16 rsvd2:7; // 15:7 reserved
};
union PLLSTS_REG {
Uint16 all;
struct PLLSTS_BITS bit;
};
//
// High speed peripheral clock register bit definitions
//
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
//
// Low speed peripheral clock register bit definitions
//
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
//
// Peripheral clock control register 0 bit definitions
//
struct PCLKCR0_BITS { // bits description
Uint16 rsvd1:2; // 1:0 reserved
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
Uint16 rsvd2:2; // 7:6 reserved
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
};
union PCLKCR0_REG {
Uint16 all;
struct PCLKCR0_BITS bit;
};
//
// Peripheral clock control register 1 bit definitions
//
struct PCLKCR1_BITS { // bits description
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
Uint16 rsvd1:2; // 7:6 reserved
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
};
union PCLKCR1_REG {
Uint16 all;
struct PCLKCR1_BITS bit;
};
//
// Peripheral clock control register 2 bit definitions
//
struct PCLKCR3_BITS { // bits description
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
Uint16 rsvd2:2; // 15:14 reserved
};
union PCLKCR3_REG {
Uint16 all;
struct PCLKCR3_BITS bit;
};
//
// PLL control register bit definitions
//
struct PLLCR_BITS { // bits description
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
Uint16 rsvd1:12; // 15:4 reserved
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
//
// Low Power Mode 0 control register bit definitions
//
struct LPMCR0_BITS { // bits description
Uint16 LPM:2; // 1:0 Set the low power mode
Uint16 QUALSTDBY:6; // 7:2 Qualification
Uint16 rsvd1:7; // 14:8 reserved
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
//
// Dual-mapping configuration register bit definitions
//
struct MAPCNF_BITS { // bits description
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
Uint16 rsvd1:15; // 15:1 reserved
};
union MAPCNF_REG {
Uint16 all;
struct MAPCNF_BITS bit;
};
//
// System Control Register File
//
struct SYS_CTRL_REGS {
Uint16 rsvd1; // 0
union PLLSTS_REG PLLSTS; // 1
Uint16 rsvd2[8]; // 2-9
//
// 10: High-speed peripheral clock pre-scaler
//
union HISPCP_REG HISPCP;
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
Uint16 rsvd3; // 15: reserved
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
union PLLCR_REG PLLCR; // 17: PLL control register
//
// No bit definitions are defined for SCSR because
// a read-modify-write instruction can clear the WDOVERRIDE bit
//
Uint16 SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
//
// No bit definitions are defined for WDCR because
// the proper value must be written to the WDCHK field
// whenever writing to this register.
//
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[4]; // 26-29
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
Uint16 rsvd7[1]; // 31
};
//
// CSM Registers
//
//
// CSM Status & Control register bit definitions
//
struct CSMSCR_BITS { // bit description
Uint16 SECURE:1; // 0 Secure flag
Uint16 rsvd1:14; // 14-1 reserved
Uint16 FORCESEC:1; // 15 Force Secure control bit
};
//
// Allow access to the bit fields or entire register
//
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
//
// CSM Register File
//
struct CSM_REGS {
Uint16 KEY0; // KEY reg bits 15-0
Uint16 KEY1; // KEY reg bits 31-16
Uint16 KEY2; // KEY reg bits 47-32
Uint16 KEY3; // KEY reg bits 63-48
Uint16 KEY4; // KEY reg bits 79-64
Uint16 KEY5; // KEY reg bits 95-80
Uint16 KEY6; // KEY reg bits 111-96
Uint16 KEY7; // KEY reg bits 127-112
Uint16 rsvd1; // reserved
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
Uint16 rsvd4; // reserved
Uint16 rsvd5; // reserved
Uint16 rsvd6; // reserved
Uint16 rsvd7; // reserved
union CSMSCR_REG CSMSCR; // CSM Status & Control register
};
//
// Password locations
//
struct CSM_PWL {
Uint16 PSWD0; // PSWD bits 15-0
Uint16 PSWD1; // PSWD bits 31-16
Uint16 PSWD2; // PSWD bits 47-32
Uint16 PSWD3; // PSWD bits 63-48
Uint16 PSWD4; // PSWD bits 79-64
Uint16 PSWD5; // PSWD bits 95-80
Uint16 PSWD6; // PSWD bits 111-96
Uint16 PSWD7; // PSWD bits 127-112
};
//
// Defines for Flash Registers
//
#define FLASH_SLEEP 0x0000;
#define FLASH_STANDBY 0x0001;
#define FLASH_ACTIVE 0x0003;
//
// Flash Option Register bit definitions
//
struct FOPT_BITS { // bit description
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
Uint16 rsvd:15; // 1-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
//
// Flash Power Modes Register bit definitions
//
struct FPWR_BITS { // bit description
Uint16 PWR:2; // 0-1 Power Mode bits
Uint16 rsvd:14; // 2-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
//
// Flash Status Register bit definitions
//
struct FSTATUS_BITS { // bit description
Uint16 PWRS:2; // 0-1 Power Mode Status bits
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
Uint16 rsvd2:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
//
// Flash Sleep to Standby Wait Counter Register bit definitions
//
struct FSTDBYWAIT_BITS { // bit description
//
// 0-8 Bank/Pump Sleep to Standby Wait Count bits
//
Uint16 STDBYWAIT:9;
Uint16 rsvd:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
//
// Flash Standby to Active Wait Counter Register bit definitions
//
struct FACTIVEWAIT_BITS { // bit description
//
// 0-8 Bank/Pump Standby to Active Wait Count bits
//
Uint16 ACTIVEWAIT:9;
Uint16 rsvd:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
//
// Bank Read Access Wait State Register bit definitions
//
struct FBANKWAIT_BITS { // bit description
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
Uint16 rsvd2:4; // 12-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
//
// OTP Read Access Wait State Register bit definitions
//
struct FOTPWAIT_BITS { // bit description
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
Uint16 rsvd:11; // 5-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT; // Option Register
Uint16 rsvd1; // reserved
union FPWR_REG FPWR; // Power Modes Register
union FSTATUS_REG FSTATUS; // Status Register
//
// Pump/Bank Sleep to Standby Wait State Register
//
union FSTDBYWAIT_REG FSTDBYWAIT;
//
// Pump/Bank Standby to Active Wait State Register
//
union FACTIVEWAIT_REG FACTIVEWAIT;
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
};
//
// System Control External References & Function Declarations
//
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SYS_CTRL_H definition
//
// End of file
//

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// TI File $Revision: /main/4 $
// Checkin $Date: July 27, 2009 13:57:25 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.h
//
// TITLE: DSP2833x Device External Interface Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_XINTF_H
#define DSP2833x_XINTF_H
#ifdef __cplusplus
extern "C" {
#endif
//
// XINTF timing register bit definitions
//
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
//
// XINTF control register bit definitions
//
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 rsvd2:1; // 8 reserved
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd3:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd4:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
//
// XINTF bank switching register bit definitions
//
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
struct XRESET_BITS {
Uint16 XHARDRESET:1;
Uint16 rsvd1:15;
};
union XRESET_REG {
Uint16 all;
struct XRESET_BITS bit;
};
//
// XINTF Register File
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
Uint32 rsvd1[5];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[2];
union XRESET_REG XRESET;
};
//
// XINTF External References & Function Declarations
//
extern volatile struct XINTF_REGS XintfRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//
// End of File
//

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// TI File $Revision: /main/2 $
// Checkin $Date: March 1, 2007 15:57:02 $
//###########################################################################
//
// FILE: DSP2833x_Sci.h
//
// TITLE: DSP2833x Device SCI Register Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_SCI_H
#define DSP2833x_SCI_H
#ifdef __cplusplus
extern "C" {
#endif
//
// SCI Individual Register Bit Definitions
//
//
// SCICCR communication control register bit definitions
//
struct SCICCR_BITS { // bit description
Uint16 SCICHAR:3; // 2:0 Character length control
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
Uint16 LOOPBKENA:1; // 4 Loop Back enable
Uint16 PARITYENA:1; // 5 Parity enable
Uint16 PARITY:1; // 6 Even or Odd Parity
Uint16 STOPBITS:1; // 7 Number of Stop Bits
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICCR_REG {
Uint16 all;
struct SCICCR_BITS bit;
};
//
// SCICTL1 control register 1 bit definitions
//
struct SCICTL1_BITS { // bit description
Uint16 RXENA:1; // 0 SCI receiver enable
Uint16 TXENA:1; // 1 SCI transmitter enable
Uint16 SLEEP:1; // 2 SCI sleep
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
Uint16 rsvd:1; // 4 reserved
Uint16 SWRESET:1; // 5 Software reset
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
Uint16 rsvd1:9; // 15:7 reserved
};
union SCICTL1_REG {
Uint16 all;
struct SCICTL1_BITS bit;
};
//
// SCICTL2 control register 2 bit definitions
//
struct SCICTL2_BITS { // bit description
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
Uint16 rsvd:4; // 5:2 reserved
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
Uint16 TXRDY:1; // 7 Transmitter ready flag
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICTL2_REG {
Uint16 all;
struct SCICTL2_BITS bit;
};
//
// SCIRXST Receiver status register bit definitions
//
struct SCIRXST_BITS { // bit description
Uint16 rsvd:1; // 0 reserved
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
Uint16 PE:1; // 2 Parity error flag
Uint16 OE:1; // 3 Overrun error flag
Uint16 FE:1; // 4 Framing error flag
Uint16 BRKDT:1; // 5 Break-detect flag
Uint16 RXRDY:1; // 6 Receiver ready flag
Uint16 RXERROR:1; // 7 Receiver error flag
};
union SCIRXST_REG {
Uint16 all;
struct SCIRXST_BITS bit;
};
//
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions
//
struct SCIRXBUF_BITS { // bits description
Uint16 RXDT:8; // 7:0 Receive word
Uint16 rsvd:6; // 13:8 reserved
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
};
union SCIRXBUF_REG {
Uint16 all;
struct SCIRXBUF_BITS bit;
};
//
// SCIPRI Priority control register bit definitions
//
struct SCIPRI_BITS { // bit description
Uint16 rsvd:3; // 2:0 reserved
Uint16 FREE:1; // 3 Free emulation suspend mode
Uint16 SOFT:1; // 4 Soft emulation suspend mode
Uint16 rsvd1:3; // 7:5 reserved
};
union SCIPRI_REG {
Uint16 all;
struct SCIPRI_BITS bit;
};
//
// SCI FIFO Transmit register bit definitions
//
struct SCIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
Uint16 SCIFFENA:1; // 14 Enhancement enable
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
};
union SCIFFTX_REG {
Uint16 all;
struct SCIFFTX_BITS bit;
};
//
// SCI FIFO recieve register bit definitions
//
struct SCIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SCIFFRX_REG {
Uint16 all;
struct SCIFFRX_BITS bit;
};
//
// SCI FIFO control register bit definitions
//
struct SCIFFCT_BITS { // bits description
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:5; // 12:8 reserved
Uint16 CDC:1; // 13 Auto baud mode enable
Uint16 ABDCLR:1; // 14 Auto baud clear
Uint16 ABD:1; // 15 Auto baud detect
};
union SCIFFCT_REG {
Uint16 all;
struct SCIFFCT_BITS bit;
};
//
// SCI Register File
//
struct SCI_REGS {
union SCICCR_REG SCICCR; // Communications control register
union SCICTL1_REG SCICTL1; // Control register 1
Uint16 SCIHBAUD; // Baud rate (high) register
Uint16 SCILBAUD; // Baud rate (low) register
union SCICTL2_REG SCICTL2; // Control register 2
union SCIRXST_REG SCIRXST; // Recieve status register
Uint16 SCIRXEMU; // Recieve emulation buffer register
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
Uint16 rsvd1; // reserved
Uint16 SCITXBUF; // Transmit data buffer
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
union SCIFFCT_REG SCIFFCT; // FIFO control register
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
union SCIPRI_REG SCIPRI; // FIFO Priority control
};
//
// SCI External References & Function Declarations
//
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
extern volatile struct SCI_REGS ScicRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SCI_H definition
//
// End of file
//

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#include "main.h"
CPowerOnCheckValue PowerOnCheckValue;
CGeneralOperValue GeneralOperValue;
CSoftTimer SoftTimer[TIMER_MAX];
CWaitTimer WaitTimer[SOFTTIMER_WAIT_MAX];
Uint32 ulSoftClock;
void CInitSystem(void);
void CInitGeneralOperValue(void);
void CInitGpio(void);
void CSystemConfigure(void);
void CMappingInterrupt(void);
void CProcessSoftTimer(void);
Uint16 CPowerOnCheck(void);
void CSoftTimerWorkProcess(void);
Uint16 CIsStatusSoftTimer(Uint16 ucTimerIndex);
void CReloadSoftTimer(Uint16 ucTimerIndex);
void CInitSoftTimers(void);
void CInitSoftTimer(void);
void CConfigSoftTimer(Uint16 ucTimerIndex, Uint32 ulDelay);
void CStartSoftTimer(Uint16 ucTimerIndex);
Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock);
Uint32 CGetSoftClock(void);
void CSOftWaitCountCancel(Uint16 Index);
int main(void)
{
CSetApuOperIndex(APU_OPER_IDX_BOOT);
CInitSystem();
CInitOled();
CSetApuOperIndex(APU_OPER_IDX_INITIAL);
for ( ; ; )
{
CSoftTimerWorkProcess();
if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL)
{
if (OledOperValue.uiProgressDone == 1U)
{
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_INIT, TIME_1SEC) == TIME_OVER)
{
COledBufferReset();
CSetApuOperIndex(APU_OPER_IDX_POST); // Adc 보정완료 이 후 POST 시작
}
}
}
else if (CGetApuOperIndex() == APU_OPER_IDX_POST)
{
if (CPowerOnCheck() == 0U)
{
AdcOperValue.uiOffsetAdjustStart = 1U; // 센서 문제 없을 경우 offset 계산.
COledBufferReset();
CSetApuOperIndex(APU_OPER_IDX_STANDBY);
}
}
else
{
if (GeneralOperValue.uiMaintenence == 0U)
{
// 정비 모드가 꺼져있어야 시퀀스 동작.
//CApuOperProcedure();
CLedControlProcedure();
GPIO_ENGINE_HEATER_CS(GPIO_USER_MODE_1());
GPIO_GLOW_PLUG_CS(GPIO_USER_MODE_1());
GPIO_SOLENOID_CS(GPIO_USER_MODE_1());
GPIO_FUEL_PUMP_CS(GPIO_USER_MODE_1());
GPIO_COOLANT_PUMP_CS(GPIO_USER_MODE_1());
GPIO_FAN1_CS(GPIO_USER_MODE_1());
GPIO_FAN2_CS(GPIO_USER_MODE_1());
}
else
{
CDebugModeProcedure();
}
}
}
}
void CSoftTimerWorkProcess(void)
{
static Uint16 RefeshDelay = 0U;
if (CIsStatusSoftTimer(TIMER_01MS) == SOFTTIMER_TIME_OVER) // Excute Per 1msec
{
CReloadSoftTimer(TIMER_01MS);
if (GeneralOperValue.uiApuState > APU_OPER_IDX_POST) // ADC 오프셋 보정 완료 후 감지
{
CAlarmProcedure();
CDisplayAlarmPopup();
}
if (GeneralOperValue.Maintenence.KeyTest == 0U)
{
// (정비모드:키테스트)가 아니면 키 입력 시작 함.
CKeyCheckProcedure();
CKeyWaitCount();
}
}
if (CIsStatusSoftTimer(TIMER_10MS) == SOFTTIMER_TIME_OVER) // Excute Per 10msec
{
CReloadSoftTimer(TIMER_10MS);
CSendECanDataA();
CSendECanDataB();
COledReflash(0, 0, OLED_WIDTH, OLED_HEIGHT);
if (CGetApuOperIndex() == APU_OPER_IDX_INITIAL)
{
CInitializePage();
}
else
{
if (RefeshDelay == 0U)
{
if (CGetApuOperIndex() == APU_OPER_IDX_POST)
{
CDisplayPostFail();
}
else
{
CSetPage(OledOperValue.uiPageNum);
}
}
RefeshDelay = (RefeshDelay + 1U) % 10U;
}
}
if (CIsStatusSoftTimer(TIMER_100MS) == SOFTTIMER_TIME_OVER) // Excute Per 100msec
{
CReloadSoftTimer(TIMER_100MS);
// 차량제어컴퓨터의 통신 수신이 한번이라도 되었을 경우 통신 타임아웃 체크 시작
if (CApuSystemAlarmCheck() == 0U)
{
// 고장발생시 타임아웃은 체크하지 않는다.
CommCheck.CarComputer = ((GeneralOperValue.Conection.CarComputer == 1U) && (CommCheck.CarComputer < COMM_TIME_OUT_COUNT)) ? (CommCheck.CarComputer + 1U) : 0U;
CommCheck.Gcu = ((GeneralOperValue.Conection.Gcu == 1U) && (CommCheck.Gcu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Gcu + 1U) : 0U;
CommCheck.Ecu = ((GeneralOperValue.Conection.Ecu == 1U) && (CommCheck.Ecu < COMM_TIME_OUT_COUNT)) ? (CommCheck.Ecu + 1U) : 0U;
}
}
if (CIsStatusSoftTimer(TIMER_1SEC) == SOFTTIMER_TIME_OVER) // Excute Per 1s
{
CReloadSoftTimer(TIMER_1SEC);
if (OledOperValue.uiAlreadyAlarm == 1U) // 경고 고장 알람 발생 후 해제 되지 않으면 1분뒤 다시 팝업 하기 위함.
{
if (CSoftWaitCountProcedure(SOFTTIMER_WAIT_POPUP, (TIME_1SEC * 60UL)) == TIME_OVER)
{
OledOperValue.uiAlarmPopCheck = 0U;
OledOperValue.uiAlreadyAlarm = 0U;
}
}
else
{
CSOftWaitCountCancel(SOFTTIMER_WAIT_POPUP);
}
}
}
void CSOftWaitCountCancel(Uint16 Index)
{
WaitTimer[Index].ulCountSoftClock = 0U;
WaitTimer[Index].uiSoftCountTarget = 0U;
}
Uint16 CIsStatusSoftTimer(Uint16 uiTimerIndex)
{
Uint16 isRunning = 1U;
if (SoftTimer[uiTimerIndex].iStart != -1)
{
if (SoftTimer[uiTimerIndex].iStart == 1)
{
if (SoftTimer[uiTimerIndex].ulDecreaseValue == 0U)
{
isRunning = SOFTTIMER_TIME_OVER; // Success
}
else
{
isRunning = SOFTTIMER_RUNNING;
}
}
}
return isRunning;
}
void CReloadSoftTimer(Uint16 uiTimerIndex)
{
if (SoftTimer[uiTimerIndex].iTimer != -1)
{
SoftTimer[uiTimerIndex].ulDecreaseValue = SoftTimer[uiTimerIndex].ulSetValue;
}
}
Uint16 CSoftWaitCountProcedure(Uint16 uiIndex, Uint32 ulWaitTime)
{
Uint16 isCountOver = 0U;
switch (WaitTimer[uiIndex].uiSoftCountTarget)
{
case 0U:
{
WaitTimer[uiIndex].ulCountSoftClock = CGetSoftClock();
WaitTimer[uiIndex].uiSoftCountTarget = 1U;
break;
}
case 1U:
{
if (CSoftClockTimeOut(WaitTimer[uiIndex].ulCountSoftClock, ulWaitTime) == SOFTTIMER_TIME_OVER)
{
WaitTimer[uiIndex].uiSoftCountTarget = 2U;
}
break;
}
default:
{
WaitTimer[uiIndex].ulCountSoftClock = 0U;
WaitTimer[uiIndex].uiSoftCountTarget = 0U;
isCountOver = 1U;
break;
}
}
return isCountOver;
}
Uint16 CSoftClockTimeOut(Uint32 ulStartClock, Uint32 ulTimeOutClock)
{
Uint16 isRunning = 1U;
Uint32 ulCpuClock = CGetSoftClock();
if (((ulCpuClock + SYSTEM_10MIN_TIME - ulStartClock) % SYSTEM_10MIN_TIME) >= ulTimeOutClock)
{
isRunning = 0U;
}
return isRunning;
}
Uint32 CGetSoftClock(void)
{
return ulSoftClock;
}
void CInitSystem(void)
{
DINT;
IER = 0x0000;
IFR = 0x0000;
InitSysCtrl();
CInitGpio(); // GPIO Direction and mux
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, 150.0f, 100.0f); // 100usec
CSystemConfigure();
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
CpuTimer0Regs.TCR.all = 0x4001U; // Use write-only instruction to set TSS bit = 0
}
void CInitGpio(void)
{
EALLOW;
// GPIO MUX Setting
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0x1U; // SCL
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x1U; // SDA
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0x0U; // Enable pull-up (SDAA)
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0x0U; // Enable pull-up (SCLA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0x3U; // Asynch input (SDAA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0x3U; // Asynch input (SCLA)
// GPIO Direction Setting '1' Output, '0' Input
GpioCtrlRegs.GPADIR.bit.GPIO1 = 0U; // GPIO_COOLING_PUMP_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U; // GPIO_FUEL_PUMP_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U; // GPIO_COOLING_FAN1_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U; // GPIO_COOLING_FAN2_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U; // GPIO_GLOW_PLUG_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO6 = 0U; // GPIO_ENGINE_HEATER_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U; // GPIO_STOP_SOLENOID_FUSE
GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U; // GPIO_ECU_ON_OFF
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U; // GPIO_FUEL_PUMP
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U; // GPIO_GLOW_PLUG
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U; // GPIO_STOP_SOLENOID
GpioCtrlRegs.GPADIR.bit.GPIO24 = 0U; // GPIO_ENGINE_HEATER
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0U; // CPU_SW_MODE_RESET
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0U; // CPU_SW_MODE_ENT
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0U; // CPU_SW_DOWN
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0U; // CPU_SW_UP
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0U; // CPU_SW_EMERGENCY
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0U; // CPU_SW_START
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0U; // CPU_SW_PWR
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1U; // GPIO_CPU_LED_SWITCH3
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U; // GPIO_CPU_LED_SWITCH2
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1U; // GPIO_CPU_LED_SWITCH1
GpioCtrlRegs.GPADIR.bit.GPIO26 = 1U; // GPIO_FUEL_PUMP_CS
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1U; // GPIO_GLOW_PLUG_CS
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1U; // GPIO_OLED_CS
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1U; // GPIO_OLED_RESET
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U; // GPIO_STOP_SOLENOID_CS
GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U; // GPIO_ENGINE_HEATER_CS
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U; // GPIO_COOLING_FAN1_CS
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U; // GPIO_COOLING_FAN2_CS
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U; // GPIO_COOLING_PUMP_CS
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1U; // GPIO_FAULT_CMD_CS
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1U; // GPIO_EMERGENCY_CMD_CS
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1U; // GPIO_STOP_CMD_CS
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U; // GPIO_START_CMD_CS
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1U; // GPIO_POWER_HOLD
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1U; // GPIO_CPU_LED_COM_FAULT
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1U; // GPIO_CPU_LED_COM_RUN
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 1U; // GPIO_CPU_LED_COM_STA
// GPAQSEL : 0b00 - Synchronize to SYSCLKOUT, 0b01 - Qualification 3 sample, 0b10 - Qualification 6 sample, 0b11 - Asynchronous
GpioCtrlRegs.GPAQSEL1.all = 0x0000U; // GPIO0-GPIO15 Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.all = 0x0000U; // GPIO16-GPIO31 Synch to SYSCLKOUT
GpioCtrlRegs.GPBQSEL1.all = 0x0000U; // GPIO32-GPIO47 Synch to SYSCLKOUT
GpioCtrlRegs.GPBQSEL2.all = 0x0000U; // GPIO48-GPIO63 Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 1U; // 3 Clk Sampling
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 1U; // 3 Clk Sampling
// Gpio Default Value Initial
GPIO_POWER_HOLD(1);
GPIO_CPU_LED_COM_FAULT_N(1);
GPIO_CPU_LED_COM_RUN_N(1);
GPIO_CPU_LED_COM_STA_N(1);
EDIS;
}
void CActiveChipSelect(Uint16 Active)
{
if (Active == 0U)
{
// 비상정지 상황에서는 모든 CS를 OFF한다. (0 - CS OFF, 1 - CS ON)
GPIO_ENGINE_HEATER_CS(0);
GPIO_GLOW_PLUG_CS(0);
GPIO_SOLENOID_CS(0);
GPIO_FUEL_PUMP_CS(0);
GPIO_COOLANT_PUMP_CS(0);
GPIO_FAN1_CS(0);
GPIO_FAN2_CS(0);
}
else
{
// 운영 상태에서는 EcuSignal의 상태를 확인하고 엔진히터, 글로우플러그, 솔레노이드, 연료펌프를 동작한다.
// 0 - CS OFF, 1 - CS ON
GPIO_ENGINE_HEATER_CS(GPIO_ENGINE_HEATER());
GPIO_GLOW_PLUG_CS(GPIO_GLOW_PLUG());
GPIO_SOLENOID_CS(GPIO_SOLENOID());
GPIO_FUEL_PUMP_CS(GPIO_FUEL_PUMP());
GPIO_COOLANT_PUMP_CS(1);
GPIO_FAN1_CS(1);
GPIO_FAN2_CS(1);
}
}
static interrupt void CMainTimer0Interrupt(void)
{
// Per 100uSec
DINT;
ulSoftClock = (ulSoftClock + 1U) % SYSTEM_10MIN_TIME;
CProcessSoftTimer();
// Do Something
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x01U; // Adc Read Start
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
EINT;
}
void CSystemConfigure(void)
{
CMappingInterrupt();
CInitGeneralOperValue();
CInitAdc();
CInitEcan();
CInitXintf();
CInitSoftTimers();
CInitKeyOperValue();
}
void CInitGeneralOperValue(void)
{
(void) memset(&GeneralOperValue, 0, sizeof(CGeneralOperValue));
(void) memset(&PowerOnCheckValue, 0x1FF, sizeof(CPowerOnCheckValue)); // Set All bit 1
GeneralOperValue.uiPassword[OLED_PASS_DIGIT_1] = 0;
GeneralOperValue.uiPassword[OLED_PASS_DIGIT_2] = 0;
GeneralOperValue.uiPassword[OLED_PASS_DIGIT_3] = 0;
GeneralOperValue.uiPassword[OLED_PASS_DIGIT_4] = 0;
}
void CMappingInterrupt(void)
{
EALLOW;
// Interrupt Vector Remapping
PieCtrlRegs.PIEIER1.bit.INTx7 = 0x1U; // TINT0
PieCtrlRegs.PIEIER1.bit.INTx6 = 0x1U; // ADC
PieCtrlRegs.PIEIER9.bit.INTx5 = 0x1U; // ECAN0INTA
PieCtrlRegs.PIEIER9.bit.INTx7 = 0x1U; // ECAN0INTB
PieVectTable.TINT0 = &CMainTimer0Interrupt;
PieVectTable.ECAN0INTA = &CECanInterruptA;
PieVectTable.ECAN0INTB = &CECanInterruptB;
PieVectTable.ADCINT = &CAdcInterrupt;
IER = M_INT1 | M_INT9;
EDIS;
}
void CProcessSoftTimer(void)
{
Uint16 i;
for (i = 0U; i < TIMER_MAX; i++)
{
if (SoftTimer[i].iTimer != -1)
{
if (SoftTimer[i].iStart == 1)
{
if (SoftTimer[i].ulDecreaseValue > 0UL)
{
SoftTimer[i].ulDecreaseValue--;
}
}
}
}
}
void CInitSoftTimers(void)
{
CInitSoftTimer();
CConfigSoftTimer(TIMER_01MS, TIME_01MS);
CConfigSoftTimer(TIMER_10MS, TIME_10MS);
CConfigSoftTimer(TIMER_20MS, TIME_20MS);
CConfigSoftTimer(TIMER_50MS, TIME_50MS);
CConfigSoftTimer(TIMER_100MS, TIME_100MS);
CConfigSoftTimer(TIMER_500MS, TIME_500MS);
CConfigSoftTimer(TIMER_1SEC, TIME_1SEC);
CStartSoftTimer(TIMER_01MS);
CStartSoftTimer(TIMER_10MS);
CStartSoftTimer(TIMER_20MS);
CStartSoftTimer(TIMER_50MS);
CStartSoftTimer(TIMER_100MS);
CStartSoftTimer(TIMER_500MS);
CStartSoftTimer(TIMER_1SEC);
}
void CStartSoftTimer(Uint16 ucTimerIndex)
{
if (SoftTimer[ucTimerIndex].iTimer != -1)
{
SoftTimer[ucTimerIndex].iStart = 1;
}
}
void CInitSoftTimer(void)
{
Uint16 i;
(void) memset(&SoftTimer, 0, sizeof(SoftTimer));
(void) memset(&WaitTimer, 0, sizeof(WaitTimer));
for (i = 0; i < TIMER_MAX; i++)
{
SoftTimer[i].iTimer = -1;
}
}
void CConfigSoftTimer(Uint16 TimerIndex, Uint32 Delay)
{
SoftTimer[TimerIndex].iTimer = (int16) TimerIndex;
SoftTimer[TimerIndex].ulSetValue = Delay;
SoftTimer[TimerIndex].ulDecreaseValue = Delay;
SoftTimer[TimerIndex].iStart = 0;
}
Uint16 CPowerOnCheck(void)
{
// 통신 수신 확인은 CAN 수신 인터럽트 발생 시, 체크
Uint16 retValue = (*(Uint16*)&PowerOnCheckValue) & 0x7FU;
PowerOnCheckValue.EngineHeaterSensor = ((Adc_EngineHeater_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_EngineHeater_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.GlowPlugSensor = ((Adc_GlowPlug_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_GlowPlug_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.SolenoidSensor = ((Adc_Solenoid_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Solenoid_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.FuelPumpSensor = ((Adc_FuelPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_FuelPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.CoolantPumpSensor = ((Adc_CoolantPump_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_CoolantPump_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.Fan1Sensor = ((Adc_Fan1_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan1_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
PowerOnCheckValue.Fan2Sensor = ((Adc_Fan2_I.iAdcValue > SENSOR_MIN_LIMIT) && (Adc_Fan2_I.iAdcValue < SENSOR_MAX_LIMIT)) ? 0U : 1U;
return retValue; // '0' 정상
}

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@@ -0,0 +1,465 @@
// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:52:10 $
//###########################################################################
//
// FILE: DSP2833x_EPwm.h
//
// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_EPWM_H
#define DSP2833x_EPWM_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Time base control register bit definitions
//
struct TBCTL_BITS { // bits description
Uint16 CTRMODE:2; // 1:0 Counter Mode
Uint16 PHSEN:1; // 2 Phase load enable
Uint16 PRDLD:1; // 3 Active period load
Uint16 SYNCOSEL:2; // 5:4 Sync output select
Uint16 SWFSYNC:1; // 6 Software force sync pulse
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
Uint16 PHSDIR:1; // 13 Phase Direction
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union TBCTL_REG {
Uint16 all;
struct TBCTL_BITS bit;
};
//
// Time base status register bit definitions
//
struct TBSTS_BITS { // bits description
Uint16 CTRDIR:1; // 0 Counter direction status
Uint16 SYNCI:1; // 1 External input sync status
Uint16 CTRMAX:1; // 2 Counter max latched status
Uint16 rsvd1:13; // 15:3 reserved
};
union TBSTS_REG {
Uint16 all;
struct TBSTS_BITS bit;
};
//
// Compare control register bit definitions
//
struct CMPCTL_BITS { // bits description
Uint16 LOADAMODE:2; // 0:1 Active compare A
Uint16 LOADBMODE:2; // 3:2 Active compare B
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
Uint16 rsvd1:1; // 5 reserved
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
Uint16 rsvd2:1; // 7 reserved
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
Uint16 rsvd3:6; // 15:10 reserved
};
union CMPCTL_REG {
Uint16 all;
struct CMPCTL_BITS bit;
};
//
// Action qualifier register bit definitions
//
struct AQCTL_BITS { // bits description
Uint16 ZRO:2; // 1:0 Action Counter = Zero
Uint16 PRD:2; // 3:2 Action Counter = Period
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
Uint16 rsvd:4; // 15:12 reserved
};
union AQCTL_REG {
Uint16 all;
struct AQCTL_BITS bit;
};
//
// Action qualifier SW force register bit definitions
//
struct AQSFRC_BITS { // bits description
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
Uint16 OTSFA:1; // 2 One-time SW Force A output
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
Uint16 OTSFB:1; // 5 One-time SW Force A output
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
Uint16 rsvd1:8; // 15:8 reserved
};
union AQSFRC_REG {
Uint16 all;
struct AQSFRC_BITS bit;
};
//
// Action qualifier continuous SW force register bit definitions
//
struct AQCSFRC_BITS { // bits description
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
Uint16 rsvd1:12; // 15:4 reserved
};
union AQCSFRC_REG {
Uint16 all;
struct AQCSFRC_BITS bit;
};
//
// As of version 1.1
// Changed the MODE bit-field to OUT_MODE
// Added the bit-field IN_MODE
// This corresponds to changes in silicon as of F2833x devices
// Rev A silicon.
//
//
// Dead-band generator control register bit definitions
//
struct DBCTL_BITS { // bits description
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
Uint16 POLSEL:2; // 3:2 Polarity Select Control
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
Uint16 rsvd1:10; // 15:4 reserved
};
union DBCTL_REG {
Uint16 all;
struct DBCTL_BITS bit;
};
//
// Trip zone select register bit definitions
//
struct TZSEL_BITS { // bits description
Uint16 CBC1:1; // 0 TZ1 CBC select
Uint16 CBC2:1; // 1 TZ2 CBC select
Uint16 CBC3:1; // 2 TZ3 CBC select
Uint16 CBC4:1; // 3 TZ4 CBC select
Uint16 CBC5:1; // 4 TZ5 CBC select
Uint16 CBC6:1; // 5 TZ6 CBC select
Uint16 rsvd1:2; // 7:6 reserved
Uint16 OSHT1:1; // 8 One-shot TZ1 select
Uint16 OSHT2:1; // 9 One-shot TZ2 select
Uint16 OSHT3:1; // 10 One-shot TZ3 select
Uint16 OSHT4:1; // 11 One-shot TZ4 select
Uint16 OSHT5:1; // 12 One-shot TZ5 select
Uint16 OSHT6:1; // 13 One-shot TZ6 select
Uint16 rsvd2:2; // 15:14 reserved
};
union TZSEL_REG {
Uint16 all;
struct TZSEL_BITS bit;
};
//
// Trip zone control register bit definitions
//
struct TZCTL_BITS { // bits description
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
Uint16 rsvd:12; // 15:4 reserved
};
union TZCTL_REG {
Uint16 all;
struct TZCTL_BITS bit;
};
//
// Trip zone control register bit definitions
//
struct TZEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
Uint16 rsvd2:13; // 15:3 reserved
};
union TZEINT_REG {
Uint16 all;
struct TZEINT_BITS bit;
};
//
// Trip zone flag register bit definitions
//
struct TZFLG_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFLG_REG {
Uint16 all;
struct TZFLG_BITS bit;
};
//
// Trip zone flag clear register bit definitions
//
struct TZCLR_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZCLR_REG {
Uint16 all;
struct TZCLR_BITS bit;
};
//
// Trip zone flag force register bit definitions
//
struct TZFRC_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFRC_REG {
Uint16 all;
struct TZFRC_BITS bit;
};
//
// Event trigger select register bit definitions
//
struct ETSEL_BITS { // bits description
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
Uint16 INTEN:1; // 3 EPWMxINTn Enable
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
};
union ETSEL_REG {
Uint16 all;
struct ETSEL_BITS bit;
};
//
// Event trigger pre-scale register bit definitions
//
struct ETPS_BITS { // bits description
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
};
union ETPS_REG {
Uint16 all;
struct ETPS_BITS bit;
};
//
// Event trigger Flag register bit definitions
//
struct ETFLG_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Flag
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFLG_REG {
Uint16 all;
struct ETFLG_BITS bit;
};
//
// Event trigger Clear register bit definitions
//
struct ETCLR_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Clear
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
Uint16 rsvd2:12; // 15:4 reserved
};
union ETCLR_REG {
Uint16 all;
struct ETCLR_BITS bit;
};
//
// Event trigger Force register bit definitions
//
struct ETFRC_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Force
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Force
Uint16 SOCB:1; // 3 EPWMxSOCB Force
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFRC_REG {
Uint16 all;
struct ETFRC_BITS bit;
};
//
// PWM chopper control register bit definitions
//
struct PCCTL_BITS { // bits description
Uint16 CHPEN:1; // 0 PWM chopping enable
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
Uint16 rsvd1:5; // 15:11 reserved
};
union PCCTL_REG {
Uint16 all;
struct PCCTL_BITS bit;
};
struct HRCNFG_BITS { // bits description
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
Uint16 CTLMODE:1; // 2 Control mode Select Bit
Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
Uint16 rsvd1:12; // 15:4 reserved
};
union HRCNFG_REG {
Uint16 all;
struct HRCNFG_BITS bit;
};
struct TBPHS_HRPWM_REG { //bits description
Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits)
Uint16 TBPHS; //31:16 Phase offset register
};
union TBPHS_HRPWM_GROUP {
Uint32 all;
struct TBPHS_HRPWM_REG half;
};
struct CMPA_HRPWM_REG { // bits description
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
Uint16 CMPA; // 31:16 Compare A reg
};
union CMPA_HRPWM_GROUP {
Uint32 all;
struct CMPA_HRPWM_REG half;
};
struct EPWM_REGS {
union TBCTL_REG TBCTL; //
union TBSTS_REG TBSTS; //
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
Uint16 TBCTR; // Counter
Uint16 TBPRD; // Period register set
Uint16 rsvd1; //
union CMPCTL_REG CMPCTL; // Compare control
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
Uint16 CMPB; // Compare B reg
union AQCTL_REG AQCTLA; // Action qual output A
union AQCTL_REG AQCTLB; // Action qual output B
union AQSFRC_REG AQSFRC; // Action qual SW force
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
union DBCTL_REG DBCTL; // Dead-band control
Uint16 DBRED; // Dead-band rising edge delay
Uint16 DBFED; // Dead-band falling edge delay
union TZSEL_REG TZSEL; // Trip zone select
Uint16 rsvd2;
union TZCTL_REG TZCTL; // Trip zone control
union TZEINT_REG TZEINT; // Trip zone interrupt enable
union TZFLG_REG TZFLG; // Trip zone interrupt flags
union TZCLR_REG TZCLR; // Trip zone clear
union TZFRC_REG TZFRC; // Trip zone force interrupt
union ETSEL_REG ETSEL; // Event trigger selection
union ETPS_REG ETPS; // Event trigger pre-scaler
union ETFLG_REG ETFLG; // Event trigger flags
union ETCLR_REG ETCLR; // Event trigger clear
union ETFRC_REG ETFRC; // Event trigger force
union PCCTL_REG PCCTL; // PWM chopper control
Uint16 rsvd3; //
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
};
//
// External References & Function Declarations
//
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
extern volatile struct EPWM_REGS EPwm5Regs;
extern volatile struct EPWM_REGS EPwm6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EPWM_H definition
//
// End of file
//

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// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:45:37 $
//###########################################################################
//
// FILE: DSP2833x_DefaultIsr.h
//
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
// $Copyright:
// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DSP2833x_DEFAULT_ISR_H
#define DSP2833x_DEFAULT_ISR_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Default Interrupt Service Routine Declarations:
//
// The following function prototypes are for the
// default ISR routines used with the default PIE vector table.
// This default vector table is found in the DSP2833x_PieVect.h
// file.
//
//
// Non-Peripheral Interrupts
//
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
interrupt void INT14_ISR(void); // CPU-Timer2
interrupt void DATALOG_ISR(void); // Datalogging interrupt
interrupt void RTOSINT_ISR(void); // RTOS interrupt
interrupt void EMUINT_ISR(void); // Emulation interrupt
interrupt void NMI_ISR(void); // Non-maskable interrupt
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
interrupt void USER1_ISR(void); // User Defined trap 1
interrupt void USER2_ISR(void); // User Defined trap 2
interrupt void USER3_ISR(void); // User Defined trap 3
interrupt void USER4_ISR(void); // User Defined trap 4
interrupt void USER5_ISR(void); // User Defined trap 5
interrupt void USER6_ISR(void); // User Defined trap 6
interrupt void USER7_ISR(void); // User Defined trap 7
interrupt void USER8_ISR(void); // User Defined trap 8
interrupt void USER9_ISR(void); // User Defined trap 9
interrupt void USER10_ISR(void); // User Defined trap 10
interrupt void USER11_ISR(void); // User Defined trap 11
interrupt void USER12_ISR(void); // User Defined trap 12
//
// Group 1 PIE Interrupt Service Routines
//
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
interrupt void XINT1_ISR(void); // External interrupt 1
interrupt void XINT2_ISR(void); // External interrupt 2
interrupt void ADCINT_ISR(void); // ADC
interrupt void TINT0_ISR(void); // Timer 0
interrupt void WAKEINT_ISR(void); // WD
//
// Group 2 PIE Interrupt Service Routines
//
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
//
// Group 3 PIE Interrupt Service Routines
//
interrupt void EPWM1_INT_ISR(void); // EPWM-1
interrupt void EPWM2_INT_ISR(void); // EPWM-2
interrupt void EPWM3_INT_ISR(void); // EPWM-3
interrupt void EPWM4_INT_ISR(void); // EPWM-4
interrupt void EPWM5_INT_ISR(void); // EPWM-5
interrupt void EPWM6_INT_ISR(void); // EPWM-6
//
// Group 4 PIE Interrupt Service Routines
//
interrupt void ECAP1_INT_ISR(void); // ECAP-1
interrupt void ECAP2_INT_ISR(void); // ECAP-2
interrupt void ECAP3_INT_ISR(void); // ECAP-3
interrupt void ECAP4_INT_ISR(void); // ECAP-4
interrupt void ECAP5_INT_ISR(void); // ECAP-5
interrupt void ECAP6_INT_ISR(void); // ECAP-6
//
// Group 5 PIE Interrupt Service Routines
//
interrupt void EQEP1_INT_ISR(void); // EQEP-1
interrupt void EQEP2_INT_ISR(void); // EQEP-2
//
// Group 6 PIE Interrupt Service Routines
//
interrupt void SPIRXINTA_ISR(void); // SPI-A
interrupt void SPITXINTA_ISR(void); // SPI-A
interrupt void MRINTA_ISR(void); // McBSP-A
interrupt void MXINTA_ISR(void); // McBSP-A
interrupt void MRINTB_ISR(void); // McBSP-B
interrupt void MXINTB_ISR(void); // McBSP-B
//
// Group 7 PIE Interrupt Service Routines
//
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
//
// Group 8 PIE Interrupt Service Routines
//
interrupt void I2CINT1A_ISR(void); // I2C-A
interrupt void I2CINT2A_ISR(void); // I2C-A
interrupt void SCIRXINTC_ISR(void); // SCI-C
interrupt void SCITXINTC_ISR(void); // SCI-C
//
// Group 9 PIE Interrupt Service Routines
//
interrupt void SCIRXINTA_ISR(void); // SCI-A
interrupt void SCITXINTA_ISR(void); // SCI-A
interrupt void SCIRXINTB_ISR(void); // SCI-B
interrupt void SCITXINTB_ISR(void); // SCI-B
interrupt void ECAN0INTA_ISR(void); // eCAN-A
interrupt void ECAN1INTA_ISR(void); // eCAN-A
interrupt void ECAN0INTB_ISR(void); // eCAN-B
interrupt void ECAN1INTB_ISR(void); // eCAN-B
//
// Group 10 PIE Interrupt Service Routines
//
//
// Group 11 PIE Interrupt Service Routines
//
//
// Group 12 PIE Interrupt Service Routines
//
interrupt void XINT3_ISR(void); // External interrupt 3
interrupt void XINT4_ISR(void); // External interrupt 4
interrupt void XINT5_ISR(void); // External interrupt 5
interrupt void XINT6_ISR(void); // External interrupt 6
interrupt void XINT7_ISR(void); // External interrupt 7
interrupt void LVF_ISR(void); // Latched overflow flag
interrupt void LUF_ISR(void); // Latched underflow flag
//
// Catch-all for Reserved Locations For testing purposes
//
interrupt void PIE_RESERVED(void); // Reserved for test
interrupt void rsvd_ISR(void); // for test
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEFAULT_ISR_H definition
//
// End of file
//

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#ifndef SOURCE_MAIN_H_
#define SOURCE_MAIN_H_
typedef signed char int8;
typedef unsigned char Uint8;
#include <string.h>
#include "DSP28x_Project.h"
#include "DSP2833x_Device.h"
#include "DSP2833x_EPwm_defines.h"
#include "DSP2833x_I2c_defines.h"
#include "State.h"
#include "Oper.h"
#include "Display.h"
#include "Comm.h"
// Key Input Port (Lo Active)
#define GPIO_KEY_UP() (!GpioDataRegs.GPBDAT.bit.GPIO39)
#define GPIO_KEY_DOWN() (!GpioDataRegs.GPADAT.bit.GPIO31)
#define GPIO_KEY_ENTER() (!GpioDataRegs.GPADAT.bit.GPIO30)
#define GPIO_KEY_MENU() (!GpioDataRegs.GPADAT.bit.GPIO29)
#define GPIO_KEY_POWER() (!GpioDataRegs.GPCDAT.bit.GPIO67)
#define GPIO_KEY_START() (!GpioDataRegs.GPCDAT.bit.GPIO66)
#define GPIO_KEY_EMERGENCY() (!GpioDataRegs.GPCDAT.bit.GPIO64)
// 전류센서 CS가 활성되었을 때 FUSE 핀이 high면 그 쪽 라인은 문제 발생된 것임(ips 칩 또는 fuse)
#define GPIO_ENGINE_HEATER_FUSE() (GpioDataRegs.GPADAT.bit.GPIO6)
#define GPIO_GLOW_PLUG_FUSE() (GpioDataRegs.GPADAT.bit.GPIO5)
#define GPIO_SOLENOID_FUSE() (GpioDataRegs.GPADAT.bit.GPIO7)
#define GPIO_FUEL_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO2)
#define GPIO_COOLANT_PUMP_FUSE() (GpioDataRegs.GPADAT.bit.GPIO1)
#define GPIO_FAN1_FUSE() (GpioDataRegs.GPADAT.bit.GPIO3)
#define GPIO_FAN2_FUSE() (GpioDataRegs.GPADAT.bit.GPIO4)
#define GPIO_ECU_ON_OFF() (GpioDataRegs.GPADAT.bit.GPIO8)
#define GPIO_FUEL_PUMP() (GpioDataRegs.GPADAT.bit.GPIO9)
#define GPIO_GLOW_PLUG() (GpioDataRegs.GPADAT.bit.GPIO10)
#define GPIO_SOLENOID() (GpioDataRegs.GPADAT.bit.GPIO11)
#define GPIO_ENGINE_HEATER() (GpioDataRegs.GPADAT.bit.GPIO24)
#define GPIO_USER_MODE_1() (!GpioDataRegs.GPCDAT.bit.GPIO81)
#define GPIO_USER_MODE_2() (!GpioDataRegs.GPCDAT.bit.GPIO82)
#define GPIO_USER_MODE_3() (!GpioDataRegs.GPCDAT.bit.GPIO83)
#define GPIO_ENGINE_HEATER_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO49)
#define GPIO_GLOW_PLUG_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO27)
#define GPIO_SOLENOID_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO48)
#define GPIO_FUEL_PUMP_CS_READ() (GpioDataRegs.GPADAT.bit.GPIO26)
#define GPIO_COOLANT_PUMP_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO52)
#define GPIO_FAN1_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO50)
#define GPIO_FAN2_CS_READ() (GpioDataRegs.GPBDAT.bit.GPIO51)
// ChipSelect Port
#define GPIO_ENGINE_HEATER_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO49 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1));
#define GPIO_GLOW_PLUG_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO27 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO27 = 1));
#define GPIO_SOLENOID_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO48 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1));
#define GPIO_FUEL_PUMP_CS(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO26 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO26 = 1));
#define GPIO_COOLANT_PUMP_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO52 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO52 = 1));
#define GPIO_FAN1_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO50 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1));
#define GPIO_FAN2_CS(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO51 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO51 = 1));
// Pannel LED Port
#define GPIO_CPU_LED_STOP(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO12 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO12 = 1));
#define GPIO_CPU_LED_FAULT(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO14 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO14 = 1));
#define GPIO_CPU_LED_OPERATION(x) ((x) ? (GpioDataRegs.GPASET.bit.GPIO13 = 1) : (GpioDataRegs.GPACLEAR.bit.GPIO13 = 1));
#define GPIO_OLED_RESET(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO37 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO37 = 1));
#define GPIO_FAULT_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO55 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO55 = 1));
#define GPIO_EMERGENCY_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO56 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO56 = 1));
#define GPIO_STOP_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO57 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1));
#define GPIO_START_CMD(x) ((x) ? (GpioDataRegs.GPBSET.bit.GPIO58 = 1) : (GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1));
#define GPIO_POWER_HOLD(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO65 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO65 = 1));
#define GPIO_CPU_LED_COM_FAULT_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO68 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO68 = 1));
#define GPIO_CPU_LED_COM_RUN_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO69 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO69 = 1));
#define GPIO_CPU_LED_COM_STA_N(x) ((x) ? (GpioDataRegs.GPCSET.bit.GPIO70 = 1) : (GpioDataRegs.GPCCLEAR.bit.GPIO70 = 1));
/* Comment Description
* [!] : 변경시 주의
* [?] : 결정이 필요
* [*] : 주의보다 더 엄중
*/
/* Firmware 버전 (Semantic Versioning) */
#define FIRMWARE_VERSION_MAJOR (0) // 하위버전과 호환 되지 않는 변화가 생길 때 증가, 대대적인 변화가 있을 때
#define FIRMWARE_VERSION_MINOR (0) // 하위버전과 호환 되면서 새로운 기능이 생길 때 증가, 기존 기능이 변경되거나 사용 방법이 변경 될 때
#define FIRMWARE_VERSION_PATCH (5) // 하위버전과 호환 되면서 버그 수정, 기능적으로 변경된것을 알아차리지 못할 정도의 소소한 변경이 있을 때
/* Version History
* [0.0.1] : DCU 프로젝트 생성
* [0.0.2] : DCU 펌웨어 탑재 성공
* [0.0.3] : OLED XINTF(BUS) 방식 드라이브단 구현
* [0.0.4] : OLED 표시 화면 구현
* [0.0.5] : CAN-B 확인 및 맵핑
*/
#define DEBUG_MENU_PASSWORD {0,0,0,0}
#define ENABLED (1)
#define DISABLED (!ENABLED)
/*
Timer Clock Per 100us
*/
#define SYSTEM_10MIN_TIME (6000000UL)
#define TIME_01MS (10U)
#define TIME_10MS (100U)
#define TIME_20MS (200U)
#define TIME_50MS (500U)
#define TIME_100MS (1000U)
#define TIME_500MS (5000U)
#define TIME_1SEC (10000U)
// 전류센서 0A 기준값 450(0.33V), 허용 오차 +/- 150
#define SENSOR_OFFSET_REF 450
#define SENSOR_TOLERANCE 150
#define SENSOR_MIN_LIMIT (SENSOR_OFFSET_REF - SENSOR_TOLERANCE) // 300
#define SENSOR_MAX_LIMIT (SENSOR_OFFSET_REF + SENSOR_TOLERANCE) // 600
#define TIME_OVER (1U)
#define ABS(x) ((x) < 0 ? -(x) : (x))
enum
{
TIMER_01MS = 0,
TIMER_10MS,
TIMER_20MS,
TIMER_50MS,
TIMER_100MS,
TIMER_500MS,
TIMER_1SEC,
TIMER_MAX
};
enum
{
SOFTTIMER_TIME_OVER = 0,
SOFTTIMER_RUNNING,
SOFTTIMER_PAUSE,
SOFTTIMER_DONT_EXIST
};
enum
{
SOFTTIMER_WAIT_INIT = 0,
SOFTTIMER_WAIT_POPUP,
SOFTTIMER_WAIT_APU_STOP,
SOFTTIMER_WAIT_SHUTDOWN,
SOFTTIMER_WAIT_MAX
};
typedef struct ClassSoftTimer
{
Uint32 ulSetValue;
Uint32 ulDecreaseValue;
int16 iTimer;
int16 iStart;
} CSoftTimer;
typedef struct ClassWaitTimer
{
Uint32 ulCountSoftClock;
Uint16 uiSoftCountTarget;
} CWaitTimer;
typedef struct ClassPowerOnCheckValue
{
Uint16 EngineHeaterSensor : 1;
Uint16 GlowPlugSensor : 1;
Uint16 SolenoidSensor : 1;
Uint16 FuelPumpSensor : 1;
Uint16 CoolantPumpSensor : 1;
Uint16 Fan1Sensor : 1;
Uint16 Fan2Sensor : 1;
} CPowerOnCheckValue;
typedef struct ClassGeneralOperValue
{
Uint16 uiPassword[4];
Uint16 uiAlarmOccured;
Uint16 uiApuState;
Uint16 uiAlarmReset;
Uint16 uiMaintenence;
Uint32 ulTotalOperationHour;
struct
{
Uint16 PlayCmd : 4;
Uint16 rsvd_padding : 4;
} GcuCommand;
struct
{
Uint16 EngineStart : 1;
Uint16 EngineStop : 1;
Uint16 rsvd : 2;
Uint16 RpmSetPoint : 2;
Uint16 Override : 1;
Uint16 Emergency : 1;
} EcuCommand;
struct
{
Uint16 CarComputer : 1;
Uint16 Gcu : 1;
Uint16 Ecu : 1;
} Conection;
struct
{
Uint16 ManualCranking : 1;
Uint16 LampTest : 1;
Uint16 KeyTest : 1;
} Maintenence;
} CGeneralOperValue;
Uint16 CSoftWaitCountProcedure(Uint16 ucIndex, Uint32 ulWaitTime);
void CActiveChipSelect(Uint16 Active);
extern CGeneralOperValue GeneralOperValue;
extern CPowerOnCheckValue PowerOnCheckValue;
#endif /* SOURCE_MAIN_H_ */

289
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@@ -0,0 +1,289 @@
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